U.S. patent application number 10/193176 was filed with the patent office on 2002-12-05 for semiconductor device having a nitride barrier for preventing formation of structural defects.
This patent application is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Kobayashi, Kiyoteru, Tsuji, Naoki.
Application Number | 20020179996 10/193176 |
Document ID | / |
Family ID | 17891758 |
Filed Date | 2002-12-05 |
United States Patent
Application |
20020179996 |
Kind Code |
A1 |
Tsuji, Naoki ; et
al. |
December 5, 2002 |
Semiconductor device having a nitride barrier for preventing
formation of structural defects
Abstract
Providing a method of producing a semiconductor device and a
structure of the semiconductor device employing a trench isolation
structure for isolating semiconductor elements wherein volumetric
expansion of a trench-filling material due to oxidation process
after forming the trench isolation structure is controlled thereby
making it possible to prevent deterioration of the electrical
characteristics of the semiconductor device. A nitriding treatment
is applied to the trench surface of the silicon substrate after
forming the trench by etching, thereby to form a thin nitride layer
having a better effect of preventing oxidation in the interface of
silicon.
Inventors: |
Tsuji, Naoki; (Tokyo,
JP) ; Kobayashi, Kiyoteru; (Tokyo, JP) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Assignee: |
Mitsubishi Denki Kabushiki
Kaisha
2-3, Marunouchi 2-chome, Chiyoda-ku
Tokyo
JP
100-8310
|
Family ID: |
17891758 |
Appl. No.: |
10/193176 |
Filed: |
July 12, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10193176 |
Jul 12, 2002 |
|
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|
09352401 |
Jul 14, 1999 |
|
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6441444 |
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Current U.S.
Class: |
257/510 ;
257/499; 257/506; 257/E21.546; 257/E21.616 |
Current CPC
Class: |
H01L 21/8234 20130101;
H01L 21/76224 20130101 |
Class at
Publication: |
257/510 ;
257/499; 257/506 |
International
Class: |
H01L 029/00 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 22, 1998 |
JP |
P 10-301010 |
Claims
What is claimed is:
1. A semiconductor, comprising: (a) a substrate having a surface,
said surface being formed with a groove to define a first region on
one side of said groove and a second region on the opposite side of
said groove; (b) first and second transistors provided in said
first and second region, respectively, each of said first and
second transistors having a gate oxidation film provide on said
surface, a gate electrode provided on said gate oxidation film, and
impurity-doped layers positioned on either sides of said gate
electrode and between said substrate and gate oxidation film; (c)
an insulator filled in said groove; and (d) a nitride layer
positioned on a surface of said groove to separate said insulator
from a surface of said groove.
2. The semiconductor device according to claim 1, wherein said
nitride layer is formed on the full surface of said groove.
3. The semiconductor device according to claim 1, further
comprising an oxidation film formed on the surface of the groove,
wherein said nitride layer is provided by nitriding said surface of
the groove through an oxidation film.
4. The semiconductor device according to claim 1, wherein said
insulator is an oxidation film formed by CVD method.
5. The semiconductor device according to claim 1, wherein said
nitride layer is formed to prevent said surface of the groove from
being oxidized.
6. A method of producing the semiconductor device having a
plurality of transistors comprising a semiconductor substrate of
first conductivity type having a principal plane, a gate electrode
formed on the principal plane via a gate oxidation film and
impurity-doped layers of the second conductivity type formed on the
principal plane on both sides of the gate electrode, wherein a step
of isolating the plurality of transistors from each other
comprising the steps of: (a) forming a groove by etching the
semiconductor substrate; (b) nitriding the surface of the groove to
form a nitride layer; and (c) filling the groove with an
insulator.
7. The method according to claim 6, further comprising the step of:
forming an oxidation film on the surface of the groove, wherein the
step of nitriding the surface of the groove comprises a step of
nitriding treatment carried out by nitriding the surface of the
groove through the oxidation film thereby to form a nitride layer
on the surface of the groove.
8. The method according to claim 6, wherein the step of nitriding
the surface of the groove comprises a step of nitriding treatment
of the surface of the groove carried out by using a nitrogen
monoxide gas.
9. The method according to claim 8, wherein the nitriding treatment
is carried out at a temperature of not less than 800.degree. C.
10. The method according to claim 6, wherein the step of nitriding
the surface of the groove comprises a step of nitriding treatment
of the surface of the groove carried out by using an ammonia
gas.
11. The method according to claim 10, wherein the nitriding
treatment is carried out at a temperature of not less than
700.degree. C.
12. The method according to claim 6, wherein the step of filling
the groove with an insulator is comprises a step of filling the
groove with an oxidation film formed by CVD method.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device, and
a method of producing the same. More particularly, it relates to a
trench isolation structure for electrically isolating semiconductor
elements.
[0003] 2. Description of the Related Art
[0004] Trench isolation structure formed between semiconductor
elements such as transistors has been becoming increasingly
important as semiconductor devices are packaged with higher density
and higher performance.
[0005] A method of producing trench isolation structure of the
prior art used in the conventional semiconductor device will be
described below with reference to FIGS. 12 through 21.
[0006] FIGS. 12 through 21 are cross sectional views showing first
through tenth steps of the method of producing a trench isolation
structure of the prior art.
[0007] First, referring to FIG. 12, a silicon oxide film 2 having
thickness of 100 .ANG. is grown on a principal plane of a P-type
silicon substrate 1 by thermal oxidation process, followed by the
deposition of a silicon nitride film 3 having thickness of 500
.ANG. by low pressure CVD (Chemical Vapor Deposition) process and
application of a resist to form a desired resist pattern 4 by
photolithography technology.
[0008] After etching the silicon nitride film 3 and the silicon
oxide film 2 with the resist pattern 4 used as a mask, the silicon
substrate 1 is etched thereby to form a groove 5 having a depth of
4000 .ANG. from the surface, and the resist pattern 4 is removed,
as shown in FIG. 13.
[0009] Now referring to FIG. 14, where thermal oxidation is applied
to the inner surface of the groove 5 formed in the silicon
substrate 1, thereby to form a silicon oxide film 6 having
thickness of 500 .ANG..
[0010] Then as shown in FIG. 15, the groove 5 is filled up by
depositing a silicon oxide filling 7 to a depth of 6000 .ANG. by
CVD process. Surface of the silicon oxide filling 7 is smoothed by
CMP (Chemical Mechanical Polishing) process.
[0011] Now referring to FIG. 16, where the silicon nitride film 3
is selectively removed by using thermal phosphoric acid, thus
forming a trench isolation structure 30 comprising the groove 5,
the silicon oxide film 6 and the silicon oxide filling 7.
[0012] After the isolation trench 30 has been formed as shown in
FIG. 17, boron ions are implanted with a density of
3.times.10.sup.12/cm.sup.2 and an energy of 200 KeV by ion
implantation process, thereby to form a channel stopper layer
35.
[0013] Now referring to FIG. 18, where the silicon oxide film 2 is
removed by using hydrofluoric acid (HF) solution.
[0014] Now referring to FIG. 19, where a silicon oxide film having
thickness of 50 .ANG. which would become a gate oxidation film 8 of
a transistor is formed by thermal oxidation process, and
phosphorus-doped polycrystal silicon is deposited to a thickness of
about 3000 .ANG. by low pressure CVD process. After forming a
desired resist pattern 10 by the photolithography technology, the
phosphorus-doped polycrystal silicon is etched with the resist
pattern 10 used as a mask, thereby forming a gate electrode 9.
[0015] Then as shown in FIG. 20, after removing the resist pattern
10, arsenic ions are implanted with a density of
4.times.10.sup.15/cm.sup.2 at an energy of 50 KeV by ion
implantation process, thereby to form an impurity-doped layer 11 of
a conductivity type different from that of the silicon substrate 1.
Then heat treatment is applied in nitrogen atmosphere at
800.degree. C. for about 30 minutes, thereby to form an N-type
diffusion layer 11 which is an impurity-doped layer by activating
the arsenic ions. Thus an MOS (Metal Oxide Semiconductor)
transistor 40 comprising the gate oxidation film 8, the gate
electrode 9 and the impurity-doped layer 11 is formed.
[0016] Then as shown in FIG. 21, after depositing a silicon oxide
film 12 having thickness of about 1000 .ANG. by the CVD process, a
boron phosphate glass 13 is deposited by the CVD process. After
reflowing the boron phosphate glass 13 through heat treatment
applied in nitrogen atmosphere at 850.degree. C. for 30 minutes, a
resist pattern (not shown) is formed by photolithography
technology. The resist pattern is used as a mask in etching the
boron phosphate glass 13 and the silicon oxide film 12 to make
contact holes (not shown), followed by deposition of an
aluminum-silicon-copper (Al--Si--Cu) alloy film by a sputtering
technique. Then a resist (not shown) is applied in a desired
pattern by the photolithography technology, and the resist pattern
is used as a mask for etching the aluminum-silicon-copper alloy
film, thereby to form an aluminum-silicon-copper wiring 14.
[0017] The semiconductor device of the prior art is constructed as
described above, while semiconductor elements such as transistor
are electrically isolated from each other by the trench isolation
structure.
[0018] In the semiconductor device of the prior art described
above, while the gate oxidation film 8 of the transistor is formed
by thermal oxidation process after forming the trench isolation
structure 30 as shown in FIG. 19, an oxidation agent tends to
diffuse into the silicon oxide filling 7 which is embedded in the
groove 5 and react with the silicon included in the inner wall of
the groove 5, resulting in the oxidation of the silicon included in
the inner wall of the groove 5. That is, oxidation of silicon in
the reaction of Si+O.sub.2.fwdarw.SiO.sub.2 causes silicon to turn
into a silicon oxide film, while the volume increases with the
ratio of silicon to silicon oxide being 1:2. In the present case,
since the groove 5 is filled with the silicon oxide filling 7, the
increased volume causes a compressive stress in the silicon located
near the groove 5. The compressive stress causes crystalline
defects to be generated in the silicon located near the groove
5.
[0019] FIG. 22 is a diagram for explaining a mechanism wherein leak
current flowing through an NP junction between an N-type diffusion
layer (drain) 11a and a P.sup.- type silicon substrate 1 increases
due to the generation of crystalline defects in the silicon located
near the groove 5. In FIG. 22, when an N type diffusion layer
(source) 11b and the P.sup.- type silicon substrate 1 are grounded
with a voltage of 3.3 V applied to the gate electrode 9 and 3.3 V
applied to the drain 11a to operate the MOS transistor, a depletion
layer 19 is generated in the vicinity of the interface between the
drain 11a and the P.sup.- type silicon substrate 1. At this time,
in case there is crystalline defect 20 caused by the stress due to
formation of the groove 5 in the silicon substrate 1, the depletion
layer 19 may involve the crystalline defect 20 where electron-hole
(21-22) pairs are generated, thereby increasing the leak current
flowing through the NP junction between the drain 11a and the
P.sup.- type silicon substrate 1.
[0020] In the semiconductor device which employs the trench
isolation structure of the prior art, as described above, there has
been such a problem that the stress, caused by volume expansion
through the oxidation of the silicon after forming the trench
isolation structure, thereby increasing junction leak current and
consequently causing an increased current consumption in the
semiconductor device.
SUMMARY OF THE INVENTION
[0021] The present invention has been attained to solve the problem
described above, and an object of the present invention is to
provide a semiconductor device wherein the current consumption is
reduced by controlling the generation of crystalline defects, and
another object of the present invention is to provide a method of
producing the semiconductor device.
[0022] A semiconductor device of the first invention is a
semiconductor device having a plurality of transistors comprising a
semiconductor substrate of first conductivity type having a
principal plane, a gate electrode formed on the principal plane via
a gate oxidation film and impurity-doped layers of the second
conductivity type formed on the principal plane on both sides of
the gate electrode, wherein the plurality of transistors are
isolated from each other by filling a groove formed by etching the
semiconductor substrate with an insulating material, while a
nitride layer is provided by nitriding the semiconductor in the
inner surface of the groove.
[0023] A semiconductor device of the second invention is that
wherein the nitride layer is formed by a nitriding treatment using
a nitrogen monoxide gas.
[0024] A semiconductor device of the third invention is a
semiconductor device, wherein the nitriding treatment is carried
out at a temperature of not less than 800.degree. C.
[0025] A semiconductor device of the fourth invention is a
semiconductor device, wherein the nitriding treatment is carried
out by using an ammonia gas.
[0026] A semiconductor device of the fifth invention is a
semiconductor device, wherein the nitriding treatment carried out
at a temperature of not less than 700.degree. C.
[0027] A method of producing the semiconductor device according to
the sixth invention is a method of producing the semiconductor
device having a plurality of transistors comprising a semiconductor
substrate of first conductivity type having a principal plane, a
gate electrode formed on the principal plane via a gate oxidation
film and impurity-doped layers of the second conductivity type
formed on the principal plane on both sides of the gate electrode,
wherein a step of isolating the plurality of transistors from each
other comprises a step of forming a groove by etching the
semiconductor substrate, a step of nitriding the semiconductor of
the inner surface of the groove thereby to form a nitride layer,
and a step of filling the groove with an insulating material.
[0028] A method of producing the semiconductor device according to
the seventh invention is a method, wherein the step of forming the
nitride layer comprises a step of carrying out the nitriding
treatment using a nitrogen monoxide gas.
[0029] A method of producing the semiconductor device according to
the eighth invention is a method, wherein the nitriding treatment
is carried out at a temperature of not less than 800.degree. C.
[0030] A method of producing the semiconductor device according to
the ninth invention is a method, wherein the step of forming the
nitride layer comprises a step of nitriding treatment carried out
by using an ammonia gas.
[0031] A method of producing the semiconductor device according to
the tenth invention is a method, wherein the nitriding treatment is
carried out at a temperature of not less than 700.degree. C.
[0032] The present invention, having the configuration described
above, provides the following effects.
[0033] According to the first and the sixth inventions, since the
plurality of transistors are isolated from each other and the
nitride layer is formed on the inner surface of the groove which
constitutes the trench isolation structure, expansion of the oxide
film due to the oxidation treatment after filling the groove is
suppressed thereby preventing crystalline defects from being
generated due to the compressive stress generated in the
semiconductor substrate, thus minimizing the leak current caused by
crystalline defect and improving the characteristics of the
junction, and therefore it is made possible to produce the
semiconductor device of low power consumption and stable
operation.
[0034] Further according to the second and the seventh inventions,
the nitriding treatment can also be effectively performed from
above the insulating material in which case nitrogen gas
concentrates to the interface between the semiconductor
substrate,and the insulating material due to diffusion, thus
forming a strong oxidation control layer.
[0035] Also according to the third and the eighth inventions, the
nitride layer having sufficient oxidation control effect can be
formed by applying the nitriding treatment with the nitrogen
monoxide gas at a temperature of 800.degree. C. or higher.
[0036] Further according to the fourth and the ninth inventions,
ammonia gas can be applied from above the insulating material for
the nitriding treatment in which case nitrogen concentrates to the
interface between the semiconductor substrate and the insulating
material due to diffusion, thus forming a strong oxidation control
layer.
[0037] Also according to the fifth and the tenth inventions, the
nitride layer having sufficient oxidation control effect can be
formed by applying the nitriding treatment using ammonia gas at a
temperature of 700.degree. C. or higher.
BRIEF DESCRIPTION OF THE DRAWINGS
[0038] FIG. 1 is a cross sectional view showing the semiconductor
device according to the first embodiment of the present
invention;
[0039] FIG. 2 is a cross sectional view showing a first step of the
method of producing the semiconductor device according to the first
embodiment of the present invention;
[0040] FIG. 3 is a cross sectional view showing a second step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0041] FIG. 4 is a cross sectional view showing a third step of the
method of producing the semiconductor device according to the first
embodiment of the present invention;
[0042] FIG. 5 is a cross sectional view showing a fourth step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0043] FIG. 6 is a cross sectional view showing a fifth step of the
method of producing the semiconductor device according to the first
embodiment of the present invention;
[0044] FIG. 7 is a cross sectional view showing a sixth step of the
method of producing the semiconductor device according to the first
embodiment of the present invention;
[0045] FIG. 8 is a cross sectional view showing a seventh step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0046] FIG. 9 is a cross sectional view showing an eighth step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0047] FIG. 10 is a cross sectional view showing a ninth step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0048] FIG. 11 is a cross sectional view showing a tenth step of
the method of producing the semiconductor device according to the
first embodiment of the present invention;
[0049] FIG. 12 is a cross sectional view showing a first step of
the method of producing the semiconductor device of the prior
art;
[0050] FIG. 13 is a cross sectional view showing a second step of
the method of producing the semiconductor device of the prior
art;
[0051] FIG. 14 is a cross sectional view showing a third step of
the method of producing the semiconductor device of the prior
art;
[0052] FIG. 15 is a cross sectional view showing a fourth step of
the method of producing the semiconductor device of the prior
art;
[0053] FIG. 16 is a cross sectional view showing a fifth step of
the method of producing the semiconductor device of the prior
art;
[0054] FIG. 17 is a cross sectional view showing a sixth step of
the method of producing the semiconductor device of the prior
art;
[0055] FIG. 18 is a cross sectional view showing a seventh step of
the method of producing the semiconductor device of the prior
art;
[0056] FIG. 19 is a cross sectional view showing an eighth step of
the method of producing the semiconductor device of the prior
art;
[0057] FIG. 20 is a cross sectional view showing a ninth step of
the method of producing the semiconductor device of the prior
art;
[0058] FIG. 21 is a cross sectional view showing a tenth step of
the method of producing the semiconductor device of the prior art;
and
[0059] FIG. 22 is a diagram for explaining the increasing leak
current through transistor junction due to crystalline defect
induced by the conventional trench isolation employed in the
semiconductor device of the prior art.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0060] Embodiment 1
[0061] Now the first embodiment of the present invention will be
described below with reference to FIGS. 1 through 11.
[0062] FIG. 1 is a cross sectional view showing the semiconductor
device according to the first embodiment of the present invention.
In FIG. 1, numeral 1 denotes a P type silicon substrate which is a
semiconductor substrate, 5 denotes a groove, 6 and 7 denote silicon
oxide films, 8 denotes a silicon oxidation film which is a gate
oxidation film, 9 denotes a gate electrode, 11 denotes an
impurity-doped layer, 12 denotes a silicon oxide film, 13 denotes a
boron phosphate glass, 14 denotes an aluminum-silicon-copper
wiring, 35 denotes a channel stopper layer, 40 denotes an MOS
transistor, 60 denotes a nitride layer and 80 denotes an isolation
trench.
[0063] Now a method of producing the semiconductor device will be
described below with reference to FIGS. 2 through
[0064] FIGS. 2 through 11 show first through tenth step for making
the trench isolation structure used in the semiconductor device
shown in FIG. 1.
[0065] First, with reference to FIG. 2, the silicon oxide film 2
having a thickness of 100 .ANG. is grown on the surface of the P
type silicon substrate 1 which is a semiconductor substrate by
thermal oxidation step, followed by deposition of the silicon
nitride film 3 having a thickness of 500 .ANG. by low pressure CVD
process, and then a desired pattern of resist 4 is formed by the
photolithography technology.
[0066] Then as shown in FIG. 3, the resist pattern 4 is used as a
mask in etching of the silicon nitride film 3 and the silicon oxide
film 2, surface of the silicon substrate is etched to form the
groove 5 having a depth of 4000 .ANG. and the resist pattern 4 is
removed.
[0067] Then as shown in FIG. 4, thermal oxidation is applied to the
inner surface of the groove 5 in the silicon substrate thereby to
form the silicon oxide film 6 having a thickness of 500 .ANG..
[0068] Now with reference to FIG. 5, the silicon oxide film 6 is
annealed at a temperature of 800.degree. C. or higher in nitrogen
monoxide (NO) gas atmosphere which has nitriding effect, thereby to
nitride the inner surface of the groove 5 in the silicon substrate
1 and form the nitride layer 60 made by nitriding of silicon
included in the inner surface of the silicon substrate 1. Nitriding
can be effectively performed even when applied from above the
silicon oxide film 6 since nitrogen concentrates to the interface
between the silicon substrate 1 and the silicon oxide film 6 due to
diffusion. The same nitriding effect can also be achieved without
the silicon oxide film 6, and therefore nitriding process can be
applied to a structure without the silicon oxide film 6. Also the
nitriding treatment may not necessarily be done by using nitrogen
monoxide gas, and ammonia gas or the like which has an action to
nitride the silicon surface may be employed.
[0069] Then as shown in FIG. 6, the groove 5 is filled up by
depositing a silicon oxide filling 7 to a depth of 6000 .ANG. by
the CVD process. Surface of the silicon oxide filling 7 is then
smoothed by the CMP process.
[0070] Then as shown in FIG. 7, the silicon nitride film 3 is
selectively removed using thermal phosphoric acid, thus forming a
trench isolation structure 80 according to the first embodiment
comprising the groove 5, the silicon oxide film 6, the silicon
oxide filling 7 and the nitride layer 60.
[0071] Now taking reference to FIG. 8, boron ions are implanted
with a density of 3.times.10.sup.12/cm.sup.2 and an energy of 200
KeV by ion implantation process, thereby to form the channel
stopper layer 35.
[0072] Then as shown in FIG. 9, the silicon oxide film 2 is removed
by using hydrofluoric acid solution.
[0073] Then as shown in FIG. 10, a silicon oxide film having a
thickness of 50 .ANG. which would become the gate oxidation film 8
of a transistor is grown by the thermal oxidation process, a
phosphorus-doped polycrystal silicon is deposited to a thickness of
about 3000 .ANG. by the low pressure CVD process and, after forming
a desired resist pattern 10 by the photolithography technology, the
phosphorus-doped polycrystal silicon is etched with the resist
pattern 10 used as a mask, thereby forming the gate electrode
9.
[0074] Then as shown in FIG. 11, after removing the resist pattern
10, arsenic ions are implanted with a density of 4
.times.10.sup.15/cm.sup.2 and an energy of 50 KeV by the ion
implantation process, thereby to form the impurity-doped layer 11
of a conductivity type different from that of the silicon substrate
1. Then heat treatment is applied in nitrogen atmosphere at
800.degree. C. for about 30 minutes, thereby to form the N-type
diffusion layer 11 which is an impurity-doped layer by activating
the arsenic ions. Thus a MOS transistor 40 comprising the gate
oxidation film 8, the gate electrode 9 and the impurity-doped layer
11 is formed.
[0075] Then after depositing the silicon oxide film 12 having a
thickness of about 1000 .ANG. by the CVD process, a boron phosphate
glass 13 is deposited by the CVD process. After reflowing the boron
phosphate glass 13 through heat treatment applied in nitrogen
atmosphere at 850.degree. C. for 30 minutes, a resist pattern (not
shown) is formed by the photolithography technology. The resist
pattern is used as a mask in etching the boron phosphate glass 13
and the silicon oxide film 12 to make contact holes (not shown),
followed by deposition of an aluminum-silicon-copper alloy film by
sputtering technique. Then a resist (not shown) is applied in a
desired pattern by the photolithography technology, the resist
pattern is used as a mask for etching the aluminum-silicon-copper
alloy film, thereby to form an aluminum-silicon-copper wiring 14
and forming the semiconductor device shown in FIG. 1.
[0076] According to the first embodiment of the semiconductor
device and the method of producing the semiconductor device, as
described above, since the nitride layer having an effect of
controlling the oxidation is formed on the inner surface of the
groove by nitriding the silicon included therein after etching of
the trench, volumetric expansion inside the trench can be
controlled during oxidation such as gate oxidation after forming
the trench, thereby making it possible to minimize the compressive
stress generated by the volumetric expansion in the active
region.
[0077] Minimization of the stress in turn enables it to prevent
crystalline defects from being generated in the silicon substrate,
thus suppressing leak current caused by crystalline defect flowing
through the NP junction. Further, since nitriding treatment is
applied after the trench has been etched out and before the trench
is filled up by the CVD oxidation or the like, the nitride layer
can be formed on the inner surface of the trench. As the nitriding
layer has a strong effect of suppressing oxidation, the
semiconductor device capable of controlling the volumetric
expansion in the trench can be produced also by oxidation such as
gate oxidation after forming the trench isolation structure.
* * * * *