U.S. patent application number 09/993886 was filed with the patent office on 2002-12-05 for noise floor reduction in image sensors.
Invention is credited to Stark, Moshe.
Application Number | 20020179820 09/993886 |
Document ID | / |
Family ID | 22958081 |
Filed Date | 2002-12-05 |
United States Patent
Application |
20020179820 |
Kind Code |
A1 |
Stark, Moshe |
December 5, 2002 |
Noise floor reduction in image sensors
Abstract
An image sensor array including a first plurality of unit cells
coupled to a first sense amplifier, and a second plurality of unit
cells coupled to a second sense amplifier, where the first
plurality and the second plurality are substantially electrically
isolated from each other.
Inventors: |
Stark, Moshe; (Even Yehuda,
IL) |
Correspondence
Address: |
Eitan, Pearl, Latzer & Cohen-Zedek
One Crystal Park
Suite 210
2011 Crystal Drive
Arlington
VA
22202-3709
US
|
Family ID: |
22958081 |
Appl. No.: |
09/993886 |
Filed: |
November 27, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60252915 |
Nov 27, 2000 |
|
|
|
Current U.S.
Class: |
250/208.1 ;
257/E27.132; 348/E3.021 |
Current CPC
Class: |
H01L 27/14643 20130101;
H01L 27/14609 20130101; H04N 5/3454 20130101; H04N 5/3658 20130101;
H04N 5/3415 20130101 |
Class at
Publication: |
250/208.1 |
International
Class: |
H01L 027/00 |
Claims
What is claimed is:
1. An image sensor array comprising: a first plurality of unit
cells coupled to a first sense amplifier; and a second plurality of
unit cells coupled to a second sense amplifier, wherein said first
plurality and said second plurality are substantially electrically
isolated from each other.
2. An image sensor array according to claim 1, wherein: each of
said first and second pluralities of unit cells comprises at least
one column line.
3. An image sensor array according to claim 2, wherein: said unit
cells am arranged in two or more clusters of two or more of said
unit cells each, and said unit cells within each of said clusters
are coupled to a cluster line which is coupled to said column
line.
4. An image sensor array according to claim 3 wherein only one of
said clusters is actively connected to said column line at any
given time.
5. An image sensor array according to claim 1 wherein said unit
cells are direct injection unit cells.
6. An image sensor array according to claim 1 wherein said first
plurality and said second plurality are substantially electrically
isolated from each over by at least 10M Ohms.
7. An image sensor array comprising: a plurality of columns, each
column comprising a plurality of unit cells coupled to a column
line; a first sense amplifier coupled to a first plurality of said
unit cells in each of said columns; and a second sense amplifier
coupled to a second plurality of said unit cells in each of said
columns, wherein said first and second pluralities of of said unit
cells in each of said columns are substantially electrically
isolated from each other.
8. An image sensor array according to claim 7 wherein each of said
columns comprises a plurality of clusters, each cluster comprising
two or more of said unit cells coupled to a cluster line which is
coupled to said column line.
9. An image sensor array according to claim 7 wherein only one of
said clusters is actively connected to said column line at any
given time.
10. An image sensor array according to claim 7 wherein said unit
cells are direct injection unit cells.
11. An image sensor array according to claim 7 wherein said first
plurality and said second plurality are substantially electrically
isolated from each other by at least 10M Ohms.
12. A method for reducing noise floor in an image sensor, the
method comprising: sensing a first plurality of unit cells with a
first sense amplifier; and sensing a second plurality of unit cells
with a second sense amplifier.
13. A method according to claim 12 wherein either of said sensing
steps comprises sensing different subsets of said unit cells at
different times.
14. A method according to claim 12 wherein either of said sensing
steps comprises sensing mutually exclusive subsets of said unit
cells at different times.
15. A method according to claim 12 wherein each of said sensing
steps comprises sensing its associated plurality of unit cells in
substantial electrical isolation from the other said plurality of
unit cells.
16. A method according to claim 12 wherein each of said sensing
steps are performed alternatingly.
17. An image sensor array comprising: a first plurality of unit
cells coupled to a first sense amplifier; and a second plurality of
unit cells coupled to a second sense amplifier, wherein said first
plurality and said second plurality are substantially electrically
isolated from each other; wherein: each of said first and second
pluralities of unit cells comprises at least one column line.
18. An image sensor array comprising: a first plurality of unit
cells coupled to a first sense amplifier; and a second plurality of
unit cells coupled to a second sense amplifier, wherein said first
plurality and said second plurality are substantially electrically
isolated from each other; wherein: said unit cells are arranged in
two or more clusters of two or more of said unit cells each, and
said unit cells within each of said clusters are coupled to a
cluster line which is coupled to said column line.
19. An image sensor array comprising: a first plurality of unit
cell means coupled to a first sense amplifier; and a second
plurality of unit cell means coupled to a second sense amplifier,
wherein said first plurality and said second plurality are
substantially electrically isolated from each other.
20. A method for reducing noise floor in an image sensor, the
method comprising: sensing a first plurality of unit cells with a
first sense amplifier; and sensing a second plurality of unit cells
with a second sense amplifier; wherein each of said sensing steps
comprises sensing its associated plurality of unit cells in
substantial electrical isolation from the other said plurality of
unit cells.
21. A method for reducing noise floor in an image sensor, the
method comprising: sensing a first plurality of unit cells with a
first sense amplifier; and sensing a second plurality of unit cells
with a second sense amplifier; wherein said sensing steps include
at least sensing different subsets of said unit cells at different
times.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Patent Application Ser. No. 60/252,915, filed Nov. 27, 2000, and
entitled "Noise floor reduction in image sensors," incorporated
herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to imaging electronics in
general, and more particularly to noise floor reduction in CMOS
process Active Pixel image sensor systems.
BACKGROUND OF THE INVENTION
[0003] CMOS process Active Pixel Sensor (APS) technology is
foreseen as the next generation technology for image sensors, which
will replace the currently dominating CCD technology. Among the
advantages that APS technology has over CCD technology are the
ability to integrate image sensor and camera electronics onto a
single chip, low power dissipation due to the inherently lower CMOS
process voltage as compared with CCD voltage, and
significantly-lower manufacturing costs.
[0004] Dramatic advance in the CMOS process technology are also
expected to lead to the implementation of imagers with a 5 .mu.m
pixel pitch on a submicron CMOS process, which is approximately
equal to the diffraction limit of the camera lens. This limit
offsets one of the major advantages of CCD technology, namely the
high fill factor afforded by a very simple pixel circuit.
[0005] The ability to implement photographic-quality imagers using
CCD technology is severely limited by the large array dimensions
that would be required, having thousands of pixel columns and rows.
It is difficult to implement such large arrays using CCD technology
due to the CCD Charge Transfer Efficiency (CTE) factor which
dictates that image quality severely deteriorates as the size of
the image sensor array increases. It is not commercially feasible
to produce 3,000.times.2,000 pixel CCD arrays as would be required
for near photographic quality images due to the prohibitive
manufacturing costs involved.
[0006] Although the transition from CCD-based technology to
APS-based technology for commercial image sensors appears
inevitable, APS technology has several limitations that have yet to
be overcome. The ability to implement large CMOS-based APS image
sensor arrays is limited by readout bus capacitance that originates
from multiplexing all pixels within each column into a single
column line. The parasitic output capacitances of the multiplexing
circuits and of the line interconnect, normally implemented with
metal, are the major contributors to column capacitance. Thus, for
a given CMOS process and pixel unit cell size, the column
capacitance is proportional to the number of multiplexed rows.
[0007] The column capacitance is the dominant contributor to the
input-referred noise and it governed by the so-called "kTC" noise
mechanism. One technique that may be used to reduce the kTC noise
effect involves introducing an amplification stage in each pixel's
unit cell by including an in-pixel Source-Follower circuit. The
Source-Follower amplifier "de-couples" the in-pixel integration
capacitor from the column capacitance, which results in a reduced
input-referred readout noise. However, this technique leads to a
reduction in gain due to the attenuation of the signal as a
function of column bus capacitance. This can be costly in terms of
signal-to-noise ratio (SNR) for large-format circuits with a high
column capacitance and for applications where the charge that is
involved is small. Thus, although implementing a Source-Follower
circuit results in a reduced input-referred readout noise, its
effect diminishes as the imager's size increases due to the
increasing column capacitance.
SUMMARY OF THE INVENTION
[0008] The present intention seeks to provide methods and apparatus
for noise floor reduction in CMOS-based APS image sensor arrays
that overcomes disadvantages of the prior art. The present
invention substantially reduces the column capacitance in large
image sensor arrays, resulting in a reduced noise floor and a
better signal-to-noise ratio. A Direct Injection (DI) circuit
approach is employed in place of the Source-Follower circuit per
unit cell approach. A DI circuit is relatively simple to implement
and deploys less transistors per unit cell, which results in a
higher unit cell fill-factor, a smaller pixel, or both.
Furthermore, the Fixed Pattern Noise (FPN) of a DI circuit is
considerably lower than that of the Source-Follower-based unit
cell. The DI circuit of the present invention directly injects the
charge accumulated by the integration capacitor into the column.
This results in a significant input-referred readout noise that is
higher than that of the Source-Follower-based unit cell. By
reducing column capacitance the present invention significantly
reduces the image sensor's noise floor and improves its
signal-to-noise ratio, particularly in large image sensor
arrays.
[0009] In one aspect of the present invention an image sensor array
is provided including a first plurality of unit cells coupled to a
first sense amplifier, and a second plurality of unit cells coupled
to a second sense amplifier, where the first plurality and the
second plurality are substantially electrically isolated from each
other.
[0010] In another aspect of the present invention each of the first
and second pluralities of unit cells includes at least one column
line.
[0011] In another aspect of the present invention the unit cells
are arranged in two or more clusters of two or more of the unit
cells each, and the unit cells within each of the clusters are
coupled to a cluster line which is coupled to the column line,
[0012] In another aspect of the present invention only one of the
clusters is actively connected to the column line at any given
time.
[0013] In another aspect of the present invention the unit cells
are direct injection unit cells.
[0014] In another aspect of the present invention the first
plurality and the second plurality are substantially electrically
isolated from each other by at le 10M Ohms.
[0015] In another aspect of the present invention an image sensor
array is provided including a plurality of columns, each column
including a plurality of unit cells coupled to a column lines a
first sense amplifier coupled to a first plurality of the unit
cells in each of the columns, and a second sense amplifier coupled
to a second plurality of the unit cells in each of the columns,
where the first and second pluralities of the unit cells in each of
the columns are substantially electrically isolated from each
other.
[0016] In another aspect of the present invention each of the
columns includes a plurality of clusters, each cluster including
two or more of the unit cells coupled to a cluster line which is
coupled to the column line.
[0017] In another aspect of the present invention only one of the
clusters is actively connected to the column line at any given
time.
[0018] In another aspect of the present invention the unit cells
are direct injection unit cells.
[0019] In another aspect of the present invention the first
plurality and the second plurality are substantially electrically
isolated from each other by at least 10M Ohms.
[0020] In another aspect of the present invention a method for
reducing noise floor in an image sensor is provided, the method
including sensing a first plurality of unit cells with a first
sense amplifier, and sensing a second plurality of unit cells with
a second sense amplifier.
[0021] In another aspect of the present invention either of the
sensing steps includes sensing different subsets of the unit cells
at different tunes.
[0022] In another aspect of the present invention either of the
sensing steps includes sensing mutually exclusive subsets of the
unit cells at different times.
[0023] In another aspect of the present invention each of the
sensing steps includes sensing its associated plurality of unit
cells in substantial electrical isolation from the other the
plurality of unit cells.
[0024] In another aspect of the present invention each of the
sensing steps are performed alternatingly.
[0025] The disclosures of all patents, patent applications, and
other publications mentioned in this specification and of the
patents, patent applications, and other publications cited therein
are hereby incorporated by reference in they entirety.
BRIEF DESCRIPTION OF TE DRAWINGS
[0026] The present invention will be understood and appreciated
more fully from the following detailed description taken in
conjunction with the appended drawings in which:
[0027] FIGS. 1A and 1B are schematic flow illustrations of a Direct
Injection (DI) unit cell 100, useful in understanding the present
invention;
[0028] FIG. 2 is a schematic illustration of an image sensor array
segment, useful in understanding the present invention;
[0029] FIGS. 3A and 3B, taken together, are top-view and side-view
illustrations of readout transistor T.sub.2 of FIGS. 1A, 1B, and 2,
useful in understanding the present invention;
[0030] FIG. 4 is a schematic illustration of an image sensor array,
constructed and operative in accordance with a preferred embodiment
of the present invention; and
[0031] FIG. 5 is a schematic illustration of an alternative image
sensor array column arrangement for use with the image sensor array
of FIG. 4, constructed and operative in accordance with a preferred
embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODLMENTS
[0032] Reference is now made to FIGS. 1A and 1B, which are
schematic illustrations of a Direct Injection (DI) unit cell 100,
useful in understanding he present invention. DI 100 is shown as
having a photodiode PD 102, an integration capacitor C.sub.mt 104,
a transistor T.sub.1 106, column line capacitance C.sub.col 108, a
readout transistor T.sub.2 110, a column line 112, and transistor
gates 114 and 116.
[0033] When an image sensor's background photon noise is low, its
noise floor is determined by the image sensor's electronics,
particularly the readout electronics associated with photocurrent
signals, as well as its input stages, which in turn determines the
image sensor's sensitivity.
[0034] The major noise components which determine the noise floor
are Fixed Pattern Noise (FPN), 1/f noise, and white noise. A Direct
Ejection stage typically features a very low FPN, and conventional
techniques may be applied to remove 1/f noise. If generated at
later stages, white noise may also be removed using conventional
techniques
[0035] Among the major factors which set the lower bound to noise
originating from the pixel readout, the dominant noise component is
the so-called kTC noise, which originates from transferring charges
from their origin to a collecting capacitor C. The kTC noise
originates from a resistor which charges a capacitor. The noise
output on the capacitor, <v.sub.n>, which originates from a
resistor, is expressed: 1 v n = kT C ( EQ . 1 )
[0036] where k is Boltzmann's constant of 1.38.times.10.sup.-23
Joul/.degree. K., T is the resistor's/capacitor's temperature
expressed in degrees Kelvin, C is the capacitor's capacitance
expressed in Farads, and <v.sub.n> is the capacitor's PMS
noise voltage expressed in Volts.
[0037] The noise may be expressed in terms of "noise electrons,"
that is the number of electrons that would cause the RMS noise on
capacitor C. The RMS number of noise electrons, <N.sub.n> may
be derived from (EQ. 1) as: 2 N n = 1 e kTC ( EQ . 2 )
[0038] where e is the electron charge of 1.6.times.10.sup.-19
Coulomb.
[0039] In FIG. 1A a photon-generated photocurrent I.sub.ph flows
from photodiode PD 102 into integration capacitor C.sub.int 104
through transistor T.sub.1 106. The kTC noise source is the
transistor T.sub.1 channel resistance. The photocurrent integration
stage is depicted in FIG. 1A, and thus the noise source may be
defined as the integration noise. The integration noise may be
expressed in terms of RMS voltage as: 3 v n int = kT C int ( EQ . 3
)
[0040] where <v.sub.n.sup.int> is the RMS integration noise
and C.sub.int is the charge integration capacitance. The RMS number
of noise electrons <N.sub.n.sup.int> may be expressed as: 4 N
n int = 1 e kTC int ( EQ . 4 )
[0041] FIG. 1B shows the path taken by the integrated charge
readout from the C.sub.int to the column line 112. The column
line's capacitance is shown as C.sub.col 108. The charge transfer
is embodied as a current flow through a readout transistor T.sub.2
110. This current flow generates a kTC noise on the column line,
and the noise component is translated into an equivalent noise
source on the integration capacitor C.sub.int. This represents the
noise on the integration capacitor that would result in the same
noise on the column line. This noise is referred to as
"input-referred noise," and is expressed as <v.sub.n.sup.col>
for the RMS noise voltage and <N.sub.n.sup.col> for the RMS
number of noise electrons. It may be shown that 5 v n col = kT C
int ( C col C int + C int C col ) and ( EQ . 5 ) N n col = 1 e kTC
int ( C col C int + C int C col ) ( EQ . 6 )
[0042] Typically, C.sub.col>>C.sub.int. Thus, it may be seen
that the dominant factor which contributes to noise floor is not
the integration noise, but rather the noise that originates from
the integrated charge readout to the image sensor's column.
[0043] By way of example, given a 0.6 .mu.m process, a 10
.mu.m.times.10 .mu.m pixel, and a 1,000-row image sensor, the
column capacitance is approximately 4 pF, and the integration
capacitance is approximately 0.1 pF. In this example, the column
input-referred readout noise is approximately 6.5 times greater
than the integration noise. The readout noise is approximately 40
.mu.V RMS, while the input-referred readout noise is approximately
1.5 mV. The integration noise is approximately 6 .mu.V rms.
[0044] Thus, it may be seen that the column readout noise is the
dominant factor and may be considered to be the noise floor.
Significant reduction of the column readout capacitance would
therefore result in a significant noise floor reduction, as the
column readout noise is determined by the 6 C col C int
[0045] ratio and reduction of C.sub.col would result in noise floor
reduction.
[0046] Improvement in the signal-to-noise ratio may also be
achieved as follows, Let v.sub.int represent the highest possible
signal that may be collected on the integration capacitor C.sub.int
at reaching saturation. Given that column readout noise a dominant
contributor to noise floor, the signal-to-noise ratio may be
approximated as: 7 SNR v int v n col ( EQ . 7 )
[0047] where SNR is the signal-to-noise ratio at the column line,
v.sub.int is the near-saturation voltage on the integration
capacitance, and <v.sub.n.sup.col> is the input-referred
column line noise RMS voltage. Thus, for a 5 volt process v.sub.int
is approximately 1.5 Volts. Continuing with the previous example,
given a 373.degree. K. junction temperature, the input-referred
column readout noise may be as much as .about.1.5 mVolts, resulting
in a signal-to-noise ratio of approximately 1,000. Where column
readout noise is negligible, the signal-to-noise ratio is limited
mainly by the charge integration noise, being approximately 6.5
times better than the signal-to-noise ratio in this example.
[0048] Reference is now made to FIG. 2, which is a schematic flow
illustration of an image sensor array segment, useful in
understanding the present invention. In FIG. 2 a single column 200
of an X by V-rows image sensor array is shown having multiple unit
cells 202 connected to a column line 206, where each unit cell
includes a Direct Injection (DI) circuit 204 as described
hereinabove with reference to FIGS. 1A and 1B. In the configuration
shown, when a row is read out, its readout transistors T.sub.2
conduct a charge, and the charge accumulated on the integration
capacitors of the row is transferred to its respective column line.
All the other readout transistors which reside on each column are
in a cutoff state.
[0049] The column capacitance C.sub.col in FIG. 2 may be
approximated by:
C.sub.col.congruent.V.multidot.(C.sub.d+c.sub.M.multidot.a) (EQ.
8)
[0050] where V is the number of image sensor rows, C.sub.d is the
readout transistor drain capacitance when in cutoff and when the
column is biased approximately to 0 Volts, c.sub.M is the column
metal capacitance per unit length, and a is the pixel pitch for
square pixels. C.sub.col.congruent.C.sub.d+c.sub.M.multidot.a is
thus the column capacitance per pixel, as is shown at reference
numeral 208.
[0051] It may thus be seen that column capacitance, which
determines the noise floor, is directly proportional to the number
of rows in the image sensor, and, thus, the larger the image sensor
array, the greater the noise floor.
[0052] Reference is now made to FIGS. 3A and 3B, which are top-view
and side-view illustrations of readout transistor T.sub.2 of FIGS.
1A, 1B, and 2, useful in understanding the present invention. In
FIGS. 3A and 3B a transistor assembly 300 is shown including a
transistor T.sub.2 element 302 including a gate 304, a drain 306, a
column metal line 308, a field oxide element 310, a connection 312
of column metal line 308 to drain 306, all overlying a bulk
314.
[0053] In FIGS. 3A and 3B, transistor T.sub.2 is shown with its
contact and an adjacent section of column line, typically
constructed from M1 metal. It may be seen that the width of
transistor T.sub.2 transistor is not minimal due to the
drain-to-column contact rules which require the width of transistor
T.sub.2 to be more than double the minimal possible transistor
channel width. The drain diffusion capacitance and the overlapping
gate-drain capacitance determine the drain capacitance C.sub.d as
follows:
C.sub.d.congruent.C.sub.gd+C.sub.db (EQ. 9)
[0054] where C.sub.gd is the gate-to-drain overlapping capacitance,
and C.sub.db is the drain bulk diode capacitance at zero volts. It
may further be seen that:
C.sub.gd.congruent.W.multidot.L.sub.OV.multidot.c.sub.g (EQ.
10)
[0055] where W is the T.sub.2 transistor's width, L.sub.OV is the
overlapping distance between the gate and the drain, which is
usually derived in an empirical manner, and C.sub.g is the
gate-bulk capacitance per unit area determined by the gate oxide
thickness. And finally:
C.sub.db.congruent.c.sub.jd.sup.0.multidot.A.sub.d+c.sub.jdsw.sup.0.multid-
ot.P.sub.d (EQ. 11)
[0056] where c.sub.jd.sup.0 is the drain junction capacitance at
zero voltage bias per area unit, A.sub.d is the drain junction
area, c.sub.jdsw.sup.0 is the drain junction sidewall capacitance
per unit length at zero voltage bias, and, P.sub.d is the junction
periphery length which includes all the junction sidewalls
excluding the gate side.
[0057] By way of example, for a typical 0.6 .mu.m CMOS process, the
T.sub.2 transistor has
[0058] A.sub.d.congruent.2 .mu.m.sup.2
[0059] P.sub.d.congruent.4 .mu.m
[0060] c.sub.jd.sup.o.congruent.0.4 fF/.mu.m.sup.2
[0061] c.sub.jdsw.sup.o.congruent.0.45 fF/.mu.m
[0062] L.sub.ov.congruent.0.1 .mu.m
[0063] Therefore, C.sub.d may be expressed as:
C.sub.d.congruent.3fF (EQ. 12)
[0064] The metal capacitance per unit length C.sub.M is given
by:
c.sub.M=c.sub.M.sup.A.multidot.W.sub.M+2.multidot.c.sub.M.sup.P
(EQ. 13)
[0065] where c.sub.M.sup.A is the metal line capacitance per area
unit, and c.sub.M.sup.P is the metal capacitance, per line side,
per unit length. Thus, for the example 0.6 .mu.m CMOS process, the
typical Metal 1 capacitances are
c.sub.M.sup.A.congruent.0.04 fF/.mu.m.sup.2
c.sub.M.sup.P.congruent.0.03 fF/.mu.m
[0066] and a metal width W.sub.M.congruent.0.6 .mu.m,
[0067] giving a metal capacitance per unit length C.sub.M as
c.sub.M.congruent.0.08 fF/.mu.m (EQ. 14)
[0068] Given EQ. 12 and 14, for a pixel pitch a=10 .mu.m the total
column capacitance per pixel c.sub.col may be calculated as:
c.sub.col.congruent.3.8 fF/pixel (EQ. 15)
[0069] Thus if V=1,000, the column capacitance is approximately 3.8
pF.
[0070] The integration capacitor's capacitance value may also be
calculated. This value for a 0.6 .mu.m CMOS process is:
C.sub.int.congruent.0.1 pF (EQ. 16)
[0071] Reference is now made to FIG. 4, which is a schematic
illustration of an image sensor array 400, constructed and
operative in accordance with a preferred embodiment of the present
invention. The sensor array 400 of FIG. 4 includes one or more
columns 402, each having one or more Direct Injection (DI) unit
cells 404 configured as described hereinabove with reference to
FIGS. 1A, 1B, 2, 3A, and 3B. As in most any two-dimensional array,
sensor array 400 may be alternatively referred to as having one or
more rows of unit cells 404. Each column 402 of sensor array 400 is
separated into two or more electrically isolated portions, such as
into an upper half 406 and a lower half 408 as shown in FIG. 4,
thus forming one or more upper half rows and one or more lower half
rows. The separation of the portions of each column is such that
there is little or no conductivity between the portions, such as a
resistance of greater that 10M Ohm. Each electrically isolated
portion is arranged to be read out through a separate sense
amplifier, such as is shown in FIG. 4 where each upper half row is
arranged to be read out through a top sense amplifier set 410, and
each lower half row is arranged to be read out through a bottom
sense amplifier set 412. Sensor array 400 is also preferably
configured with a row decoder 414 and an output buffer 416.
[0072] Since the upper and lower halves 406 and 408 of each column
402 are electrically isolated, the column capacitance which each
sense amplifier set faces may be expressed as: 8 C col 1 = V 2 c
col ( EQ . 17 )
[0073] The associated noise floor is of each sense amplifier set is
thus, 9 v 1 n = kT C int ( 0.5 C col C int + C int 0.5 C col ) ( EQ
. 18 )
[0074] where typically C.sub.col>>C.sub.int. The reduction in
the noise level may then be calculated as: 10 v 1 n V n 0.707 ( EQ
. 19 )
[0075] Thus, by splitting each column in the array into two halves,
the noise floor is reduced to about 70% of what it would be were
the columns not split.
[0076] The signal-to-noise ratio of the output data improves by the
same factor as the noise floor reduction as follows: 11 SNR 1 SNR 2
( EQ . 20 )
[0077] where SNR.sup.1 is the signal-to-noise ratio of the split
array, and SNR is the signal-to-noise ratio an undivided array as
described hereinabove with reference to FIGS. 1A, 1B, 2, 3A, and
3B. In an array where the columns are split into N portions, the
improvement of the SNR will be on the order of the square root of
N.
[0078] Reference is now made to FIG. 5, which is a schematic
illustration of an alternative image sensor array column
arrangement for use with the image sensor array of FIG. 4,
constructed and operative in accordance with a preferred embodiment
of the present invention. The sensor array column of FIG. 5, now
referred to as column 500, includes one or more Direct Injection
(DI) unit cells 502 configured as described hereinabove with
reference to FIGS. 1A, 1B, 2, 3A, and 3B, and is separated into
electrically isolated upper and lower halves as is described
hereinabove with reference to FIG. 4. Each half of column 500 is
segmented into k clusters 504 (shown as 504A, 504B, 504C, and
504D), typically numbering two or more. Each cluster 504 may be
expressed as 12 V k
[0079] rows, where V is the number of unit cells 502 in cluster
504, and is interconnected to a column line 506 via a cluster
select transistor 508 (shown as 508A, 508B, 508C, and 508D) that is
controlled by a cluster selector 510 (shown as 510A, 510B, 510C,
and 510D).
[0080] Typically, during row readout of column 500, only one out of
2.multidot.k cluster select transistors 508 in column 500 is "ON",
and all other cluster select transistors 508 in column 500 are
"OFF". The row readout typically starts with the top cluster 504A,
when cluster select transistors 508A transistor is "ON". The first
cluster rows are then selected and sequentially read, starting with
row 0, and ending with row 13 V 2 k - 1.
[0081] After all the rows in the top cluster are read out, cluster
select transistor 508A of the top cluster 504A switches from "ON"
to "OFF" (i.e., cluster selector 510A goes from "High" to "Low"),
and cluster select transistor 508B of the next cluster 504B
switches from "OFF" to "ON" ((i.e., cluster selector 510B goes from
"Low" to "High"). The rows of cluster 504B are then read
sequentially. This operation continues until all the rows of the
all of the columns 500 of the image sensor array are read out. As
is described hereinabove with reference to FIG. 4, the top half
rows of each column 500 is read through a top sense amplifier set,
while the bottom half rows of each column 500 is read through a
bottom sense amplifier set.
[0082] It may be seen that since only one cluster 504 is actively
connected to column line 506 at a time while all the other clusters
are not actively connected to column line 506, the total parasitic
load of column line 506 is significantly reduced. By way of
explanation, assume that cluster select transistors 508 are of the
same dimensions as the readout transistors T.sub.2 (FIGS. 1A, 1B,
2, 3A, and 3B) in every unit cell. This assumption may be
justified, since the transistor's width is much wider the minimum
width, where the width is determined by metal-to-drain contact
dimensions and overlap design rules. Thus, putting such two
transistors in series does not significantly slow down the readout.
Therefore, the dimensions of cluster select transistor 508 may be
given the same dimensions as that of readout transistor T.sub.2.
This being the case, the drain capacitance of cluster select
transistor 508 is identical to that of readout transistor T.sub.2.
Since k-1 cluster select transistors 508 are "OFF" at any given
time, their associated clusters are not actively connected to
column line 506 and, therefore, do not load the column line.
[0083] The capacitance of column line 506 may be calculated as: 14
C col 2 V 2 k ( C d + c M a ) + ( k C d + V 2 c M a ) ( EQ . 21
)
[0084] where 15 v 2 K ( C d + c M a )
[0085] is the capacitance associated with a single currently-read
cluster, 16 ( k C d + V 2 c M a )
[0086] approximates the capacitance associated with the column and
the cluster select transistors parasitic capacitance.
[0087] Since it is highly desirable to minimize column capacitance,
the optimal value for k may be found for EQ. 21 as: 17 k opt 0.5 V
( 1 + c M a C d ) ( EQ . 22 )
[0088] Once the optimal number of rows in a cluster is determined,
the column capacitance may be also derived from EQ. 21.
[0089] Continuing with the example presented hereinabove, for an
image sensor with 1,000 rows, on a 0.6 .mu.m CMOS process,
k.sub.opt.congruent.25. Thus, in this example, each half of the
image sensor array should be divided into 25 clusters, with 20 rows
in each, in order to achieve a minimum column capacitance of
C.sub.col.sup.2.congruen- t.0.55 pF.
[0090] Thus, through column segmentation and image sensor array
halving, column capacitance may be reduced approximately by a
factor of 7. This reduces the noise floor from about 1.5 mVolts to
less t 0.7 mVolts in the present example, and improves the
signal-to-noise ratio from approximately 1,000, to approximately
2300.
[0091] It is appreciated that several options are available by
which the necessary circuitry described hereinabove may be
implemented in a minimum of space. For example, the cluster line
may be implemented in M1, while the column line may be implemented
over the cluster line in M2. Alternatively, the cluster line may be
implemented in Poly, while the column line is implemented over the
cluster line in M1. The cluster selector lines may also be
implemented in Poly. This is feasible since the cluster selection
is done infrequently, once every 18 V 2 k
[0092] rows. Thus, the longer time it takes to precondition the
cluster for readout is insignificant. It is also possible to
alternate the readout between rows in the upper half of the image
sensor array and rows in the bottom half. This would effectively
double the readout time per row, and leave significant slack time
for cluster switching. If the cluster select line is implemented in
Poly, it could be placed over a ground line or a signal line which
runs in metal, thus reducing space requirements even further.
[0093] It is appreciated that one or more of the steps of any of
the methods described herein may be omitted or carried out in a
different order than that shown, without departing from the true
spirit and scope of the invention.
[0094] While the methods and apparatus disclosed herein may or may
not have been described with reference to specific hardware or
software, it is appreciated that the methods and apparatus
described herein may be readily implemented in hardware or software
using conventional techniques.
[0095] While the present invention has been described with
reference to one or more specific embodiments, the description is
intended to be illustrative of the invention as a whole and is not
to be construed as limiting the invention to the embodiments shown.
It is appreciated that various modifications may occur to those
skilled in the art that, while not specifically shown herein, are
nevertheless within the true spirit and scope of the invention.
* * * * *