U.S. patent application number 10/038963 was filed with the patent office on 2002-11-28 for system clock synchronisation using phase-locked loop.
Invention is credited to Goodings, Chris J., Young, Matthew.
Application Number | 20020177459 10/038963 |
Document ID | / |
Family ID | 9906181 |
Filed Date | 2002-11-28 |
United States Patent
Application |
20020177459 |
Kind Code |
A1 |
Young, Matthew ; et
al. |
November 28, 2002 |
System clock synchronisation using phase-locked loop
Abstract
An apparatus for synchronising the system clocks of wireless
devices in a digital communications system is presented. A digital
phase-locked loop is employed. The phase-locked loop may include a
counter which is incremented by a local device system clock and
latched by a frame synchronisation marker received from a remote
device, whereby the counter output comprises a feed forward signal.
The phase-locked loop may alternatively include a counter that
reflects the level of data stored in receive and/or transmit FIFO
buffers. The loop output signal controls the frequency of the
system clock oscillator.
Inventors: |
Young, Matthew; (Cove,
GB) ; Goodings, Chris J.; (Fleet, GB) |
Correspondence
Address: |
Law Offices of Dick and Harris
Suite 3800
181 West Madison Street
Chicago
IL
60602
US
|
Family ID: |
9906181 |
Appl. No.: |
10/038963 |
Filed: |
January 3, 2002 |
Current U.S.
Class: |
455/502 ;
455/87 |
Current CPC
Class: |
H04L 7/033 20130101;
H03L 7/091 20130101; H04M 1/725 20130101; H03L 7/181 20130101; H04J
3/062 20130101; H03L 7/085 20130101; H04B 7/2675 20130101; H04W
56/0035 20130101 |
Class at
Publication: |
455/502 ;
455/87 |
International
Class: |
H04B 007/005 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 3, 2001 |
GB |
0100094.2 |
Claims
I claim:
1. A wireless receiver which receives digital data from a remote
transmitter via a radiofrequency communications link comprised of a
plurality of data frames, which wireless receiver is comprised of:
a counter with a count input that is derived from a system clock
signal generated within the wireless receiver, the counter also
including a latch input that is derived from a frame
synchronisation signal generated during each data frame; a loop
filter with an input derived from the counter output; a loop gain
block, which gain block receives an input derived from the loop
filter output; a frequency-tuneable oscillator which receives the
output of the loop gain block and generates the system clock
signal, the frequency of the system clock signal being dependent
upon the loop gain block output; whereby the frequency of the
system clock signal is synchronized with the remote
transmitter.
2. The wireless receiver of claim 1, in which the loop gain block
input is comprised of the output of a summing block, the summing
block having a first input derived from the loop filter output and
a second input which receives a calibration value.
3. The wireless receiver of claim 1, in which the
frequency-tuneable oscillator is comprised of: a digital-to-analog
converter which receives a digital input signal derived from the
output of the loop gain block and generates an analog control
signal; and a voltage-controlled crystal oscillator which receives
the analog control signal and outputs the system clock signal,
where the frequency of the system clock signal is dependent upon
the analog control signal.
4. The wireless receiver of claim 3, in which the
voltage-controlled crystal oscillator is comprised of: a varactor
which receives the analog control signal as its tuning input; and a
crystal connected in parallel with the varactor.
5. A wireless receiver which receives digital data from a remote
transmitter via a radiofrequency communications link comprised of a
plurality of data frames and stores at least some of the received
digital data within a buffer, the wireless receiver being comprised
of: the buffer having a load input to which a signal is applied
causing data to be loaded into the buffer, and having a transfer
out input to which a signal is applied causing data to be read out
of the buffer; an up/down counter circuit which counts up when a
signal is applied to a first input derived from the buffer load
input and counts down when a signal is applied to a second input
derived from the buffer transfer out input, the counter also
including a latch input that is derived from a frame
synchronisation signal generated during each data frame; a loop
filter with an input derived from the counter output; a summing
block that includes a first input which receives a calibration
value and a second input derived from the loop filter output; a
loop gain block, which gain block receives an input derived from
the loop filter output; a frequency-tuneable oscillator which
receives the output of the loop gain block and generates the system
clock signal, the frequency of the system clock signal being
dependent upon the loop gain block output; whereby the frequency of
the system clock signal is synchronized with the remote
transmitter.
6. The wireless receiver of claim 5, in which the loop gain block
input is comprised of the output of a summing block, the summing
block having a first input derived from the loop filter output and
a second input which receives a calibration value.
7. The wireless receiver of claim 5, in which the
frequency-tuneable oscillator is comprised of: a digital-to-analog
converter which receives a digital input signal derived from the
output of the loop gain block and generates an analog control
signal; and a voltage-controlled crystal oscillator which receives
the analog control signal and outputs the system clock signal,
where the frequency of the system clock signal is dependent upon
the analog control signal.
8. The wireless receiver of claim 7, in which the
voltage-controlled crystal oscillator is comprised of: a varactor
which receives the analog control signal as its tuning input; and a
crystal connected in parallel with the varactor.
9. A method for synchronising a first system clock frequency within
a first wireless device with a second system clock within a second
wireless device, the first device and the second device
communicating via a radiofrequency communications link comprised of
a plurality of data frames, the method comprising the steps of:
receiving periodically a frame synchronisation signal by the first
wireless device from the second wireless device, the frame
synchronisation signal being indicative of the arrival of a data
frame; measuring the number of cycles of the first system clock
that occur between each frame synchronisation signal; adjusting the
frequency of the system clock such that the number of cycles
measured is equal to a predetermined value.
10. A method for controlling the frequency of an oscillator in a
first wireless device which communicates via a radiofrequency
communications link, the method comprising the steps of: receiving
digital data by the first wireless device via the communications
link; storing the received data into a buffer within the first
wireless device; reading data out from the buffer at a rate
determined by a system clock signal generated within the first
wireless device; determining the amount of data present within the
buffer; increasing the frequency of the system clock signal when
the amount of data within the buffer exceeds a predetermined level;
decreasing the frequency of the system clock signal when the amount
of data within the buffer falls below a predetermined level.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates in general to wireless digital
communications. In particular, the invention relates to the
synchronisation of base and mobile station system clocks in a
digital communications system such as a cordless telephone.
[0003] 2. Background Art
[0004] This proposal is concerned with matching the system clock
frequencies of two radio systems using a Time Division Duplex (TDD)
frame structure. The discussion is based on a digital cordless
telephone system, but the application is not limited to such a
system.
[0005] The system consists of a Basestation (BS) communicating with
a Handset (HS) in full-duplex. FIG. 1 shows the TDD frame
structure. The basestation transmits to the handset in first half
of the frame and the handset replies in the second half of the
frame. The hatched areas are reserved for future use and the grey
shaded area are guard bits to compensate for differences in the
local clocks.
[0006] Audio data is transmitted in bursts across the air. To
enable continuous audio be heard at the receiver buffers are used
to smooth out the bursts, as shown in FIG. 2. The rate at which the
buffers are filled and emptied is dependent upon the frequencies of
the crystals in the basestation and handset.
[0007] If the Basestation crystal frequency is slightly slower than
the handset crystal frequency then the Handset will empty its Rx
Buffer before the Basestation has filled it. This will result in
audio dropouts, causing irritation to the handset user.
[0008] The effect of the different crystal frequencies is to change
the sampling rate of the audio stream. As the audio stream is
arriving at the handset at a different sample frequency, one
solution to this problem is to oversample the incoming audio stream
and then resample it to match the local sample frequency. This will
prevent a break in the audio stream at the receiver. However the
resampling process has a large overhead in terms of microprocessor
loading.
[0009] An alternative approach is to adjust the handset and
basestation crystal frequency to match each other, the design of
such a system is described in this proposal.
SUMMARY OF THE INVENTION
[0010] In accordance with one aspect of the invention, a method for
synchronising a first system clock frequency within a first
wireless device with a second system clock within a second wireless
device, the first device and the second device communicating via a
radiofrequency communications link comprised of a plurality of data
frames, is presented. The method comprises the steps of: receiving
periodically a frame synchronisation signal by the first wireless
device from the second wireless device, the receipt of the frame
synchronisation signal being indicative of the arrival of a data
frame; and controlling the frequency of the first system clock
using a phase-locked loop, the phase-locked loop receiving the
frame synchronisation signal as an input. In accordance with
another aspect of the invention, a method for controlling the
frequency of a system clock within a first wireless device which
communicates via a radiofrequency communications link is presented.
This method comprises the steps of: receiving digital data by the
first wireless device via the communications link; storing the
received data into a buffer within the first wireless device;
reading data out from the buffer at a rate determined by the system
clock signal; determining the amount of data present within the
buffer; and controlling the frequency of the system clock signal
based upon the amount of data present within the buffer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a time-division duplexed digital radio frame
structure.
[0012] FIG. 2 is a block diagram of a digital radio communications
system.
[0013] FIG. 3 is a graph illustrating the level of data within
transmit and receive buffers of a digital radio communications
system.
[0014] FIG. 4 is a graph illustrating the change in receive buffer
level over time in an unsynchronised radio system.
[0015] FIG. 5 is a phased-locked loop for controlling the frequency
of a system clock in a digital radio communications system.
DETAILED DESCRIPTION OF THE INVENTION
[0016] While this invention is susceptible to embodiment in many
different forms, there are shown in the drawings and will be
described in detail herein specific embodiments. The present
disclosure is to be considered as an exemplification of the
principle of the invention intended merely to explain and
illustrate the invention, and is not intended to limit the
invention in any way to embodiments illustrated.
[0017] To transmit voice data between the two systems, the audio is
sampled at regular intervals by a first system. Each sample is then
compressed and placed in a First In First Out (FIFO) data buffer.
The compressed samples are taken from the FIFO, gathered into
packets, and transmitted in bursts over the air. When the packets
are received by a second system, the data is placed in a receive
FIFO. The compressed samples are then popped and decompressed at
regular intervals to produce a continuous audio stream to the
receiver. The dynamic transmit and receive FIFO levels are shown in
FIG. 3.
[0018] The two systems each operate from their own, independent
crystals. The crystals are frequency matched in production but will
drift away from each other over time and temperature variations. To
keep the two systems locked together in frequency, a bit counter is
used as described below.
[0019] The basestation transmits a synchronisation marker at the
beginning of the frame. On detecting the synchronisation marker the
handset resets its bit counter. The bit counter is then incremented
on the basestation and handset according to its own local clock.
This system prevents small differences in the local clock from
disrupting the reception of frame of data.
[0020] However, over many frames of data the difference between the
local clocks will have a detrimental effect on the FIFO behaviour.
As the handset frame is locked to the basestation frame then the
amount of data being pushed into the handset receive FIFO will
differ from the amount of data being popped out of the FIFO. This
will cause the Handset receive FIFO to either fill up or empty
depending on whether the basestation clock is faster or slower than
the handset clock.
[0021] In general it can be shown that the FIFO level drift is as
follows
L=d.fs.t+C
[0022] where:
[0023] L Average FIFO level (samples)
[0024] d Relative difference between the clock frequencies
[0025] fs Sample clock frequency (Hz)
[0026] t Time (s)
[0027] C Initial FIFO level (samples)
[0028] The proposal which is the subject of this application is to
use a Phase-Locked Loop (PLL) in the handset to lock the two
crystals together. The PLL system is shown in FIG. 5 below, and
consists of the following:
[0029] A Phase Detector
[0030] A Frame synchronisation marker
[0031] A Loop filter
[0032] Zero adjustment
[0033] Filter Gain
[0034] Digital to Analogue converter (DAC)
[0035] A Varactor to provide crystal frequency tuning
[0036] In the illustrated embodiment, the phase detector includes a
free running counter clocked by the system clock. The frame
synchronisation marker provides a latch for the counter. Phase
detector software calculates the difference in counter values each
time the counter is latched, accounting for when the counter
loops.
[0037] The output of the phase detector is fed to the loop filter.
The illustrated loop filter is a digital single pole IIR filter
implemented in software. The loop filter averages the phase
differences from the phase counter and provides the feed-forward
signal. While the illustrated filter provides simple
implementation, other averaging filters could readily be used.
[0038] An alternative method for phase detection, also claimed as
part of this proposal, would use the handset and basestation audio
FIFO counters, as shown in FIG. 4, to provide a measure of the
difference in frequency between the handset and basestation
crystals. This method could be implemented, for example, by
periodically performing a peak detection on the FIFO level, such
that changes in the FIFO level over time are detected. The system
clock can then be adjusted higher or lower to maintain a desired
FIFO level.
[0039] The loop gain provides tuning of the loop characteristics.
The DAC drives the varactor which in turn tunes the crystal
frequency. The zero adjustment allows for tuning of the system in
the factory. Note that the use of the DAC and varactor to tune
crystal frequency is not essential to this proposal. Other methods
for frequency tuning such as using a switched capacitor array in
parallel with a crystal could also be used to perform the tuning
function, and are therefore considered to be within the scope of
the invention.
[0040] This solution is efficient in hardware as it only requires
one extra counter to provide the relative phase information and a
DAC plus varactor to provide the frequency tuning.
[0041] The solution is also efficient in software as there is only
a loop filter calculation (requiring only 3 Multiply and accumulate
(MAC) instructions) and one multiply for the loop gain adjustment.
To further minimise the processing overhead the calculation can be
run after a number of frame synchronisation markers have been
received.
[0042] In conclusion, a system for synchronising the system clocks
of two radio systems has been proposed. The system uses a frame
synchronisation marker together with an efficient implementation of
Phase-Locked Loop. This system provides the following advantages
over other methods:
[0043] Low software implementation cost: A simple loop filter
calculation to be run at a fraction of the audio sampling rate.
This is opposed to audio resampling which requires a large number
of calculations to be run at a multiple of the audio sampling
rate.
[0044] Low hardware implementation cost: One hardware counter plus
a DAC and varactor to tune the crystal. The need for a hardware
loop filter has been removed as it is performed in software.
[0045] Flexibility: As the PLL is almost all in software it can be
changed and reconfigured to meet new system requirements.
[0046] The foregoing description and drawings merely explain and
illustrate the invention and the invention is not limited thereto,
inasmuch as those skilled in the art, having the present disclosure
before them will be able to make modifications and variations
therein without departing from the scope of the invention.
* * * * *