U.S. patent application number 09/837552 was filed with the patent office on 2002-11-28 for semiconductor device and manufacturing method thereof.
Invention is credited to Arai, Yasuyuki, Koyama, Jun, Ohtani, Hisashi, Yamazaki, Shunpei.
Application Number | 20020175376 09/837552 |
Document ID | / |
Family ID | 26581308 |
Filed Date | 2002-11-28 |
United States Patent
Application |
20020175376 |
Kind Code |
A1 |
Ohtani, Hisashi ; et
al. |
November 28, 2002 |
Semiconductor device and manufacturing method thereof
Abstract
In a CMOS circuit formed on a substrate 101, a subordinate gate
wiring line (a first wiring line) 102a and main gate wiring line (a
second wiring line) 107a are provided in an n-channel TFT. The LDD
regions 113 overlaps the first wiring line 102a and does not
overlap the second wiring line 107a. Thus, when a gate voltage is
applied to the first wiring line, the GOLD structure is formed,
while no applying forms the LLD structure. In this way, the GOLD
structure and the LLD structure can be used appropriately in
accordance with the respective specifications required for the
circuits.
Inventors: |
Ohtani, Hisashi; (Kanagawa,
JP) ; Yamazaki, Shunpei; (Tokyo, JP) ; Koyama,
Jun; (Kanagawa, JP) ; Arai, Yasuyuki;
(Kanagawa, JP) |
Correspondence
Address: |
NIXON PEABODY, LLP
8180 GREENSBORO DRIVE
SUITE 800
MCLEAN
VA
22102
US
|
Family ID: |
26581308 |
Appl. No.: |
09/837552 |
Filed: |
April 19, 2001 |
Current U.S.
Class: |
257/350 ;
257/347; 257/351; 257/E27.111; 257/E29.275 |
Current CPC
Class: |
H01L 29/78645 20130101;
H01L 27/1259 20130101; H01L 29/78648 20130101; H01L 27/1214
20130101; H01L 27/124 20130101; G02F 1/13454 20130101 |
Class at
Publication: |
257/350 ;
257/347; 257/351 |
International
Class: |
H01L 027/01 |
Claims
1. A semiconductor device including a CMOS circuit formed by an
n-channel TFT and a p-channel TFT, characterized in that: the CMOS
circuit has a structure that an active layer is sandwiched by a
first wiring line and a second wiring line through an insulating
layer in only the n-channel TFT, the active layer includes a low
concentration impurity region that is in contact with the channel
formation region; and the low concentration impurity region is
formed to overlap the first wiring line and not to overlap the
second wiring line.
2. A semiconductor device according to claim 1, characterized in
that the first wiring line is electrically connected with the
second wiring line.
3. A semiconductor device including a CMOS circuit formed by an
n-channel TFT and a p-channel TFT, characterized in that: the CMOS
circuit has a structure that an active layer is sandwiched by a
first wiring line and a second wiring line through an insulating
layer in only the n-channel TFT; and the second wiring line has a
portion of a laminated structure of a first conductive layer and a
second conductive layer, and a portion of a structure in which a
third conductive layer is wrapped by the first conductive layer and
the second conductive layer.
4. A semiconductor device according to claim 3, characterized in
that the third conductive layer has a lower resistance value than a
first conductive layer or the second conductive layer.
5. A semiconductor device according to claim 3, characterized in
that the first wiring line or the second wiring line is a
conductive film mainly containing an element selected from the
group consisting of tantalum (Ta), titanium (Ti), tungsten (W),
molybdenum (Mo), and silicon (Si), or an alloy film or silicide
film containing the above elements in combination.
6. A semiconductor device according to claim 3, characterized in
that the third wiring line is a conductive film mainly containing
aluminum (Al) or copper (Cu).
7. A semiconductor device including a pixel matrix circuit that has
a pixel TFT formed by an n-channel TFT and a storage capacitor,
characterized in that: the pixel TFT has a structure that an active
layer is sandwiched by a first wiring line and a second wiring line
through an insulating layer, the active layer includes a low
concentration impurity region that is in contact with the channel
formation region; and the low concentration impurity region is
formed to overlap the first wiring line and not to overlap the
second wiring line.
8. A semiconductor device according to claim 7, characterized in
that the first wiring line is kept at the ground electric potential
or at the source power supply electric potential.
9. A semiconductor device according to claim 7, characterized in
that the first wiring line is kept at the floating electric
potential.
10. A semiconductor device including a pixel matrix circuit that
has a pixel TFT formed by an n-channel TFT and a storage capacitor,
characterized in that: the pixel TFT has a structure that an active
layer is sandwiched by a first wiring line and a second wiring line
through an insulating layer, the second wiring line has a portion
of a laminated structure of a first conductive layer and a second
conductive layer, and a portion of a structure in which a third
conductive layer is wrapped by the first conductive layer and the
second conductive layer.
11. A semiconductor device according to claim 10, characterized in
that the third conductive layer has a lower resistance value than
the first conductive layer or the second conductive layer.
12. A semiconductor device according to claim 10, characterized in
that the first wiring line or the second wiring line is a
conductive film mainly containing an element selected from the
group consisting of tantalum (Ta), titanium (Ti), tungsten (W),
molybdenum (Mo), and silicon (Si), or an alloy film or silicide
film containing the above elements in combination.
13. A semiconductor device according to claim 10, characterized in
that the third wiring line is a conductive film mainly containing
aluminum (Al) or copper (Cu).
14. A semiconductor device having a pixel matrix circuit and a
driver circuit that are formed on the same substrate, characterized
in that: a pixel TFT included in the pixel matrix circuit and an
n-channel TFT included in the driver circuit have a structure that
an active layer is sandwiched by a first wiring line and a second
wiring line through an insulating layer; and the first wiring line
connected to the pixel TFT is kept at the fixed electric potential
or the floating electric potential, and the first wiring connected
to the n-channel TFT included in the driver circuit is kept at the
same level of electric potential as the second wiring line
connected to the n-channel TFT included in the said driver
circuit.
15. A semiconductor device according to claim 14, characterized in
that the active layer includes a low concentration impurity region
that is in contact with the channel formation region; and the low
concentration impurity region is formed to overlap the first wiring
line and not to overlap the second wiring line.
16. A semiconductor device according to claim 14, characterized in
that the second wiring line has a portion of a laminated structure
of a first conductive layer and a second conductive layer, and a
portion of a structure in which a third conductive layer is wrapped
by the first conductive layer and the second conductive layer.
17. A semiconductor device according to claim 14, characterized in
that the third conductive layer has a lower resistance value than a
first conductive layer or the second conductive layer.
18. A semiconductor device according to claim 14, characterized in
that the first wiring line or the second wiring line is a
conductive film mainly containing an element selected from the
group consisting of tantalum (Ta), titanium (Ti), tungsten (W),
molybdenum (Mo), and silicon (Si), or an alloy film or silicide
film containing the above elements in combination.
19. A semiconductor device according to claim 14, characterized in
that the third wiring line is a conductive film mainly containing
aluminum (Al) or copper (Cu).
20. A semiconductor device, characterized in that the semiconductor
device according to any one of claims 1 to 19 is an active matrix
liquid crystal display or an active matrix EL display.
21. A semiconductor device, characterized in that the semiconductor
device according to any one of claims 1 to 19 is a video camera, a
digital camera, a projector, a projection TV, a goggle type
display, an automobile navigation system, a personal computer, or a
portable information terminal.
22. A manufacturing method of a semiconductor device including a
CMOS circuit formed by an n-channel TFT and a p-channel TFT
comprising: a process of forming a first wiring line on a
substrate, a process of forming a first insulating layer on the
first wiring line, a process of forming active layers, an active
layer of the n-channel TFT and an active layer of the p-channel
TFT, on the first insulating layer, a process of forming a second
insulating layer to overlap the active layer of the n-channel TFT
and the active layer of the p-channel layer, and a process of
forming a second wiring line on the second insulating layer; and
characterized in that the first wiring line is formed to cross only
the active layer of the n-channel TFT.
23. A manufacturing method of a semiconductor device according to
claim 22, characterized in that the second wiring line has a
portion of a laminated structure of a first conductive layer and a
second conductive layer, and a portion of a structure in which a
third conductive layer is wrapped by the first conductive layer and
the second conductive layer.
24. A manufacturing method of a semiconductor device including a
CMOS circuit formed by an n-channel TFT and a p-channel TFT
comprising: a process of forming a first wiring line on a
substrate, a process of forming a first insulating layer on the
first wiring line, a process of forming active layers, an active
layer of the n-channel TFT and an active layer of the p-channel
TFT, on the first insulating layer, a process of forming a second
insulating layer to overlap the active layer of the n-channel TFT
and the active layer of the p-channel layer, a process of forming a
first conductive layer on the second insulating layer, a process of
forming a patterned third conductive layer on the first conductive
layer, and a process of forming a second conductive layer to
overlap the third conductive layer; and characterized in that the
first wiring line is formed to cross only the active layer of the
n-channel TFT.
25. A manufacturing method of a semiconductor device according to
claim 23 or 24, characterized in that a material with a lower
resistance value than the first conductive layer or the second
conductive layer is used as the third conductive layer.
26. A manufacturing method of a semiconductor device according to
claim 23 or 24, characterized in that the first wiring line or the
second wiring line is a conductive film mainly containing an
element selected from the group consisting of tantalum (Ta),
titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si), or
an alloy film or silicide film containing the above elements in
combination.
27. A manufacturing method of a semiconductor device according to
claim 23 or 24, characterized in that the third conductive layer is
a conductive film mainly containing aluminum (Al) or copper (Cu).
Description
DETAILED DESCRIPTION OF THE INVENTION
[0001] 1. [Technical Field to Which the Invention Belongs]
[0002] The present invention relates to a semiconductor device
having a circuit composed of a thin film transistor (hereinafter
referred to as TFT). For example, the invention relates to an
electro-optical device represented by a liquid crystal display
panel and to electronic equipment mounted with the electro-optical
device as a component.
[0003] In this specification, a `semiconductor device` refers to a
device in general that can function by utilizing semiconductor
characteristics, and electro-optical devices, semiconductor
circuits, and electronic equipment are semiconductor devices.
[0004] 2. [Prior Art]
[0005] A thin film transistor (hereinafter referred to as TFT) can
be formed on a transparent glass substrate, and hence its
application to an active matrix liquid crystal display (hereinafter
referred to as AM-LCD) has been developed actively. Since a TFT
utilizing a crystalline semiconductor film (typically, a
polysilicon film) can provide high mobility, it is considered that
it is possible to integrate functional circuits on the same
substrate for realizing high definition image display.
[0006] An active matrix liquid crystal display device requires a
million TFTs only for pixels when the resolution of the screen is
high definition. When functional circuits are further added, more
TFTs become necessary. Each TFT has to have secured reliability and
be operated stably in order to realize stable operation of the
liquid crystal display device.
[0007] However, the TFT is considered as not so equal in terms of
reliability to a MOSFET that is formed on a single crystal
semiconductor substrate. In the TFT, phenomena lowering of mobility
and ON current occur when it is operated for a long period of time,
as the MOSFET with the same problem. One of causes of the phenomena
is characteristic degradation due to hot carriers that accompany
increase of a channel electric field.
[0008] In The MOSFET, on the other hand, the LDD (lightly doped
drain) structure is well known as a technique for improving
reliability. In this structure, low concentration impurity regions
are further provided inside source and drain regions. The low
concentration impurity region is called an LDD region. Some TFTs
employ the LDD structure.
[0009] It is another known structure for the MOSFET to make the LDD
region somewhat overlap a gate electrode with a gate insulating
film sandwiched therebetween. There are several methods for forming
this structure. For example, structures called GOLD (Gate-drain
overlapped LDD) and LATID (Large-tilt-angle implanted drain) are
known. Withstanding against the hot carrier can be enhanced by such
structures.
[0010] There have been attempts to apply these structures of
MOSFETs to TFTs. However, application of the GOLD structure (in
this specification, a structure having an LDD region to which a
gate voltage is applied is called a GOLD structure whereas a
structure having only an LDD region to which a gate voltage is not
applied is called an LDD structure) to a TFT has a problem that OFF
current (current which flows when the TFT is in an OFF state) is
larger compared to the LDD structure. Therefore, the GOLD structure
is not suitable for a circuit in which OFF current should be as
small as possible, such as a pixel matrix circuit of an AM-LCD.
[0011] [Problems to be Solved by the Invention]
[0012] An object of the present invention is to provide an AM-LCD
having high reliability by form circuits of the AM-LCD of TFTs
having suitable structures in accordance with the respective
functions of the circuits. The invention aims to accordingly
enhance the reliability of a semiconductor device (electronic
equipment) having such AM-LCD.
[0013] [Means for Solving the Problems]
[0014] According to a structure of the present invention disclosed
in this specification , a semiconductor device including a CMOS
circuit formed by an n-channel TFT and a p-channel TFT,
characterized in that:
[0015] the CMOS circuit has a structure that an active layer is
sandwiched by a first wiring line and a second wiring line through
an insulating layer in only the n-channel TFT,
[0016] the active layer includes a low concentration impurity
region that is in contact with the channel formation region;
and
[0017] the low concentration impurity region is formed to overlap
the first wiring line and not to overlap the second wiring
line.
[0018] In the above structures, the first wiring line may be
electrically connected with the second wiring line. That is, a
first wiring line and a second wiring line are in the same electric
potential, and it becomes possible to add the same voltage to an
active layer.
[0019] According to another structure of the present invention, a
semiconductor device including a CMOS circuit formed by an
n-channel TFT and a p-channel TFT, characterized in that:
[0020] the CMOS circuit has a structure that an active layer is
sandwiched by a first wiring line and a second wiring line through
an insulating layer in only the n-channel TFT; and
[0021] the second wiring line has a portion of a laminated
structure of a first conductive layer and a second conductive
layer, and a portion of a structure in which a third conductive
layer is wrapped by the first conductive layer and the second
conductive layer.
[0022] In the above structures, a material with a lower resistance
value than the first conductive layer or the second conductive
layer is used as the third conductive layer. Concretely, the first
conductive layer or the second conductive layer is preferably a
conductive film mainly containing an element selected from the
group consisting of tantalum (Ta), titanium (Ti), tungsten (W),
molybdenum (Mo), and silicon (Si), or an alloy film or silicide
film containing the above elements in combination. And the third
wiring line is preferably a conductive film mainly containing
aluminum (Al) or copper (Cu).
[0023] According to another structure of the present invention, a
semiconductor device including a pixel matrix circuit that has a
pixel TFT formed by an n-channel TFT and a storage capacitor,
characterized in that:
[0024] the pixel TFT has a structure that an active layer is
sandwiched by a first wiring line and a second wiring line through
an insulating layer,
[0025] the active layer includes a low concentration impurity
region that is in contact with the channel formation region;
and
[0026] the low concentration impurity region is formed to overlap
the first wiring line and not to overlap the second wiring
line.
[0027] In the above structures, the first wiring line may be kept
at the ground electric potential or at the source power supply
electric potential, or may be kept at the floating electric
potential.
[0028] According to another structure of the present invention, a
semiconductor device including a pixel matrix circuit that has a
pixel TFT formed by an n-channel TFT, characterized in that:
[0029] the pixel TFT has a structure that an active layer is
sandwiched by a first wiring line and a second wiring line through
an insulating layer,
[0030] the second wiring line has a portion of a laminated
structure of a first conductive layer and a second conductive
layer, and a portion of a structure in which a third conductive
layer is wrapped by the first conductive layer and the second
conductive layer.
[0031] According to another structure of the present invention, a
semiconductor device having a pixel matrix circuit and a driver
circuit that are formed on the same substrate, characterized in
that:
[0032] a pixel TFT included in the pixel matrix circuit and an
n-channel TFT included in the driver circuit have a structure that
an active layer is sandwiched by a first wiring line and a second
wiring line through an insulating layer; and
[0033] the first wiring line connected to the pixel TFT is kept at
the fixed electric potential or the floating electric potential,
and the first wiring connected to the n-channel TFT included in the
driver circuit is kept at the same level of electric potential as
the second wiring line connected to the n-channel TFT included in
the said driver circuit.
[0034] In the above structures, the active layer includes a low
concentration impurity region that is in contact with the channel
formation region and the low concentration impurity region is
formed to overlap the first wiring line and not to overlap the
second wiring line.
[0035] Further, the second wiring line has a portion of a laminated
structure of a first conductive layer and a second conductive
layer, and a portion of a structure in which a third conductive
layer is wrapped by the first conductive layer and the second
conductive layer.
[0036] According to another structure of the present invention, a
manufacturing method of a semiconductor device including a CMOS
circuit formed by an n-channel TFT and a p-channel TFT
comprising:
[0037] a process of forming a first wiring line on a substrate, a
process of forming a first insulating layer on the first wiring
line,
[0038] a process of forming active layers, an active layer of the
n-channel TFT and an active layer of the p-channel TFT, on the
first insulating layer,
[0039] a process of forming a second insulating layer to overlap
the active layer of the n-channel TFT and the active layer of the
p-channel layer, and
[0040] a process of forming a second wiring line on the second
insulating layer; and
[0041] characterized in that the first wiring line is formed to
cross only the active layer of the n-channel TFT.
[0042] In the above structures, the second wiring line has a
portion of a laminated structure of a first conductive layer and a
second conductive layer, and a portion of a structure in which a
third conductive layer is wrapped by the first conductive layer and
the second conductive layer.
[0043] According to another structure of the present invention, a
manufacturing method of a semiconductor device including a CMOS
circuit formed by an n-channel TFT and a p-channel TFT
comprising:
[0044] a process of forming a first wiring line on a substrate, a
process of forming a first insulating layer on the first wiring
line,
[0045] a process of forming active layers, an active layer of the
n-channel TFT and an active layer of the p-channel TFT, on the
first insulating layer,
[0046] a process of forming a second insulating layer to overlap
the active layer of the n-channel TFT and the active layer of the
p-channel layer, and
[0047] a process of forming a first conductive layer on the second
insulating layer,
[0048] a process of forming a patterned third conductive layer on
the first conductive layer, and
[0049] a process of forming a second conductive layer to overlap
the third conductive layer; and
[0050] characterized in that the first wiring line is formed to
cross only the active layer of the n-channel TFT.
[0051] [Embodiment Mode of the Invention]
[0052] [Embodiment Mode 1]
[0053] An embodiment mode of the present invention will be
described taking as an example a CMOS circuit (inverter circuit) in
which an n-channel TFT (hereinafter referred to as NTFT) is
combined with a p-channel TFT (hereinafter referred to as
PTFT).
[0054] A sectional structure thereof is shown in FIG. 1A and a top
view thereof is shown in FIG. 1B. The description will be given
using symbols which are common to FIG. 1A and FIG. 1B. The
sectional views taken along the lines A-A', B-B', and C-C' in FIG.
1B correspond to the sectional views A-A', B-B', and C-C' in FIG.
1A, respectively.
[0055] In FIG. 1A, 101 denotes a substrate; 102a, 102b, and 102c,
first wiring lines; 103, a first insulating layer; 104, an active
layer of NTFT; 105, an active layer of PTFT; and 106, a second
insulating layer.
[0056] Thereon, there are a second wiring line 107a laminated as a
first conductive layer 107a1 and a second conductive layer 107a2,
similarly a second wiring line 107b laminated as a first conductive
layer 107b1 and a second conductive layer 107b2, a second wiring
line 107c laminated as a first conductive layer 107c1 and a second
conductive layer 107c2, and a second wiring line 107d which has a
structure of sandwiching a third conductive layer d3 with a first
conductive layer 107d1 and a second conductive layer 107d2.
[0057] 108 is a first interlayer insulating layer, 109 to 111 are
third wiring lines, 109 and 110 are source wiring lines (including
source electrodes), and 111 is a drain wiring line (including a
drain electrode).
[0058] In the CMOS circuit structured as above, a glass substrate,
a quartz substrate, a metal substrate, a stainless steel substrate,
a plastic substrate, a ceramic substrate, or a silicon substrate
may be used as the substrate 100. When a silicon substrate is used,
it is appropriate to oxidize its surface to form a silicon oxide
film in advance.
[0059] Although the first wiring line is a wiring line of the same
pattern as shown in FIG. 1B, it is sectioned into 102a, 102b, and
102c for the sake of explanation. Here, the first wiring line 102a
represents an intersection with the active layer 103, the first
wiring line 102b represents a connection between the TFTs, and the
first wiring line 102c represents a power supplying portion which
is common to the respective circuits.
[0060] The first wiring line 102a here functions as a subordinate
gate electrode of the NTFT. That is, the electric charge of the
channel formation region 112 is controlled by the first wiring line
102a and by the second wiring line (main gate electrode) 107a that
is given with the same electric potential as the first wiring line
102a, so that only the first wiring line 102a can apply a gate
voltage (or a predetermined voltage) to the LDD regions 113.
[0061] Accordingly, the GOLD structure is not obtained with only
the second wiring line 107a functioning as the gate electrode (the
LDD structure is obtained instead), until the first wiring line
102a joins with the second wiring line 107a. Advantages of this
structure will be described later. The first wiring line 102a also
functions as a light-shielding layer.
[0062] Any material can be used for the first wiring line as long
as it has conductivity. However, a desirable material is one having
heat resistance against the temperature in a later process. For
example, a conductive film mainly containing (50% or more
composition ratio) an element selected from the group consisting of
tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and
silicon (Si), or an alloy film or silicide film containing the
above elements in combination.
[0063] Given as a feature of this embodiment mode is providing the
first wiring line 102a only in the NTFT and not in the PTFT.
Although the PTFT in FIG. 1A does not have an offset region or an
LDD region either, one of the regions or both of the regions may be
formed in the PTFT.
[0064] With the structure as above, the first wiring line is led
from the power supplying portion through the connection to the NTFT
to function as a subordinate gate electrode of the NTFT as shown in
FIG. 1B.
[0065] Although the second wiring line is also a wiring line of the
same pattern, for the sake of explanation, it is sectioned with
almost the same way as the first wiring line is sectioned. In FIG.
1A, 107a represents an intersection with the active layer of the
NTFT 104, 107b represents an intersection with the active layer of
the PTFT 105, 107c represents a connection between the TFTs, and
107d represents a power supplying portion.
[0066] A second wiring line is formed by laminating two kinds of
conductive layers basically. Any upper layer and any lower layer
can be used as long as it has a conductivity, a tantalum (Ta) film,
a titanium (Ti) film, a tungsten (W) film, a molybdenum (Mo) film,
and a silicon (Si) film may be used in any combination to form the
second wiring lines. An alloy film or silicide film of those may
also be used.
[0067] It is necessary to select materials so as to be possible to
pattern to the same form after laminating. That is, the
combination, which can make it possible to etch the lower layer
side with the upper layer side as a mask, is desirable. And a
conductive layer provided as the lower layer must obtain an etching
selective ratio to the third conductive layer 107d3.
[0068] The third conductive layer 107d3 is a conductive film mainly
containing aluminum (Al) or copper (Cu), (the component ratio is
more than 50%), and the second wiring line is formed by a structure
wrapped with the first conductive layer 107d1 and the second
conductive layer 107d2 (hereinafter referred to as a cladding
structure). This second wiring line 107d forms a wiring line which
is corresponding to the power supply portion.
[0069] The CMOS circuit is an inverter circuit much used as a
driver circuit of AM-LCD and other signal process circuits. Since
these driver circuit and signal process circuit are integrated in
high density, it is desirable to make the width of the wiring line
narrow to the utmost. Therefore, the crossing portion (a gate
electrode portion) with active layers and the connecting portion (a
portion drawing wiring lines) are designed to be as narrow as
possible. the lengths of the wiring lines itself in these portion
are not so long that it is hardly affected by resistance of the
wiring lines.
[0070] In the power supply portion, however, the length of a wiring
line itself is so long that it is much affected by resistance of
the wiring line. Therefore, in the present embodiment mode, a
material mainly containing aluminum or copper with low resistance
is used to reduce resistance of the wiring line. With the structure
such as the second wiring line 107d, the width of the wiring line
is a little wide, but it is no problem because the power supply
portion is formed outside complicatedly integrated circuits.
[0071] Like an AM-LCD having a diagonal size of 4 inch or less, in
the case of applying the present invention to the semiconductor
device with wholly small circuits and without extremely long wiring
lines, a wiring line to be the power supply portion is also so
short that it is unnecessary to use the above-mentioned cladding
structure. In other words, it can be said that the structure as
shown in FIG. 1 is effective for an AM-LCD with a diagonal size of
4 inch or more.
[0072] As described above, the CMOS circuit of this embodiment mode
has the two characteristics as follows;
[0073] 1. The first wiring line (subordinate gate wiring line) is
provided only in the NTFT and the same voltage as the second wiring
line (main gate wiring line) or a predetermined voltage is applied
to the first wiring line, thereby giving the NTFT the GOLD
structure.
[0074] 2. The gate electrode portion and the connecting portion of
the second wiring line are made narrow and integrated, and the
power supply portion is made to have low resistance with a
structure in which the third conductive layer with low resistance
is sandwiched with the first and the second conductive layers (the
cladding structure).
[0075] [Embodiment Mode 2]
[0076] An embodiment mode of the present invention will be
described taking as an example a pixel matrix circuit that uses an
NTFT as a pixel TFT. This pixel matrix circuit is formed on the
same substrate as the CMOS circuit described in Embodiment Mode 1
at the same time. Therefore, the description in Embodiment Mode 1
may be referred to for details of the wiring lines with the
identical names.
[0077] A sectional structure of the pixel matrix circuit is shown
in FIG. 2A and a top view thereof is shown in FIG. 2B. The
description will be given using common symbols to FIG. 2A and FIG.
2B. The sectional views taken along the lines A-A' and B-B' in FIG.
2B correspond to the sectional views A-A' and B-B' in FIG. 2A,
respectively
[0078] In FIG. 2A, 201 denotes a substrate; 202a, 202b and 202c,
first wiring lines; 203, a first insulating layer; 204, an active
layer of a pixel TFT (NTFT); and 205, a second insulating layer.
The pixel TFT shown here as an example has a double gate structure,
but a single gate structure or a multi-gate structure in which
three or more TFTs are connected in series may be adopted.
[0079] On the second insulating layer 203, a second wiring line
206a with a structure in which a third conductive layer 206a3 is
sandwiched with a first conductive layer 206a1 and a second
conductive layer 206a2, a second wiring line 206b laminated as a
first conductive layer 206b1 and a second conductive layer 206b2, a
second wiring line 206c laminated as a first conductive layer 206c1
and a second conductive layer 206c2, and a capacitor wiring line
207 laminated as a first conductive layer 207a and a second
conductive layer 207b.
[0080] Here, a storage capacitor is formed between the capacitor
wiring line 207 and an active layer 204 (namely, a region extended
from the drain region) with the first insulating layer 205 as
dielectric. In this case, when the first insulating layer 205 is
made to have a laminate structure of a silicon nitride and a
silicon oxide film provided thereon and a second wiring line is
formed after selectively removing the silicon oxide film of the
portion to be the storage capacitor, it is realized that the
storage capacitor has only a silicon nitride film with high
dielectric constant as a dielectric.
[0081] Denoted by 208 is a first interlayer insulating layer, 209
and 210, third wiring lines, 209, a source wiring line (including a
source electrode), and 215, a drain wiring line (including a drain
electrode). Formed thereon are a second interlayer insulating layer
211, a black mask 212, a third interlayer insulating layer 213, and
a pixel electrode 214.
[0082] Although the first wiring line is a wiring line of the same
pattern as shown in FIG. 2B, it is sectioned into 202a, 202b, and
202c for the sake of explanation. Here, the first wiring line 202a
represents a wiring line portion that does not function as a gate
electrode, whereas 202b and 202c are intersections with the active
layer 204 and function as the gate electrodes.
[0083] The first wiring lines shown here are formed at the same
time when the first wiring lines described in Embodiment Mode 1 are
formed. Therefore the material and other explanations thereof are
omitted.
[0084] The first wiring lines 202b and 202c function as
light-shielding films of the pixel TFT. In other words, they do not
have the function as the subordinate gate wiring line as described
in Embodiment Mode 1, and are given a fixed electric potential or
set to a floating state (an electrically isolated state). The fixed
electric potential may be a ground electric potential or a source
power supply electric potential (at the same electric potential as
a source wiring line). Then, holes generated by hot carrier
injection can be removed from the channel formation regions, and as
a result, electric charge is neutralized to disappear hot
carrier.
[0085] Electric charges in the channel formation regions 215 and
216 are thus controlled by the first wiring lines 206b and 206c to
provide the LDD structure. Therefore, an increase of OFF current
can be contained effectively.
[0086] The pixel matrix circuit shown in this embodiment mode thus
has an NTFT as its pixel TFT, and the structure is the same as the
NTFT of the CMOS circuit explained in Embodiment Mode 1. However,
the NTFT in the pixel matrix circuit is different from the NTFT in
the CMOS circuit in which the GOLD structure is obtained by using
the first wiring line as a subordinate gate wiring line through
applying a predetermined voltage, since the LDD structure is
obtained by giving the first wiring lines a fixed electric
potential or setting them to a floating state in the pixel matrix
circuit.
[0087] In other words, the biggest feature of the present invention
is that NTFTs with the same structure are formed on the same
substrate and then respectively given the GOLD structure or the LDD
structure, with or without being applied a voltage to their first
wiring lines (subordinate gate wiring lines). This makes the
optimal circuit design possible without increasing the number of
manufacture steps.
[0088] With respect to second wiring lines 206a, 206b and 206c,
206b and 206c are gate electrode portions and 206a is a wiring line
portion. Since it is desirable that resistance of the wiring line
is lowered as much as possible in the wiring line portion, a
cladding structure is adopted. But in the gate electrode portion,
since the width of the wiring line decides the length of a channel,
it is designed to make the width of lines narrow by laminating the
first conductive layer and the second conductive layer.
[0089] Details and the effect of the cladding structure is
explained in Embodiment Mode 1, therefore explanation is omitted
here. And as described in Embodiment Mode 1. Needless to say, it is
unnecessary that an AM-LCD with a diagonal size of 4 inch or less
adopts a cladding structure.
[0090] The structures of the present invention in the above will be
described in detail in the following embodiments.
[0091] [Embodiment 1]
[0092] In this embodiment, a method of manufacturing the CMOS
circuit described in Embodiment Mode 1 will be described. The
description will be given with reference to FIG. 3.
[0093] First, a glass substrate is prepared as a substrate 301, and
first wiring lines 302a, 302b, and 302c are formed thereon. The
material of the first wiring lines is a laminated film, that a
tungsten silicide (WSix) film and a silicon film are laminated in
order by sputtering. The order of laminating can of course be
reversed and the CVD method can be used as means of depositing.
Further, it is effective to form oxide film on the surface after
forming the above-mentioned laminated film in the sense of
protection of the surface.
[0094] Other metal films, alloy films, or the like may of course be
used as long as the first wiring lines 302a, 302b, and 302c are any
film with conductivity. A chromium film or a tantalum film that can
be formed into a pattern with a small taper angle is effective in
improving the levelness.
[0095] A second insulating layer 303 of an insulating film
containing silicon is formed next. The first insulating layer 303
functions as a gate insulating film in using the first wiring line
302a as a subordinate gate wiring line, as well as performs as a
base film to protect an active layer.
[0096] This embodiment employs a laminate structure in which a
silicon nitride film with a thickness of 50 nm is formed first and
a silicon oxide film with a thickness of 80 nm is formed thereon. A
silicon oxynitride film expressed as SiO.sub.xN.sub.y (x/y=0.01 to
100) may be used. In this case, the voltage to withstand thereof
can be enhanced by making the nitrogen content larger than the
oxygen content.
[0097] Next, an amorphous silicon film (not shown in the drawing)
with a thickness of 50 nm is formed and a crystalline silicon film
is formed by crystallizing using a known laser crystallization
technique. And the crystalline silicon film is patterned to form
active layers 304 and 305. In the process of crystallization in
this embodiment, an amorphous silicon film is irradiated by
processing the pulse-oscillating type KrF excimer laser light into
a linear beam.
[0098] Although this embodiment uses as a semiconductor film for
the active layers a crystalline silicon film obtained by
crystallizing an amorphous silicon film, other semiconductor films
such as a microcrystalline silicon film may be used or a
crystalline silicon film may be deposited directly. A compound
semiconductor film such as a silicon germanium film may be used
except silicon films.
[0099] A second insulating layer 306 is formed next of a silicon
oxide film, a silicon oxynitride film, or a silicon nitride film,
or a laminate film of those so as to cover the active layers 304
and 305. A silicon oxynitride film is formed here by plasma CVD to
a thickness of 100 nm. The second insulating layer functions as a
gate insulating film when the second wiring line is used as a main
gate wiring line.
[0100] Next, a tantalum film 307 with a thickness of 20 nm is
formed as a first conductive layer, and a third conductive layer
308 of an aluminum film to which scandium is added, is formed
thereon. And a second conductive layer 309 of a tantalum film is
formed to have a thickness of 200 nm. Either sputtering or CVD can
be used to form these films.
[0101] After the state of FIG. 3A is thus obtained, resist masks
310 and 311 are formed to etch the first conductive layer 307 and
the second conductive layer 309. In this way, a second wiring line
312 is formed of the laminate structure of the tantalum films. The
second wiring line 312 corresponds to the second wiring line (main
gate wiring line) 107a in FIG. 1A.
[0102] Next, an element which belongs to Group 15 (typically,
phosphorus or arsenic) is doped to form low concentration impurity
regions 313. A channel formation region of the NTFT is defined
simultaneously. In this embodiment, phosphorus is used as the
element which belongs to Group 15, and ion doping method that does
not perform mass separation is employed. (FIG. 3B)
[0103] Doping conditions include setting the acceleration voltage
to 90 keV, and adjusting the dose so that phosphorus is contained
in a concentration of 1.times.10.sup.16 to 1.times.10.sup.19
atoms/cm.sup.3 (preferably 5.times.10.sup.17 to 5.times.10.sup.18
atoms/cm.sup.3). This concentration later becomes the impurity
concentration in the LDD regions, and hence is needed to be
controlled precisely.
[0104] The resist masks 310 and 311 are then removed and resist
masks 315 to 318 are newly formed. The first conductive layer 307
and the second conductive layer 309 are etched to form second
wiring lines 319 to 321. The second wiring lines 319, 320 and 321
respectively correspond to the second wiring lines 107b, 107c and
107d of FIG. 1A.
[0105] Next, an element which belongs to Group 13 (typically boron
or gallium) is doped to form an impurity region 322. At this time,
a channel formation region 323 of the PTFT is defined
simultaneously. In this embodiment, boron is used as the element
which belongs to Group 13, and ion doping method that does not
perform mass separation is employed. (FIG. 3C)
[0106] Doping conditions include setting the acceleration voltage
to 75 keV, and adjusting the dose so that boron is contained in a
concentration of 1.times.10.sup.19 to 5.times.10.sup.21
atoms/cm.sup.3 (preferably 1.times.10.sup.20 to 1.times.10.sup.21
atoms/cm.sup.3).
[0107] The resist masks 315 to 318 are then removed and resist
masks 324 to 327 are formed again. In this embodiment, the resist
masks are formed by using a back side exposure method. For the
resist masks 324, 326 and 327, the first wiring lines serve as
masks whereas the second wiring lines serve as masks for the resist
mask 325. With the first wiring lines as masks, a small amount of
light reaches behind the wiring lines and hence the line width in
this case is narrower than the width of the first wiring lines. The
line width can be controlled by exposure conditions.
[0108] The resist masks can of course be formed by using masks
instead. In this case, the degree of freedom in pattern design is
raised but the number of masks is increased.
[0109] After the resist masks 324 to 327 are thus formed, a step of
doping an element which belongs to Group 15 (phosphorus in this
embodiment) is conducted. Here, the acceleration voltage is set to
90 keV, and the dose is adjusted so that phosphorus is contained in
a concentration of 1.times.10.sup.19 to 5.times.10.sup.21
atoms/cm.sup.3 (preferably 1.times.10.sup.20 to 1.times.10.sup.21
atoms/cm.sup.3).
[0110] Through this step, a source region 328, a drain region 329
and LDD regions 330 of the NTFT are defined. Further, a source
region 331 and a drain region 332 of the PTFT are defined. A source
region and a drain region of the PTFT are also doped with
phosphorus in this step. However, the P type conductivity thereof
can be maintained without reversing to the N type conductivity if
they are doped with boron in a higher concentration in the previous
step.
[0111] After the NTFT and the PTFT are thus doped with impurity
elements each imparting one of the conductivity types, the impurity
elements are activated by furnace annealing, laser annealing, or
lamp annealing, or by using these annealing methods in
combination.
[0112] The state of FIG. 3D is obtained in this way. Then a first
interlayer insulating layer 333 is formed of a silicon oxide film,
a silicon nitride film, a silicon oxynitride film, or a resin film,
or a laminate film of those films. Contact holes are opened to form
source wiring lines 334 and 335 and a drain wiring line 336. (FIG.
3E).
[0113] The first interlayer insulating layer 333 in this embodiment
has a two-layered structure in which a silicon nitride film with a
thickness of 50 nm is formed first and a silicon oxide film with a
thickness of 950 nm is formed thereon. The source wiring lines and
the drain wiring line in this embodiment are formed by patterning a
three-layered laminate structure obtained by successively forming,
by sputtering, a titanium film with a thickness of 100 nm, an
aluminum film containing titanium and having a thickness of 300 nm,
and another titanium film with a thickness of 150 nm.
[0114] A CMOS circuit with a structure as shown in FIG. 3E is thus
completed. The CMOS circuit of this embodiment has the structure
shown in FIG. 1A, and the explanation thereof is omitted here
because it is described in detail in Embodiment Mode 1. To obtain
the structure of FIG. 1A, the manufacturing process is not
necessarily limited to this embodiment. For example, the NTFT may
take the double gate structure while the PTFT is given the single
gate structure.
[0115] The CMOS circuit described in this embodiment serves as a
basic unit circuit for constructing a driver (driving) circuit
(including a shift register circuit, a buffer circuit, a level
shifter circuit, a sampling circuit, etc.) and other signal
processing circuits (such as a divider circuit, a D/A converter
circuit, a .gamma. correction circuit, and an operation amplifier
circuit) in an AM-LCD.
[0116] In this embodiment, the first wiring line of the NTFT is
used as a subordinate gate wiring line to thereby obtain a
substantial GOLD structure and prevent degradation due to hot
carrier injection. Accordingly, a circuit with a very high
reliability can be formed.
[0117] By narrowing the width of wiring lines in a part with high
integration and by using a cladding structure in a part (an
electric power supplying portion) which does not have so high
integration, The structure, in which resistance of wiring lines is
reduced and the delayed time because of resistance of wiring lines
are reduced, is realized.
[0118] [Embodiment 2]
[0119] In this embodiment, a method of manufacturing the pixel
matrix circuit described in Embodiment Mode 2 will be described.
The description will be given with reference to FIGS. 4 and 5. The
pixel matrix circuit is formed on the same substrate as the CMOS
circuit shown in Embodiment 1 at the same time. Therefore, the
description will be given in relation to the manufacturing process
of Embodiment 1 and the same symbols as those in FIG. 3 are used
when necessary.
[0120] First, second wiring lines 401a, 401b, and 401c are formed
on the glass substrate 301. The second wiring lines have the
material as described in Embodiment 1. Next, the first insulating
layer 303, an active layer of a pixel TFT 402, the second
insulating layer 306, the first conductive layer 307, a third
conductive layer 403 and the second conductive layer 309 are formed
consulting Embodiment 1. Thus obtained is the state of FIG. 4A. The
CMOS circuit being formed simultaneously is now in the state of
FIG. 3A.
[0121] Next, resist masks 404 to 407 are formed to etch the first
conductive layer 307 and the second conductive layer 309. Second
wiring lines 408 and 409 and a capacitor wiring line 410 are thus
formed. The second wiring line 408 corresponds to the second wiring
line 206b in FIG. 2A and the second wiring line 409 corresponds to
the second wiring line 206c in FIG. 2A. Further, the capacitor
wiring line 410 corresponds to the capacitor wiring line 207 in
FIG. 2A.
[0122] The phosphorus doping step for forming LDD regions later is
conducted next to form low concentration impurity regions 411 to
413. Channel formation regions 414 and 415 are defined
simultaneously. This step corresponds to the step of FIG. 3B.
Accordingly, the material and thickness of the second wiring lines
and phosphorus doping conditions in the step of FIG. 4B are the
same as Embodiment 1.
[0123] A step which is corresponding to the step of FIG. 3C is
conducted next. First, resist masks 416 and 417 are formed to etch
the first conductive layer 307 and the second conductive layer 309,
and thus a second wiring line 418 is formed. This second wiring
line 418 corresponds to the second wiring line 206a in FIG. 2A.
[0124] Next, the boron doping step for forming the PTFT of the CMOS
circuit is conducted. In this Embodiment, the pixel matrix circuit
is entirely covered with a resist mask 417 because a pixel TFT is
formed of NTFT. (FIG. 4C)
[0125] After the resist mask 416 and 417 are then removed, resist
masks 419 to 422 are formed by the back side exposure method. Then
the phosphorus doping step is conducted to form a source region
423, a drain region 424 and a LDD region 425. The conditions of the
back side exposure and phosphorus doping may be set in accordance
with the step of FIG. 3D in Embodiment 1.
[0126] The source region and the drain region in FIG. 4D are named
so for the sake of explanation. However, a source region and drain
region in a pixel TFT are reversed between charging and discharging
and hence there is no definite discrimination between the two
regions.
[0127] After the doping steps of phosphorus and boron are finished,
the impurity elements are activated as in Embodiment 1. Then the
first interlayer insulating film 333 is formed and contact holes
are formed therein to form a source wiring line 426 and a drain
wiring line 427. The state of FIG. 4E is thus obtained. The CMOS
circuit at this point is in the state of FIG. 3E.
[0128] Next, a second interlayer insulating layer 428 is formed to
cover the source wiring line 426 and the drain wiring line 427. In
this embodiment, a silicon nitride film with a thickness of 30 nm
is formed as a passivation film and an acrylic film with a
thickness of 700 nm is formed thereon. Of course, an insulating
film mainly containing silicon such as a silicon oxide film, or
other resin films may be used. Other resin films that are usable
are a polyimide film, a polyamide film, a BCB (benzocyclobutene)
film, and the like.
[0129] Next, a black mask 429 is formed of a titanium film with a
thickness of 100 nm. Other films may be used to form the black mask
427 if they have light-shielding property. Typically, a chromium
film, an aluminum film, a tantalum film, a tungsten film, a
molybdenum film, a titanium film, or a laminate of these films is
used.
[0130] A third interlayer insulating layer 430 is then formed.
Though an acrylic film with a thickness of 1 .mu.m is used in this
embodiment, the same material as the second interlayer insulating
layer may be used instead.
[0131] A contact hole is next formed in the third interlayer
insulating layer 430 to form a pixel electrode 431 of a transparent
conductive film (typically an ITO film). The pixel electrode 431 is
electrically connected to the drain wiring line 427. Since the
contact hole accordingly has to be very deep, and hence it is
effective in preventing failure such as break of the pixel
electrode to form the contact hole with its inner wall tapered or
curved.
[0132] A pixel matrix circuit with a structure as shown in FIG. 5A
is thus completed. Although the example shown in this embodiment is
an example of manufacturing a transmission type AM-LCD using a
transparent conductive film as a pixel electrode, a reflection type
AM-LCD can readily be manufactured when a metal film with high
reflectance (such as a metal film mainly containing aluminum) is
used as the pixel electrode.
[0133] The substrate in the state of FIG. 5A is called an active
matrix substrate. This embodiment also describes a structure in the
case of actually manufacturing an AM-LCD.
[0134] After the state of FIG. 5A is obtained, an orientation film
432 with a thickness of 80 nm is formed. An opposite substrate is
fabricated next. The opposite substrate prepared is a glass
substrate 433 on which a color filter 434, a transparent electrode
(opposite electrode) 435, and an orientation film 436 are formed.
The orientation films 432 and 435 are subjected to rubbing
treatment, and the active matrix substrate is bonded to the
opposite substrate using a seal (sealing member). Then a liquid
crystal 436 is held therebetween. A spacer for maintaining the cell
gap may be provided if necessary.
[0135] An AM-LCD with a structure as shown in FIG. 5B (the part of
a pixel matrix circuit) is thus completed. The second interlayer
insulating layer 428 and the third interlayer insulating layer 430
of this embodiment is also formed over the CMOS circuit shown in
Embodiment 1 in actuality. When the black mask 429 and the pixel
electrode 431 are formed, wiring lines maybe formed, at the same
time, of the same materials that constitute the black mask and the
pixel electrode, and the wiring lines may be used as lead out
wiring lines (fourth wiring lines or fifth wiring lines) of a
driver circuit and signal processing circuit of the AM-LCD.
[0136] In this embodiment, the first wiring lines 401b and 401c
provided in the pixel TFT are set to the fixed electric potential
(the ground electric potential or the source electric potential).
This makes it possible to draw holes generated in the drain end due
to hot carrier injection to the first wiring lines, thereby
improving the reliability. Although the first wiring lines 401b and
401c may of course be set to a floating state, the hole drawing
effect cannot be expected in this case.
[0137] As shown in the top view of FIG. 2B, the second wiring line
418 deposited in the wiring line portion adopts the cladding
structure to reduce resistance of wiring lines as much as
possible.
[0138] [Embodiment 3]
[0139] In this embodiment, an AM-LCD is provided with a pixel
matrix circuit and a CMOS circuit (concretely, a driver circuit and
signal processing circuit constructed of CMOS circuits) according
to the present invention, and the appearance thereof is shown in
FIG. 6.
[0140] On an active matrix substrate 601, a pixel matrix circuit
602, a signal line driving circuit (source driver circuit) 603,
scanning line driving circuits (gate driver circuits) 604, and a
signal processing circuit (including a signal divider circuit, a
D/A converter circuit, and a .gamma. correction circuit) 605 are
formed, and an FPC (flexible printed circuit) 606 is attached.
Denoted by 607 is an opposite substrate.
[0141] The various circuits formed on the active matrix substrate
601 are illustrated in detail in a block diagram of FIG. 7.
[0142] In FIG. 7, 701 denotes a pixel matrix circuit that functions
as an image display unit. 702a, 702b, and 702c represent a shift
register circuit, a level shifter circuit, and a buffer circuit,
respectively. The three together constitute a gate driver
circuit.
[0143] In the block diagram of the AM-LCD in FIG. 7, the gate
driver circuits are provided to sandwich a pixel matrix circuit and
to share the same gate wiring lines. This is, application of
voltage to the gate wiring lines is still possible even after one
of the gate drivers has failure occurred, thereby giving the AM-LCD
redundancy. 703a, 703b, 703c, and 703d represent a shift register
circuit, a level shifter circuit, a buffer circuit, and a sampling
circuit, respectively. The four together constitute a source driver
circuit. A precharge circuit 14 is provided at the opposite side of
the source driver circuit across the pixel matrix circuit.
[0144] The reliability of an AM-LCD having circuits as shown in
FIG. 6 can be greatly improved by employing the present invention.
In this case, CMOS circuits which form a driver circuit and a
signal processing circuit are made in accordance with Embodiment 1
and a pixel matrix circuit is made in accordance with Embodiment
2.
[0145] [Embodiment 4]
[0146] This embodiment gives a description on a case where a CMOS
circuit is structured differently from Embodiment 1 and a pixel
matrix circuit is structured differently from Embodiment 2. To be
specific, circuits are given different structures in accordance
with the specifications the circuits demand.
[0147] The basic structure of the CMOS circuit is the structure
shown in FIG. 1A and the basic structure of the pixel matrix
circuit is the structure shown in FIG. 2A. Therefore only the part
that needs explanation is denoted by a symbol and explained in this
embodiment.
[0148] The structure shown in FIG. 8A lacks an LDD region at the
source side of the NTFT and has an LDD region 801 only at the drain
side. The CMOS circuit, which is used for a driver circuit and a
signal processing circuit, is required to operate at high speed and
hence resist components that can cause reduction in operation speed
have to be removed as much as possible.
[0149] In the case of the CMOS circuit according to the present
invention, a gate voltage is applied to a first wiring line which
functions as a subordinate gate wiring line to obtain the GOLD
structure and prevent degradation due to hot carrier injection.
However, it is sufficient that an LDD region that is overlapped
with a gate electrode is formed at an end of a channel formation
region at the drain region side where hot carriers are
injected.
[0150] Accordingly, an LDD region at an end of the channel
formation region at the source region side is not indispensable. On
the contrary, the LDD region provided at the source region side
might work as a resist component. The structure as FIG. 8A is
therefore effective in improving the operation speed.
[0151] The structure of FIG. 8A cannot be applied to a circuit that
behaves like a pixel TFT in which a source region and a drain
region are switched. Since a source region and a drain region of a
CMOS circuit are normally fixed, the structure such as FIG. 8A can
be realized.
[0152] FIG. 8B is basically the same as FIG. 8A, but the width of
an LDD region 802 in FIG. 8B is narrower than in FIG. 8A.
Specifically, the width is set to 0.05 to 0.5 .mu.m (preferably 0.1
to 0.3 .mu.m). The structure in FIG. 8B is capable of not only
reducing the resist component at the source region side but also
reducing the resist component at the drain region side as much as
possible.
[0153] This structure is actually suitable for a circuit that is
driven at as low voltage as 3 to 5 V and is required to operate at
high speed, such as a shift register circuit. Since the operation
voltage is low, the narrow LDD region (LDD region that is
overlapped with a gate electrode, strictly speaking) does not raise
the problem of hot carrier injection.
[0154] Of course, LDD regions in the NTFT may be completely omitted
in some cases if the omission is limited to the shift register
circuit. In this case, the NTFT of the shift register circuit has
no LDD region while other circuits in the same driver circuit
employ the structure shown in FIG. 1A or the structure shown in
FIG. 8B.
[0155] Next, FIG. 8C shows an example of a CMOS circuit in which
its NTFT has the double gate structure and PTFT has the single gate
structure. In this case, LDD regions 805 and 806 are provided only
at ends of channel formation regions 803 and 804 which are closer
to drain regions.
[0156] The width of an LDD region is determined by the amount of
light that reaches around in the back side exposure step, as shown
in FIG. 3D. However, if resist masks are formed by mask alignment,
the masks can be designed freely. Forming an LDD region only at one
side is easy also in the structure shown in FIG. 8C if a mask is
used.
[0157] However, forming an LDD region only at one side by the back
side exposure method is possible when gate wiring lines (second
wiring lines) 807a and 807b are formed so as to be shifted from
first wiring lines 808 and 809 as in this embodiment.
[0158] This structure eliminates the resist component due to an LDD
region at the source side, and the double gate structure has an
effect of diffusing and easing the electric field applied between
the source and the drain.
[0159] The structure in FIG. 8D is a mode of a pixel matrix
circuit. In the structure of FIG. 8D, LDD regions 809 and 810 are
provided at either the side closer to the source region or the side
closer to the drain region. In other words, no LDD region is
provided between two channel formation regions 811 and 812.
[0160] In the case of a pixel TFT, a source region and a drain
region are frequently switched since charging and discharging are
repeated. Accordingly, when the pixel TFT has a structure of FIG.
8D, the LDD region is always provided at the drain region side of
the channel formation region whichever region serves as the drain
region. On the other hand, it is effective in increasing ON current
(current flowing when the TFT is in an ON state) to omit an LDD
region to be a resist component since there is no electric field
concentration between the channel formation regions 811 and
812.
[0161] An LDD region is not provided at an end of the channel
formation region at the source region side in the structures of
FIGS. 8A to 8D. However, the LDD region may be provided there if it
has a narrow width. This structure may be obtained by forming
resist masks through mask alignment or by the back side exposure
method after the positions of the first wiring lines and the second
wiring lines are adjusted.
[0162] Needless to say, the structure of this embodiment can be
combined with Embodiments 1 and 2, and applied to the AM-LCD shown
in Embodiment 3.
[0163] [Embodiment 5]
[0164] This embodiment shows, with reference to FIG. 9, a case of
forming a storage capacitor with a different structure from the
pixel matrix circuit shown in Embodiment 2. Since the fundamental
structure is the same as FIG. 2A, only necessary parts are denoted
by the symbols in this embodiment and explained.
[0165] In the structure shown in FIG. 9A, a storage capacitor is
formed of a capacitor wiring line 901 which is formed in the same
layer as the first wiring line, a first insulating layer 902, and
an active layer 903 (strictly speaking, the portion extended from a
drain region).
[0166] This structure has the advantage of having conductivity
since an element which belongs to Group 13 or 15 is doped at high
concentration into a portion of the active layer which functions as
an electrode of the storage capacitor. The element which belongs to
Group 13 or 15 may of course be formed at the same time as the
process of forming a source region or a drain region.
[0167] In the case of the structure described in "Embodiment Mode
2", the active layer which functions as the electrode of the
storage capacitor is not doped with the impurity element which give
a conductivity because the second wiring line performs a mask, the
state that an inverse layer is formed in the active layer by
applying a voltage to the capacitor wiring line at all times, must
be kept. In the structure of FIG. 9A, however, the active layer
itself which functions as the electrode of the storage capacitor
has a conductivity, and it is not necessary to apply voltage and
what has to be done is only fixing in the ground electric
potential.
[0168] Thus, it can be said that it is an effective structure to
lower power consumption because it is unnecessary that the extra
voltage is applied.
[0169] The structure of FIG. 9B is an example of combining the
structure of the storage capacitor shown in FIG. 2A with the
structure of the storage capacitor shown in FIG. 9A. Concretely, a
first storage capacitor is formed of a first capacitor wiring line
904 which is in the same layer as the first wiring line, a first
insulating layer 905 and an active layer 906, and a second storage
capacitor is formed of the active layer 906, a second insulating
layer 907 and a second capacitor wiring line 908 which is in the
same layer as the first wiring line.
[0170] This structure can ensure a nearly double capacitor of the
structure of the storage capacitor shown in FIG. 2A and FIG. 9A
without increasing the number of process. Specially, the AM-LCD
with higher definition requires the storage capacitor with a
smaller surface area in order to improve the aperture ratio. In
such a case, the structure of FIG. 9B is effective.
[0171] It is effective to use the structure of this embodiment in
AM-LCD shown in Embodiment 3.
[0172] Embodiment [6]
[0173] This embodiment shows, with reference to FIG. 10, an example
of a case in which the first conductive layer that consists of the
second wiring line is omitted in the CMOS circuit shown in FIG. 1A
and in the pixel matrix circuit shown in FIG. 2A. In FIG. 10A, the
same structures as FIG. 1A or FIG. 2A are denoted by the same
symbols.
[0174] In the CMOS circuit of FIG. 10A, all of second wiring lines
11 to 13 are formed of a tantalum film with a single layer, that
is, are a structure having the first conductive layer omitted and
having the second wiring line formed of only the second conductive
layer, compared with the structure of FIG. 1A. The thickness is 200
to 400 nm. Except tantalum, a conductive film mainly containing an
element selected from the group consisting of titanium, tungsten,
molybdenum, and silicon, or an alloy film or silicide film
containing the above elements in combination may of course be
used.
[0175] In the case of this structure, the power supply portion (the
portion denoted as the cladding structure in FIG. 1A) of the second
wiring line has a structure in which the third conductive layer 14a
is covered by the second conductive layer 14b. Undesirably, this
structure might allow aluminum or copper that is an element
constituting the third conductive layer 14a to diffuse into a
second insulating layer 106. Therefore, when a silicon nitride film
is formed on the surface of the second insulating layer 106, it is
possible to prevent diffusion of aluminum or copper
effectively.
[0176] The structure of this embodiment may also be applied to a
pixel matrix circuit. The pixel matrix circuit in FIG. 10B uses
only a second conductive layer (a tantalum film in this embodiment)
for a second wiring line (a gate wiring line) 16 and 17 and a
capacitor wiring line, and employs the structure in which a third
conductive layer 15a is covered with a second conductive layer 15b
for a part of the gate wiring line that is required to reduce
wiring line resistance.
[0177] Needless to say, the circuits shown in FIG. 10A and FIG. 10B
are both formed on the same substrate at the same time.
[0178] The structure of this embodiment can be realized only by
omitting a process of forming the first conductive layer in the
manufacturing process shown in Embodiment 1 and Embodiment 2. It
can also be applied to the AM-LCD of Embodiment 3 and can be
combined with the structure shown in Embodiment 4 and 5.
[0179] [Embodiment 7]
[0180] This embodiment shows, with reference to FIG. 11, an example
of a case in which the gate electrode portion of the NTFT has a
cladding structure in the CMOS circuit shown in FIG. 1A and in the
pixel matrix circuit shown in FIG. 2A. In FIG. 11A, the same
structures as FIG. 1A or FIG. 2A are denoted by the same
symbols.
[0181] In the CMOS circuit shown in FIG. 1A, the gate electrode 21
of the NTFT has a cladding structure in which a third conductive
layer 21c is wrapped with a first conductive layer 21a and a second
conductive layer 21b. The length of a channel formation region 22
is coincident with the line width of a third conductive layer
21c.
[0182] The LDD region 23 can be substantially divided into two
regions. One is overlapped with a gate electrode 21 which is a
portion of the second wiring line, the other is not overlapped with
the gate electrode 21. In the structure of this embodiment, the
GOLD structure is realized only with a gate electrode which is a
portion of the second wiring line. Since the LDD region which is
not overlapped with a gate electrode is provided outside the LDD
region which is overlapped with a gate electrode, OFF current can
be made much smaller.
[0183] Similarly, in the pixel matrix circuit shown in FIG. 11B,
both gate electrodes 24 and 25 of the pixel TFT adopts the cladding
structure in which third conductive layers 24c and 25c are
respectively wrapped with first conductive layers 24a and 25a and
second conductive layers 24b and 25b. The lengths of channel
formation regions 26 and 27 are coincident with the widths of lines
of third conductive layers 24c and 25c, respectively. Both the LDD
regions 28 and 29 can be substantially divided into two regions in
the same way as the LDD region 23.
[0184] In the case of the structures shown in "Embodiment Mode 1"
and "Embodiment Mode 2", the GOLD structure is realized by adding a
gate voltage to the first wiring lines (subordinate gate wiring
lines) in the CMOS circuit while the LDD structure is adopted to
reduce OFF current in the pixel matrix circuit in order to avoid
increase in OFF current which is a disadvantage of the GOLD
structure. Therefore, the advantage of the GOLD structure which
prevents degradation of ON current can not be obtained.
[0185] In this embodiment, however, even in the pixel matrix
circuit, the NTFT with the GOLD structure is realized, and it can
be possible to improve the reliability more. Of course, it is the
very reason for the pixel TFT with the GOLD structure to provide
the LDD region which is not overlapped with a gate electrode
outside the LDD region which is overlapped with the gate
electrode.
[0186] Here, a description is given, with reference to FIG. 12, on
the manufacturing process to realize the structure of this
embodiment. Since it is fundamentally same as the process described
in Embodiment 1, the new symbols are used only when necessary.
[0187] First, a third conductive layer 308 is formed in accordance
with the process of Embodiment 1. In the case of this embodiment, a
third conductive layer 31 on the NTFT at the same time as when the
third conductive layer 308 is formed. Then, a resist mask 32 is
formed and the phosphorus doping step is conducted. With respect to
the doping condition, the process of FIG. 3B in Embodiment 1 may be
referred to. Through this step, the low concentration impurity
regions 33 and 34 are formed and the channel formation region 35 is
defined. (FIG. 12A)
[0188] After the resist mask 32 is removed, second conductive
layers 36 and 37 are formed. Through this step, a main gate wiring
line of NTFT 38 is formed. (FIG. 12B)
[0189] Next, resist masks 315 to 318 are formed, and then the boron
doping step is conducted. With the doping condition, the process of
FIG. 3C in Embodiment 1 may be referred to. Thus, after the
phosphorus doping step and the boron doping step are conducted, the
doped impurity element is activated in the same way as Embodiment 1
to obtain the state of FIG. 12C.
[0190] Next, after the resist masks 315 to 318 are removed, the
back side exposure method is used to form resist masks 324 to 327,
and the phosphorus doping step is then conducted. With respect to
the doping conditions, the process of FIG. 3D in Embodiment 1 may
be referred to.
[0191] Through this step, a source region 39, a drain region 40 and
low concentration impurity regions (the LDD regions) 41 of the NTFT
are formed. (FIG. 12D)
[0192] At this time, the length of the portion of the LLD region 41
with which the gate electrode 38 is overlapped, is set to 0.1 to
3.5 .mu.m (typically 0.1 to 0.5 .mu.m, preferably 0.1 to 0.3 .mu.m)
whereas the length of the portion with which the gate electrode 38
is not overlapped, is set to 0.5 to 3.5 .mu.m (typically 1.5 to 2.5
.mu.m).
[0193] Thereafter, a CMOS circuit with such a structure as shown in
FIG. 11A is completed by forming the first interlayer insulating
layer 108, the source wiring lines 109 and 110 and the drain wiring
line 111, through the same step as Embodiment 1.
[0194] Although he description in this embodiment takes as an
example the manufacturing step of a CMOS circuit, the structure of
FIG. 11B may be obtained through the similar manufacturing step
also in the pixel matrix circuit. Therefore, the description here
is omitted.
[0195] Further, the structure of this embodiment can be applied to
the AM-LCD of Embodiment 3 and can be freely combined with the
structure shown in Embodiments 4 to 6.
[0196] [Embodiment 8]
[0197] In the process of FIG. 3D in Embodiment 1, it is effective
that the second insulating layer 306 is etched to be removed after
the back side exposure method is used to form resist masks 324 to
327, and the exposed active layer is doped with phosphorus.
[0198] This can lower the acceleration voltage in doping phosphorus
to 100 keV, and reduce the burden of the doping device. The
throughput is also greatly improved. This is the same in the step
shown in FIG. 4D in Embodiment 2.
[0199] The structure of this embodiment can also be applied to the
AM-LCD of Embodiment 3 and can be freely combined with the
structure shown in Embodiments 4 to 7.
[0200] [Embodiment 9]
[0201] This embodiment gives a description with reference to FIG.
13 on the structure for reducing OFF current of NTFT in a CMOS
circuit used in a driver circuit.
[0202] In FIG. 13, the LDD region 51 can be substantially divided
into two portions in which one is overlapped and the other is not
overlapped with a first wiring line 102a. Therefore, when a gate
voltage is applied to the first wiring line 102a, the structure of
the NTFT of FIG. 13 has the LDD region which is not overlapped with
a gate electrode outside the LDD region which is overlapped with a
gate electrode.
[0203] As described in Embodiment 8, this structure has an effect
that degradation of ON current is prevented, which is the advantage
of the GOLD structure, and obtains electrical characteristics that
increase of OFF current, which is the defect of the GOLD structure,
is suppressed. Accordingly, a CMOS circuit with very high
reliability can be realized.
[0204] Here, although an example of a CMOS circuit is described,
the structure of this embodiment may be applied to a pixel matrix
circuit.
[0205] To realize the structure of this embodiment, the back side
exposure method may not be used in the process shown in FIG. 3D in
Embodiment 1. That is, the structure of this embodiment can be
readily obtained by performing a step of doping phosphorus after
providing the wider resist masks than the first wiring line with
usual mask alignment.
[0206] With respect to the lengths of the LDD region (the lengths
of the portion that is overlapped and the portion that is not
overlapped with a gate electrode), the range shown in Embodiment 8
may be referred to.
[0207] The structure of this embodiment can also be applied to the
AM-LCD of Embodiment 3 and can be freely combined with the
structure shown in Embodiments 4 to 7.
[0208] [Embodiment 10]
[0209] This embodiment describes a case in which other methods
except laser crystallization is used to form the active layer shown
in Embodiment 1 or 2
[0210] Specifically, a case is described in which a crystalline
semiconductor film used as an active layer is formed by the thermal
crystallization method using a catalytic element. In the case of
using the catalytic element, it is desirable to use the technique
disclosed in Japanese Patent Application Laid-open No. Hei 7-130652
(corresponding to U.S. patent application Ser. No. 08/329,644 or
U.S. patent application Ser. No. 08/430,623) and Japanese Patent
Application Laid-open No. Hei 8-78329. Specially, it is preferable
to use nickel as the catalytic element.
[0211] The structure of this embodiment can be combined freely with
all of the structures of Embodiments 1 through 9.
[0212] [Embodiment 11]
[0213] This embodiment describes a case, as a method of forming an
active layer, in which the thermal crystallization method shown in
Embodiment 10 is used and the catalytic element used is removed
from the crystalline semiconductor film. To remove the catalytic
element, this embodiment employs the technique disclosed in
Japanese Patent Application Laid-open No. Hei 10-135468
(corresponding to U.S. patent application Ser. No. 08/951,193) or
Japanese Patent Application Laid-open No. Hei 10-135469
(corresponding to U.S. patent application Ser. No. 08/951,819).
[0214] It is the technique described in the publication to remove a
catalytic element used in crystallization of an amorphous
semiconductor film by utilizing gettering effect of halogen after
the crystallization. With this technique, the concentration of the
catalytic element in the crystalline semiconductor film can be
reduced to 1.times.10.sup.17 atoms/cm.sup.3 or less, preferably to
1.times.10.sup.16 atoms/cm.sup.3.
[0215] The structure of this embodiment can be combined freely with
all of the structures of Embodiments 1 through 10.
[0216] [Embodiment 12]
[0217] This embodiment describes a case, as a method of forming an
active layer, in which the thermal crystallization method shown in
Embodiment 10 is used and the catalytic element used is removed
from the crystalline semiconductor film. To remove the catalytic
element, this embodiment employs the technique disclosed in
Japanese Patent Application Laid-open No. Hei 10-270363
(corresponding to U.S. patent application Ser. No. 09/050,182).
[0218] It is the technique described in the publication to remove a
catalytic element used in crystallization of an amorphous
semiconductor film by utilizing the gettering effect of phosphorus
after the crystallization. With this technique, the concentration
of the catalytic element in the crystalline semiconductor film can
be reduced to 1.times.10.sup.17 atoms cm.sup.3or less, preferably
to 1.times.10.sup.16 atoms/cm.sup.3.
[0219] The structure of this embodiment can be combined freely with
all of the structures of Embodiments 1 through 10.
[0220] [Embodiment 13]
[0221] This embodiment describes another mode of the gettering step
with phosphorus which is shown in Embodiment 12. The basic process
follows FIG. 1 and hence differences are picked out and
explained.
[0222] First, the state of FIG. 3D is obtained by following the
process of Embodiment 1. FIG. 14A shows a state in which the resist
masks 324 to 327 are removed from the state of FIG. 3D. A
semiconductor layer to become an active layer of TFT is formed by
using a technique of the thermal crystallization shown in
Embodiment 10.
[0223] At this point, the source region 328 of the NTFT and the
drain region 329 thereof, and the source region 331 of the PTFT and
the drain region 332 thereof contain phosphorus in a concentration
of 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3
(preferably 5.times.10.sup.20 atoms/cm.sup.3).
[0224] In this state, a heat treatment step is conducted in a
nitrogen atmosphere at 500 to 800.degree. C. for 1 to 24 hours, for
example, at 600.degree. C. for 12 hours, in this embodiment.
Through the step, the doped impurity elements that give n type and
p type can be activated. Further, the catalytic element (nickel in
this embodiment) remained after the crystallization step moves in
the direction of the arrow and is gettered (trapped) by the
above-mentioned action of phosphorus included in the source regions
and drain regions. As a result, the nickel concentration in the
channel formation region can be reduced to 1.times.10.sup.17
atoms/cm.sup.3 or less.
[0225] Once the process of FIG. 14B is completed, subsequent
processes are conducted in accordance with the processes of
Embodiment 1 to manufacture the CMOS circuit shown in FIG. 3E.
Needless to say, similar processes are performed in the pixel
matrix circuit.
[0226] The structure of this embodiment can be combined freely with
all of the structures of Embodiments 1 through 10.
[0227] [Embodiment 14]
[0228] The TFT structure of the present invention can be applied
not only to electro-optical devices such as AM-LCDs but also to
every kind of semiconductor circuit. It may be applied to
microprocessors such as RISC processors and ASIC processors, to
signal processing circuits such as D/A converters, and to high
frequency circuits for portable equipment (cellular phones
including PHS, and mobile computers).
[0229] Further, it is possible to obtain a semiconductor device
with a three-dimensional structure in which an interlayer
insulating film is formed on a conventional MOSFET and the present
invention is applied to form a semiconductor circuit thereon. The
present invention thus is applicable to all of the semiconductor
devices that currently employ LSIs. That is, the present invention
may be applied to the SOI structure (a TFT structure using a single
crystal semiconductor thin film) such as SIMOX, Smart-Cut (trade
name of SOITEC), and ELTRAN (trade name of Canon, Inc.).
[0230] The semiconductor circuits of this embodiment can be
realized by using a structure obtained from any combination of
Embodiments 1, 2 and 4 through 13.
[0231] [Embodiment 15]
[0232] A CMOS circuit and pixel matrix circuit formed by carrying
out the present invention can be applied to various electro-optical
devices and semiconductor circuits. That is, the present invention
is applicable to all of electronic devices that incorporate those
electro-optical devices and semiconductor circuits as
components.
[0233] Given as such electronic devices are video cameras, digital
cameras, projectors, projection TVs, head mounted displays (goggle
type displays), automobile navigation systems, personal computers,
portable information terminals (mobile computers, cellular phones,
electronic books or the like), etc. Examples of those are shown in
FIG. 15.
[0234] FIG. 15A shows a cellular phone, which is composed of a main
body 2001, an audio output unit 2002, an audio input unit 2003, a
display device 2004, operation switches 2005, and an antenna 2006.
The present invention is applicable to the audio output unit 2002,
the audio input unit 2003, the display device 2004, and other
signal controlling circuits.
[0235] FIG. 15B shows a video camera, which is composed of a main
body 2101, a display device 2102, an audio input unit 2103,
operation switches 2104, a battery 2105, and an image receiving
unit 2106. The present invention is applicable to the display
device 2102, the audio input unit 2103, and other signal
controlling circuits.
[0236] FIG. 15C shows a mobile computer, which is composed of a
main body 2201, a camera unit 2202, an image receiving unit 2203,
operation switches 2204, and a display device 2205. The present
invention is applicable to the display device 2205 and other signal
controlling circuits.
[0237] FIG. 15D shows a goggle type display, which is composed of a
main body 2301, display devices 2302, and arm units 2303. The
present invention is applicable to the display devices 2302 and
other signal controlling circuits.
[0238] FIG. 15E shows a rear projector, which is composed of a main
body 2401, a light source 2402, a display device 2403, a
polarization beam splitter 2404, reflectors 2405 and 2406, and a
screen 2407. The present invention is applicable to the display
device 2403 and other signal controlling circuits.
[0239] FIG. 15F shows a front projector, which is composed of a
main body 2501, a light source 2502, a display device 2503, an
optical system 2504, and a screen 2505. The present invention is
applicable to the display device 2502 and other signal controlling
circuits.
[0240] As described above, the applicable range of the present
invention is so wide that it can be applied to electronic devices
in every field. The electronic devices of this embodiment can be
realized by using a structure obtained from any combination of
Embodiments 1 through 14.
[0241] [Effect of the Invention]
[0242] The present invention is characterized in that the same NTFT
can be used as both the GOLD structure and the LDD structure by
controlling the voltage of a first wiring line provided under an
active layer. In other words, the GOLD structure and the LDD
structure can be formed on the same substrate without increasing
the number of processes or complicating the process.
[0243] Therefore, in the semiconductor device such as an AM-LCD and
electronic device that has the AM-LCD as a display, circuits with
optimal functions can be arranged in accordance with the
specifications required for the circuits, thus greatly improving
the performance and reliability of the semiconductor device.
BRIEF DESCRIPTION OF THE INVENTION
[0244] [FIG. 1] shows a structure of a CMOS circuit.
[0245] [FIG. 2] shows a structure of a pixel matrix circuit.
[0246] [FIG. 3] shows a process of manufacturing a CMOS
circuit.
[0247] [FIG. 4] shows a process of manufacturing a pixel matrix
circuit.
[0248] [FIG. 5] shows a process of manufacturing a pixel matrix
circuit.
[0249] [FIG. 6] shows the outside appearance of AM-LCD.
[0250] [FIG. 7] shows a block structure of AM-LCD.
[0251] [FIG. 8] shows a structure of a CMOS circuit or a pixel
matrix circuit.
[0252] [FIG. 9] shows a structure of a pixel matrix circuit
(specially a storage capacitor).
[0253] [FIG. 10] shows a structure of a CMOS circuit or a pixel
matrix circuit.
[0254] [FIG. 11] shows a structure of a CMOS circuit or a pixel
matrix circuit.
[0255] [FIG. 12] shows a process of manufacturing a CMOS
circuit.
[0256] [FIG. 13] shows a structure of a CMOS circuit.
[0257] [FIG. 14] shows a process of manufacturing a CMOS
circuit.
[0258] [FIG. 15] shows an example of an electronic device.
* * * * *