U.S. patent application number 09/862365 was filed with the patent office on 2002-11-28 for charge pump or other charge storage capacitor including pzt layer for combined use as encapsulation layer and dielectric layer of ferroelectric capacitor and a method for manufacturing the same.
Invention is credited to Evans, Thomas, Fox, Glen.
Application Number | 20020175361 09/862365 |
Document ID | / |
Family ID | 25338321 |
Filed Date | 2002-11-28 |
United States Patent
Application |
20020175361 |
Kind Code |
A1 |
Fox, Glen ; et al. |
November 28, 2002 |
CHARGE PUMP OR OTHER CHARGE STORAGE CAPACITOR INCLUDING PZT LAYER
FOR COMBINED USE AS ENCAPSULATION LAYER AND DIELECTRIC LAYER OF
FERROELECTRIC CAPACITOR AND A METHOD FOR MANUFACTURING THE SAME
Abstract
A charge storage capacitor includes a bottom electrode, a
dielectric layer formed on the bottom electrode, and a local
interconnect electrode formed on the dielectric layer, wherein the
dielectric layer is an encapsulation layer, and a ferroelectric
memory cell includes the charge storage capacitor.
Inventors: |
Fox, Glen; (Colorado
Springs, CO) ; Evans, Thomas; (Colorado Springs,
CO) |
Correspondence
Address: |
HOGAN & HARTSON LLP
ONE TABOR CENTER, SUITE 1500
1200 SEVENTEENTH ST
DENVER
CO
80202
US
|
Family ID: |
25338321 |
Appl. No.: |
09/862365 |
Filed: |
May 22, 2001 |
Current U.S.
Class: |
257/303 ;
257/E21.009; 438/244 |
Current CPC
Class: |
H01L 28/55 20130101 |
Class at
Publication: |
257/303 ;
438/244 |
International
Class: |
H01L 027/108; H01L
031/119 |
Claims
1. A charge storage capacitor comprising: a bottom electrode; a
dielectric layer formed on the bottom electrode; and a local
interconnect electrode formed on the dielectric layer.
2. The charge storage capacitor according to claim 1, wherein the
dielectric layer is an encapsulation layer.
3. The charge storage capacitor according to claim 2, wherein the
encapsulation layer includes PZT.
4. The charge storage capacitor according to claim 2, wherein the
encapsulation layer includes Pb-based perovskite dielectrics,
aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
5. The charge storage capacitor according to claim 1, wherein the
charge storage capacitor comprises part of a ferroelectric memory
cell.
6. The charge storage capacitor according to claim 1, wherein the
charge storage capacitor comprises part of an integrated
circuit.
7. The charge storage capacitor according to claim 6, wherein the
integrated circuit further comprises a ferroelectric memory
cell.
8. An integrated circuit comprising a capacitor, comprising: a
bottom electrode; a first dielectric layer formed on the bottom
electrode; a top electrode formed on the first dielectric layer; a
second dielectric layer formed on the top electrode, wherein the
second dielectric layer completely covers the top electrode; and a
local interconnect electrode formed on the second dielectric
layer.
9. The integrated circuit according to claim 8, wherein the second
dielectric layer is an encapsulation layer.
10. The integrated circuit according to claim 9, wherein the
encapsulation layer includes PZT.
11. The integrated circuit according to claim 9, wherein the
encapsulation layer includes Pb-based perovskite dielectrics,
aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
12. The integrated circuit according to claim 8, wherein the bottom
electrode is electrically isolated.
13. The integrated circuit according to claim 8, wherein the top
electrode, the second dielectric layer, and the local interconnect
electrode form the capacitor.
14. The integrated circuit according to claim 8, wherein the
capacitor is a charge storage capacitor.
15. The integrated circuit according to claim 8, wherein the
capacitor comprises part of a ferroelectric memory cell.
16. The integrated circuit according to claim 8, wherein the top
electrode is electrically isolated.
17. The integrated circuit according to claim 8, wherein the bottom
electrode, the first dielectric layer, the second dielectric layer,
and the local interconnect electrode form the capacitor.
18. The integrated circuit according to claim 8, wherein the
integrated circuit further comprises a ferroelectric memory
cell.
19. A charge storage capacitor comprising: a bottom electrode; a
first dielectric layer formed on the bottom electrode; a second
dielectric layer formed on the first dielectric layer; and a local
interconnect electrode formed on the second dielectric layer.
20. The charge storage capacitor according to claim 19, wherein the
second dielectric layer is an encapsulation layer.
21. The charge storage capacitor according to claim 20, wherein the
encapsulation layer includes PZT.
22. The charge storage capacitor according to claim 20, wherein the
encapsulation layer includes Pb-based perovskite dielectrics,
aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
23. The charge storage capacitor according to claim 19, wherein the
first dielectric layer and the second dielectric layer form a
dielectric layer of the charge storage capacitor, and the local
interconnect electrode forms an electrode of the capacitor.
24. The charge storage capacitor according to claim 19, wherein the
charge storage capacitor comprises part of a ferroelectric memory
cell.
25. The charge storage capacitor according to claim 19, wherein the
charge storage capacitor comprises part of an integrated
circuit.
26. The charge storage capacitor according to claim 25, wherein the
integrated circuit further comprises a ferroelectric memory
cell.
27. A method for forming a capacitor, comprising the steps of:
forming a bottom electrode; forming an encapsulation layer on the
bottom electrode; and forming a local interconnect electrode on the
encapsulation layer.
28. The method for forming a capacitor according to claim 27,
wherein the encapsulation layer includes PZT.
29. The method for forming a capacitor according to claim 27,
wherein the encapsulation layer is formed at a temperature as high
as 700.degree. C.
30. The method for forming a capacitor according to claim 28,
wherein the encapsulation layer is formed with plasma damage to
improve linear dielectric performance.
31. The method for forming a capacitor according to claim 27,
wherein the capacitor is a charge storage capacitor.
32. The method for forming a capacitor according to claim 27,
wherein the encapsulation layer includes Pb-based perovskite
dielectrics, aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
33. The method for forming a capacitor according to claim 27,
wherein a thickness of the encapsulation layer is in a range of
between 30-200 nm.
34. The method for forming a capacitor according to claim 27,
wherein a thickness of the bottom electrode is about 100 nm.
35. A method for forming an integrated circuit, comprising a charge
storage capacitor and a ferroelectric memory cell including a data
storage capacitor, comprising the steps of: forming a bottom
electrode of the charge storage capacitor and a bottom electrode of
the data storage capacitor on an integrated circuit substrate;
forming a ferroelectric layer on the bottom electrode of the data
storage capacitor; forming a top electrode layer on the
ferroelectric layer; forming a first encapsulation layer on the
bottom electrode of the charge storage capacitor and a second
encapsulation layer on the bottom electrode of the data storage
capacitor including the ferroelectric layer and the top electrode,
wherein the first encapsulation layer and the second encapsulation
are formed simultaneously; and forming a first interlayer
dielectric layer on the first encapsulation layer and a second
interlayer dielectric layer on the second encapsulation layer,
wherein the first encapsulation layer is a dielectric layer of the
charge storage capacitor.
36. The method for forming an integrated circuit according to claim
35, wherein the first and second encapsulation layers comprise
PZT.
37. The method for forming an integrated circuit according to claim
36, wherein the first and second encapsulation layers are formed at
a temperature as high as 700.degree. C.
38. The method for forming an integrated circuit according to claim
36, wherein the first and second encapsulation layers are formed
with plasma damage to improve linear dielectric performance.
39. The method for forming an integrated circuit according to claim
35, wherein the first and second encapsulation layers include
Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide,
BaTiO.sub.3, or other dielectrics.
40. The method for forming an integrated circuit according to claim
35, further comprising the steps of: etching the first interlayer
dielectric layer to form a first opening to expose the first
encapsulation layer; etching the second interlayer dielectric layer
and the second encapsulation layer to form a second opening to
expose the top electrode of the data storage capacitor; and forming
a first local interconnect electrode in the first opening and a
second local interconnect electrode in the second opening.
41. The method for forming an integrated circuit according to claim
40, wherein the first local interconnect electrode comprises part
of the charge storage capacitor.
42. A method for forming an integrated circuit comprising a
capacitor, comprising the steps of: forming a bottom electrode;
forming a ferroelectric layer on the bottom electrode; forming a
top electrode on the ferroelectric layer; forming an encapsulation
layer on the top electrode, wherein the encapsulation layer
completely covers the top electrode; and forming a local
interconnect electrode on the encapsulation layer, wherein the
ferroelectric layer includes PZT.
43. The method for forming an integrated circuit according to claim
42, wherein the encapsulation layer includes Pb-based perovskite
dielectrics, aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
44. The method for forming an integrated circuit according to claim
42, wherein the encapsulation layer includes PZT.
45. The method for forming an integrated circuit according to claim
44, wherein the encapsulation layer is formed at a temperature as
high as 700.degree. C.
46. The method for forming an integrated circuit according to claim
44, wherein the encapsulation layer is formed with plasma damage to
improve linear dielectric performance.
47. The method for forming an integrated circuit according to claim
44, wherein the encapsulation layer is formed with a lower Pb
(lead) concentration than the ferroelectric layer.
48. The method for forming an integrated circuit according to claim
44, wherein the encapsulation layer and the ferroelectric layer are
formed with different compositions.
49. The method for forming an integrated circuit according to claim
48, wherein the different compositions include different
concentrations of Pb, Zr, and/or Ti.
50. The method for forming an integrated circuit according to claim
44, wherein the encapsulation layer and the ferroelectric layer are
formed with different dopant concentrations.
51. The method for forming an integrated circuit according to claim
42, wherein the bottom electrode is electrically isolated.
52. The method for forming an integrated circuit according to claim
42, wherein the top electrode is electrically isolated.
53. The method for forming an integrated circuit according to claim
42, wherein the bottom electrode forms a first electrode of the
capacitor, the ferroelectric layer and the encapsulation layer form
a dielectric layer of the capacitor, and the local interconnect
electrode forms a second electrode of the capacitor.
54. The method for forming an integrated circuit according to claim
53, wherein the capacitor is a charge storage capacitor.
55. The method for forming an integrated circuit according to claim
42, wherein the capacitor is a charge storage capacitor.
56. The method for forming an integrated circuit according to claim
43, wherein the capacitor comprises part of a ferroelectric memory
cell.
57. The method for forming an integrated circuit according to claim
43, wherein the integrated circuit further comprises a
ferroelectric memory cell.
58. The method for forming an integrated circuit according to claim
42, wherein a thickness of the ferroelectric layer is in a range
between 150-200 nm.
59. A method for forming an integrated circuit, comprising a charge
storage capacitor and a ferroelectric memory cell including a data
storage capacitor, comprising the steps of: forming a bottom
electrode of the charge storage capacitor and a bottom electrode of
the data storage capacitor on an integrated circuit substrate;
forming a first ferroelectric layer on the bottom electrode of the
charge storage capacitor and a second ferroelectric layer on the
bottom electrode of the data storage capacitor; forming a first top
electrode on the first ferroelectric layer and a second top
electrode on the second ferroelectric layer; forming a first
encapsulation layer on the bottom electrode of the charge storage
capacitor, including the first ferroelectric layer and the first
top layer; forming a second encapsulation layer on the bottom
electrode of the data storage capacitor, including the second
ferroelectric layer and the second top layer, wherein the first
encapsulation layer and the second encapsulation are formed
simultaneously; forming a first interlayer dielectric layer on the
first encapsulation layer and a second interlayer dielectric layer
on the second encapsulation layer, etching the first interlayer
dielectric layer to form a first opening to expose the first
encapsulation layer; etching the second interlayer dielectric layer
and the second encapsulation layer to form a second opening to
expose the top electrode of the data storage capacitor; and forming
a first local interconnect electrode in the first opening and a
second local interconnect electrode in the second opening, wherein
the first local interconnect electrode comprises part of the charge
storage capacitor.
60. The method for forming an integrated circuit according to claim
59, wherein the first and second encapsulation layers comprise
PZT.
61. The method for forming an integrated circuit according to claim
60, wherein the first and second encapsulation layers are formed at
a temperature as high as 700.degree. C.
62. The method for forming an integrated circuit according to claim
60, wherein the first and second encapsulation layers are formed
with plasma damage to improve linear dielectric performance.
63. The method for forming an integrated circuit according to claim
59, wherein the first and second encapsulation layers include
Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide,
BaTiO.sub.3, or other dielectrics.
64. The method for forming an integrated circuit according to claim
59, wherein the bottom electrode is electrically isolated.
65. The method for forming an integrated circuit according to claim
59, wherein the top electrode is electrically isolated.
66. The method for forming an integrated circuit according to claim
59, wherein the bottom electrode forms a first electrode of the
charge storage capacitor, the first ferroelectric layer and the
first encapsulation layer form a dielectric layer of the charge
storage capacitor, and the first local interconnect electrode forms
a second electrode of the charge storage capacitor.
67. The method for forming an integrated circuit according to claim
59, wherein the first top electrode forms a first electrode of the
charge storage capacitor, the first encapsulation layer forms a
dielectric layer of the charge storage capacitor, and the first
local interconnect electrode forms a second electrode of the charge
storage capacitor.
68. A method for forming a capacitor, comprising the steps of:
forming a bottom electrode; forming a ferroelectric layer on the
bottom electrode; forming an encapsulation layer on the
ferroelectric layer; and forming a local interconnect electrode on
the encapsulation layer.
69. The method for forming a capacitor according to claim 68, w
herein the encapsulation layer includes PZT.
70. The method for forming a capacitor according to claim 69,
wherein the encapsulation layer is formed at a temperature as high
as 700.degree. C.
71. The method for forming a capacitor according to claim 69,
wherein the encapsulation layer is formed with plasma damage to
improve linear dielectric performance.
72. The method for forming a capacitor according to claim 70,
wherein the ferroelectric layer and the encapsulation layer form a
dielectric layer of the capacitor.
73. The method for forming a capacitor according to claim 70,
wherein the encapsulation layer includes Pb-based perovskite
dielectrics, aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics.
74. The method for forming a capacitor according to claim 68,
wherein the capacitor is a charge storage capacitor.
75. The method for forming a capacitor according to claim 68,
wherein the capacitor comprises part of a ferroelectric memory
cell.
76. The method for forming a capacitor according to claim 68,
wherein the capacitor comprises part of an integrated circuit.
77. A method for forming an integrated circuit, comprising a charge
storage capacitor and a ferroelectric memory cell including a data
storage capacitor, comprising the steps of: forming a bottom
electrode of the charge storage capacitor and a bottom electrode of
the data storage capacitor on an integrated circuit substrate;
forming a first ferroelectric layer on the bottom electrode of the
charge storage capacitor and a second ferroelectric layer on the
bottom electrode of the data storage capacitor; forming a top
electrode layer on the first and second ferroelectric layers;
etching the top electrode layer to remove from the first
ferroelectric layer and to form a top electrode of the data storage
capacitor on the second ferroelectric layer; forming a first
encapsulation layer on the bottom electrode of the charge storage
capacitor including the first encapsulation layer and a second
encapsulation layer on the bottom electrode of the data storage
capacitor including the second ferroelectric layer and the top
electrode; and forming a first interlayer dielectric layer on the
first encapsulation layer and a second interlayer dielectric layer
on the second encapsulation layer, wherein the first encapsulation
layer and the second encapsulation are formed simultaneously.
78. The method for forming an integrated circuit according to claim
77, wherein the first and second encapsulation layers comprise
PZT.
79. The method for forming an integrated circuit according to claim
77, wherein the first and second encapsulation layers include
Pb-based perovskite dielectrics, aluminum oxide, tantalum oxide,
BaTiO.sub.3, or other dielectrics.
80. The method for forming an integrated circuit according to claim
77, further comprising the steps of: etching the first interlayer
dielectric layer to form a first opening to expose the first
encapsulation layer; etching the second interlayer dielectric layer
and the second encapsulation layer to form a second opening to
expose the top electrode of the data storage capacitor; and forming
a first local interconnect electrode in the first opening and a
second local interconnect electrode in the second opening.
81. The method for forming an integrated circuit according to claim
80, wherein the first local interconnect electrode comprises part
of the charge storage capacitor.
82. The method for forming an integrated circuit according to claim
77, wherein the first ferroelectric layer and the first
encapsulation layer form a dielectric layer of the charge storage
capacitor.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a charge storage capacitor
and more particularly, to a charge storage capacitor including an
encapsulation layer that can also function as a dielectric layer of
the charge storage capacitor.
[0003] 2. Discussion of the Related Art
[0004] Integrated circuit ferroelectric memory devices include an
integrated circuit substrate which includes a cell region and a
periphery region. A plurality of ferroelectric memory cells are
formed in the cell region, including a plurality of ferroelectric
capacitors. The ferroelectric capacitor in the ferroelectric memory
cell includes a dielectric material that has a high dielectric
constant and that can be polarized by an electric field, thus
storing a memory data state. A polarization of the dielectric
material remains until reversed by an opposite electrical field.
This makes the dielectric memory cell non-volatile.
[0005] Conventionally, capacitors with a single ferroelectric
layer, such as a PZT-F layer (ferroelectric layer formed of PZT
(lead zirconate titanate)), are used for making both switchable
ferroelectric capacitors (data storage capacitors) and charge pump
capacitors or other charge storage capacitors. However, it is very
difficult to optimize the ferroelectric properties of a
ferroelectric layer, such as a PZT-F layer, for high permittivity
capacitor applications such as charge pumps or other charge storage
capacitors. Further, conventionally, an encapsulation layer, such
as a PZT-E layer (encapsulation layer formed of PZT (lead zirconate
titanate)) is utilized only for encapsulating and protecting the
underlying ferroelectric capacitor including the PZT-F layer.
SUMMARY OF THE INVENTION
[0006] Accordingly, the present invention is directed to a charge
storage capacitor that substantially obviates one or more of the
problems due to limitations and disadvantages of the related
art.
[0007] An object of the present invention is to provide an improved
charge storage capacitor.
[0008] Another object of the present invention is to provide a
capacitor including a dielectric layer that is easy to optimize for
both encapsulation and high permittivity dielectric properties.
[0009] Another object of the present invention is to provide a
capacitor having a high charge storage capability that has low
leakage current and relatively linear capacitance dependence on
voltage.
[0010] Another object of the present invention is to provide an
integrated circuit, including an improved charge storage and a
ferroelectric memory cell, having a simple manufacture process.
[0011] Additional features and advantages of the invention will be
set forth in the description, which follows, and in part will be
apparent from the description, or may be learned by practice of the
invention. The objectives and other advantages of the invention
will be realized and attained by the structure particularly pointed
out in the written description and claims hereof as well as the
appended drawings.
[0012] To achieve these and other advantages and in accordance with
the purpose of the present invention, as embodied and broadly
described, a charge storage capacitor includes a bottom electrode,
a dielectric layer formed on the bottom electrode, and a local
interconnect electrode formed on the dielectric layer.
[0013] In another aspect of the present invention, an integrated
circuit including a capacitor includes a bottom, a first dielectric
layer formed on the bottom electrode, a top electrode formed on the
first dielectric layer, a second dielectric layer formed on the top
electrode, wherein the second dielectric layer completely covers
the top electrode, and a local interconnect electrode formed on the
second dielectric layer.
[0014] In another aspect of the present invention, a charge storage
capacitor includes a bottom electrode, a first dielectric layer
formed on the bottom electrode, a second dielectric layer formed on
the first dielectric layer, and a local interconnect electrode
formed on the second dielectric layer.
[0015] In another aspect of the present invention, a method for
forming a capacitor, includes the steps of forming a bottom
electrode, forming an encapsulation layer on the bottom electrode,
and forming a local interconnect electrode on the encapsulation
layer.
[0016] In another aspect of the present invention, a method for
forming an integrated circuit, comprising a charge storage
capacitor and a ferroelectric memory cell including a data storage
capacitor, includes the steps of forming a bottom electrode of the
charge storage capacitor and a bottom electrode of the data storage
capacitor on an integrated circuit, forming a ferroelectric layer
on the bottom electrode of the data storage capacitor, forming a
top electrode on the ferroelectric layer, forming a first
encapsulation layer on the bottom electrode of the charge storage
capacitor and a second encapsulation layer on the bottom electrode
of the data storage capacitor including the ferroelectric layer and
the top electrode, wherein the first encapsulation layer and the
second encapsulation are formed simultaneously, and forming a first
interlayer dielectric layer on the first encapsulation layer and a
second interlayer dielectric layer on the second encapsulation
layer, wherein the first encapsulation layer is a dielectric layer
of the charge storage capacitor.
[0017] In another aspect of the present invention, a method for
forming an integrated circuit comprising a capacitor, includes the
steps of forming a bottom electrode, forming a ferroelectric layer
on the bottom electrode, forming a top electrode on the
ferroelectric layer, forming an encapsulation layer on the top
electrode, wherein the encapsulation layer completely covers the
top electrode, and forming a local interconnect electrode on the
encapsulation layer, wherein the ferroelectric layer includes
PZT.
[0018] In another aspect of the present invention, a method for
forming an integrated circuit, comprising a charge storage
capacitor and a ferroelectric memory cell including a data storage
capacitor, includes the steps of forming a bottom electrode of the
charge storage capacitor and a bottom electrode of the data storage
capacitor on an integrated circuit substrate, forming a first
ferroelectric layer on the bottom electrode of the charge storage
capacitor and a second ferroelectric layer on the bottom electrode
of the data storage capacitor, forming a first top electrode on the
first ferroelectric layer and a second top electrode on the second
ferroelectric layer, forming a first encapsulation layer on the
bottom electrode of the charge storage capacitor, including the
first ferroelectric layer and the first top layer, forming a second
encapsulation layer on the bottom electrode of the data storage
capacitor, including the second ferroelectric layer and the second
top layer, wherein the first encapsulation layer and the second
encapsulation are formed simultaneously, forming a first interlayer
dielectric layer on the first encapsulation layer and a second
interlayer dielectric layer on the second encapsulation layer,
etching the first interlayer dielectric layer to form a first
opening to expose the first encapsulation layer, etching the second
interlayer dielectric layer and the second encapsulation layer to
form a second opening to expose the top electrode of the data
storage capacitor, and forming a first local interconnect electrode
in the first opening and a second local interconnect electrode in
the second opening, simultaneously, wherein the first local
interconnect electrode comprises part of the charge storage
capacitor.
[0019] In another aspect of the present invention, a method for
forming a capacitor, includes the steps of forming a bottom
electrode, forming a ferroelectric layer on the bottom electrode,
forming an encapsulation layer on the ferroelectric layer, and
forming a local interconnect electrode on the encapsulation
layer.
[0020] In another aspect of the present invention, a method for
forming an integrated circuit, comprising a charge storage
capacitor and a ferroelectric memory cell including a data storage
capacitor, includes the steps of forming a bottom electrode of the
charge storage capacitor and a bottom electrode of the data storage
capacitor on an integrated circuit substrate, forming a first
ferroelectric layer on the bottom electrode of the charge storage
capacitor and a second ferroelectric layer on the bottom electrode
of the data storage capacitor, forming a top electrode layer on the
first and second ferroelectric layers, etching the top electrode
layer to remove from the first ferroelectric layer and to form a to
electrode of the data storage capacitor on the second ferroelectric
layer, forming a first encapsulation layer on the bottom electrode
of the charge storage capacitor including the first encapsulation
layer and a second encapsulation layer on the bottom electrode of
the data storage capacitor including the second ferroelectric layer
and the top electrode, and forming a first interlayer dielectric
layer on the first encapsulation layer and a second interlayer
dielectric layer on the second encapsulation layer, wherein the
first encapsulation layer and the second encapsulation are formed
simultaneously.
[0021] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are intended to provide further explanation of
the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The accompanying drawings, which are included to provide
further understanding of the invention and are incorporated in and
constitute a part of this specification, illustrate embodiments of
the invention and together with the description serve to explain
the principles of the invention. In the drawings:
[0023] FIG. 1 is a cross sectional view of a ferroelectric memory
cell;
[0024] FIGS. 2A-2F are sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a first embodiment of the present invention;
[0025] FIGS. 3A-3F are sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a second embodiment of the present invention;
[0026] FIGS. 4A-4F are sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a third embodiment of the present invention; and
[0027] FIGS. 5A-5F are sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings.
[0029] FIG. 1 shows a cross sectional view of a typical
ferroelectric memory cell structure including a ferroelectric
capacitor, which stores a memory data state. The ferroelectric
capacitor includes a bottom electrode (BE) 111, a PZT-F layer 112,
and a top electrode (TE) 113. The ferroelectric memory cell further
includes an encapsulation PZT (PZT-E) layer 114 formed on the
ferroelectric capacitor to protect the underlying capacitor from
being damaged during etching of the bottom electrode 111. Once the
etching of the bottom electrode is finished, an interlevel
dielectric (ILD) layer 150 is deposited. Thereafter, the interlevel
dielectric layer 150 and the PZT-E layer 114 are etched to form an
opening so that a local interconnect electrode (LI) 115 can be
formed to be in contact with the top electrode 113 through the
opening.
[0030] FIGS. 2A-2E show sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a first embodiment of the present invention. The integrated
circuit includes the charge storage capacitor of the present
invention and a ferroelectric memory cell including a ferroelectric
capacitor (data storage capacitor). The charge storage capacitor of
the present invention and the data storage capacitor are formed
simultaneously on an integrated circuit substrate by using the same
process sequence.
[0031] FIG. 2A shows the integrated circuit including a section
210a, where the charge storage capacitor of the present invention
is to be formed, and a section 210b, where the ferroelectric
capacitor (data storage capacitor) is to be formed. The integrated
circuit shown in FIG. 2A includes a CMOS underlayer coated with
SiO.sub.2 or other interlayer dielectric layer 241, with an
adhesion layer (not shown) formed thereon, and a bottom electrode
layer 211 deposited thereon. The adhesion layer can be formed of Ti
or TiO.sub.x having a thickness of about 20 nm, for example. The
bottom electrode layer can be made of Pt (Platinum) having a
thickness of about 100 nm, for example. On the bottom electrode
layer 211, a PZT-F 212 is deposited to a thickness in a range of
between 150-200 nm. Then, a top electrode layer 213 is deposited to
a thickness of 150 nm, for example.
[0032] Thereafter, the top electrode layer 213 in 210b is patterned
by photolithography and reactive ion etching to form a top
electrode (TE) 213b of the data storage capacitor. The top
electrode layer 213 in 210a is completely removed by the reactive
ion etching (RIE), as shown in FIG. 2B.
[0033] Thereafter, the PZT-F layer 212 in 210b is patterned by
photolithography and reactive ion etching to form a PZT-F layer
212b. Simultaneously, the PZT-F 212 in 210a is completely removed
by reactive ion etching, thus leaving a clean bottom electrode
layer surface in 210a, as shown in FIG. 2C.
[0034] Then, an encapsulation layer formed of PZT (PZT-E layer) 214
is formed to a thickness in a range of between 30 to 200 nm, for
example. Thereafter, the PZT-E layer 214 is patterned by
photolithography and reactive ion etching to form a dielectric
layer 214a of the charge storage capacitor and an encapsulation
layer 214b of the data storage capacitor. Also, the bottom
electrode layer 211 is patterned by photolithography and reactive
ion etching to form a bottom electrode 211a of the charge storage
capacitor and a bottom electrode 211b of the data storage
capacitor, as shown in FIG. 2D.
[0035] Once the bottom electrodes 211a and 211b and the PZT-E
layers 214a and 214b are formed, an interlayer dielectric layer 250
is deposited. Thereafter, the interlayer dielectric layer 250 and
the PZT-E layer 214b formed on the data storage capacitor in 210b
are etched through to form an opening to provide access to the top
electrode 213b of the data storage capacitor. Simultaneously, the
interlayer dielectric layer 250 formed in 210a is etched, without
etching the PZT-E layer 214a, to form an opening therein, as shown
in FIG. 2E.
[0036] Thereafter, a local interconnect layer 215 is deposited and
patterned by photolithography and reactive ion etching to form a
local interconnect electrode 215b of the ferroelectric memory cell
in 210b and a local interconnect electrode 215a of the charge
storage capacitor in 210a, simultaneously, as shown in FIG. 2F. The
local interconnect electrode 215a is also a second electrode of the
charge storage capacitor. The local interconnect layer can be made
of conductive materials, such as TiN and Al, for example.
[0037] In this embodiment, the charge storage capacitor includes
the encapsulation PZT (PZT-E) layer 214a as a dielectric layer of
the capacitor. Further, in this embodiment, the bottom electrode
(BE) 211a is used as a first electrode and the local interconnect
layer (LI) 215a is used as a second electrode of the charge storage
capacitor.
[0038] The PZT-E layer 214 can be formed by electron beam
deposition, flash deposition, ion plating, Rf-magnetron sputtering,
ion beam sputtering, laser ablation, molecular beam epitaxy (MBE),
chemical vapor deposition (CVD), plasma CVD or MOCVD, or sol-gel
method. By depositing the PZT layer with properly adjusted Pb
concentration with high temperature deposition, up to 700.degree.
C., or by changing deposited Pb concentration, enhanced linear
dielectric response and reduced leakage current can be provided.
Further, as part of the manufacture process, it is also possible to
plasma damage the PZT layer during the etching of the bottom
electrode layer and the PZT-E layer, thereby improving the linear
dielectric performance of the PZT layer.
[0039] FIGS. 3A-3G show sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a second embodiment of the present invention. The charge storage
capacitor and a ferroelectric capacitor (data storage capacitor)
are formed simultaneously on an integrated circuit substrate by
using the same process sequence.
[0040] FIG. 3A shows the integrated circuit including a section
310a, where the charge storage capacitor is to be formed, and a
section 310b, where the data storage capacitor is to be formed. The
integrated circuit shown in FIG. 3A includes a CMOS underlayer
coated with SiO.sub.2 or other interlayer dielectric layer 341,
with an adhesion layer (not shown) formed thereon, and a bottom
electrode layer 311 deposited thereon. The adhesion layer can be
formed of Ti or TiO.sub.x having a thickness of about 20 nm, for
example. The bottom electrode layer can be made of Pt (Platinum)
having a thickness of about 100 nm, for example. On the bottom
electrode layer 311, a PZT-F 312 is deposited to a thickness in a
range of between 150-200 nm. Then, a top electrode layer 313 is
deposited to a thickness of 150 nm, for example.
[0041] Thereafter, the top electrode layer 313 is patterned by
photolithography and reactive ion etching to form a top electrode
(TE) 313a of the charge storage capacitor and a top electrode (TE)
313b of the data storage capacitor, as shown in FIG. 3B.
[0042] Thereafter, the PZT-F 312 layer in 310b is patterned by
photolithography and reactive ion etching to form a PZT-F layer
312b. Simultaneously, the PZT-F 312 in 310a is patterned by
photolithography and reactive ion etching to form a PZT-F layer
312a, as shown in FIG. 3C. An area of the PZT-F layer 312a must be
larger than an area of the charge storage capacitor.
[0043] Then, a PZT-E layer 314 is formed to a thickness in a range
of between 30 to 200 nm, for example. Thereafter, the PZT-E layer
314 is patterned by photolithography and reactive ion etching to
form a dielectric layer 314a of the charge storage capacitor and an
encapsulation layer 314b of the data storage capacitor. Also, the
bottom electrode layer 311 is patterned by photolithography and
reactive ion etching to form a bottom electrode 311a of the charge
storage capacitor and a bottom electrode 311b of the data storage
capacitor, as shown in FIG. 3D. An area of the PZT-E layer 314a and
the bottom electrode (BE) 311a of the charge storage capacitor must
be longer than an area of the shorter of the two electrodes
constituting the charge storage capacitor.
[0044] Once the bottom electrodes 311a and 311b and the PZT-E
layers 314a and 314b are formed, an interlayer dielectric layer 350
is deposited. Thereafter, the interlayer dielectric layer 350 and
the PZT-E layer 314b formed on the data storage capacitor in 310b
are etched through to form an opening to provide access to the top
electrode 313b of the data storage capacitor. Simultaneously, the
interlayer dielectric layer 350 formed in 310a is etched, without
etching the PZT-E layer 314a, to form an opening therein, as shown
in FIG. 3E.
[0045] Thereafter, a local interconnect layer 315 is deposited and
patterned by photolithography and reactive ion etching to formed a
local interconnect electrode (LI) 315b of the ferroelectric memory
cell in 310b and a local interconnect electrode 315a of the charge
storage capacitor in 310a, as shown in FIG. 3F. The local
interconnect electrode 315a of the charge storage capacitor is also
a second electrode of the charge storage capacitor. The local
interconnect layer can be made of conductive materials, such as TiN
and Al, for example.
[0046] In this embodiment, the charge storage capacitor includes
the top electrode 313a, the PZT-E layer 314a, and the local
interconnect electrode 315a formed on the bottom electrode 311a and
the PZT-F layer 312a. In this embodiment, the bottom electrode 311a
and the PZT-F layer 312a remain as part of the capacitor structure,
but they are electrically isolated from the rest of the charge
storage capacitor. There is an electrical connection to the top
electrode 313a, but there is no electrical connection to the bottom
electrode 311a, thus neither the bottom electrode 311a nor the
PZT-F layer 312a has any electrical function in the charge storage
capacitor.
[0047] FIGS. 4A-4G show sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a third embodiment of the present invention. The charge storage
capacitor and a ferroelectric capacitor (data storage capacitor)
are formed simultaneously on an integrated circuit substrate by
using the same process sequence.
[0048] FIG. 4A shows the integrated circuit including a section
410a, where the charge storage capacitor is to be formed, and a
section 410b, where the data storage capacitor is to be formed. The
integrated circuit shown in FIG. 4A includes a CMOS underlayer
coated with SiO.sub.2 or other interlayer dielectric layer 441,
with an adhesion layer (not shown) formed thereon, and a bottom
electrode layer 411 deposited thereon. The adhesion layer can be
formed of Ti or TiO.sub.x having a thickness of about 20 nm, for
example. The bottom electrode layer can be made of Pt (Platinum)
having a thickness of about 100 nm, for example. On the bottom
electrode layer 411, a PZT-F 412 is deposited to a thickness in a
range of between 150-200 nm. Then, a top electrode layer 413 is
deposited to a thickness of 150 nm, for example.
[0049] Thereafter, the top electrode layer 413 in 410b is patterned
by photolithography and reactive ion etching to form a top
electrode 413b of the data storage capacitor and the top electrode
layer 413 in 410a is removed by reactive ion etching, as shown in
FIG. 4B.
[0050] Thereafter, the PZT-F 412 in 410b is patterned by
photolithography and reactive ion etching to form PZT-F layers 412a
and 412b, as shown in FIG. 4C.
[0051] Then, a PZT-E layer 414 is formed to a thickness in a range
of between 30 to 200 nm, for example. Thereafter, the PZT-E layer
414 is patterned by photolithography and reactive ion etching to
form 414a and 414b. Also, the bottom electrode layer 411 is
patterned by photolithography and reactive ion etching to form a
bottom electrode 411a of the charge storage capacitor and a bottom
electrode 411b of the data storage capacitor, as shown in FIG.
4D.
[0052] Once the bottom electrodes 411a and 411b and the PZT-E
layers 414a and 414b are formed, an interlayer dielectric layer 450
is deposited. Thereafter, the interlayer dielectric layer 450 and
the PZT-E layer 414b formed on the data storage capacitor in 410b
are etched through to form an opening to provide access to the top
electrode 413b of the data storage capacitor. Simultaneously, the
interlayer dielectric layer 450 formed in 410a is etched, without
etching the PZT-E layer 414a, to form an opening therein, as shown
in FIG. 4F.
[0053] Thereafter, a local interconnect layer 415 is deposited and
patterned by photolithography and reactive ion etching to form a
local interconnect electrode 415b of the ferroelectric memory cell
in 410b and a local interconnect electrode 415a of the charge
storage capacitor in 410a, as shown in FIG. 4G. The local
interconnect electrode 415a is also a second electrode of the
charge storage capacitor. The local interconnect layer can be made
of conductive materials, such as TiN and Al, for example.
[0054] In this embodiment, the charge storage capacitor includes
both the PZT-F layer and the PZT-E layer as a dielectric layer of
the capacitor. Since the PZT-E layer can be easily optimized for
better charge storage characteristics, such as voltage linearity,
for example, than the PZT-F layer, the combined PZT-F and PZT-E
layers will improve the capacitor performance of the charge storage
capacitor in comparison with using the PZT-F layer alone.
[0055] In a method for forming the PZT-E layer and the PZT-F layer,
in addition to using different processes, different compositions,
which include changing the concentrations of Pb, Zr, and/or Ti, as
well as dopant concentrations, can be used. For example, the PZT-E
layer can be deposited with a lower Pb concentration than that of
the PZT-F layer, thereby providing the layer with reduced leakage
current without a dramatic decrease in permittivity. As part of the
processing, it is also possible to plasma damage the PZT-E layer
during the top electrode, bottom electrode, PZT-E, and PZT-F
etching processes, thereby improving the linear dielectric
performance of the PZT-E layer.
[0056] FIGS. 5A-5G show sequential cross sectional views of an
integrated circuit including a charge storage capacitor according
to a fourth embodiment of the present invention. The charge storage
capacitor and a ferroelectric capacitor (data storage capacitor)
are formed simultaneously on an integrated circuit substrate by
using the same process sequence.
[0057] FIG. 5A shows the integrated circuit including a section
510a, where the charge storage capacitor is to be formed, and a
section 510b, where the data storage capacitor is to be formed. The
integrated circuit shown in FIG. 5A includes a CMOS underlayer
coated with SiO.sub.2 or other interlayer dielectric layer 541,
with an adhesion layer (not shown) formed thereon, and a bottom
electrode layer 511 deposited thereon. The adhesion layer can be
formed of Ti or TiO.sub.x having a thickness of about 20 nm, for
example. The bottom electrode layer can be made of Pt (Platinum)
having a thickness of about 100 nm, for example. On the bottom
electrode layer 511, a PZT-F 512 is deposited to a thickness in a
range of between 150-200 nm. Then, a top electrode layer 513 is
deposited to a thickness of 150 nm, for example.
[0058] Thereafter, the top electrode layer 513 is patterned by
photolithography and reactive ion etching to form a top electrode
513b of the data storage capacitor and a top electrode 513a of the
charge storage capacitor, as shown in FIG. 5B.
[0059] Thereafter, the PZT-F 512 in 510b is patterned by
photolithography and reactive ion etching to form a PZT-F layer
513b. Simultaneously, the PZT-F 513 in 510a is patterned by
photolithography and reactive ion etching to form a PZT-F layer
513a, as shown in FIG. 5C.
[0060] Then, a PZT-E layer 514 is formed to a thickness in a range
of between 30 to 200 nm, for example. Thereafter, the PZT-E layer
514 is patterned by photolithography and reactive ion etching to
form an encapsulation layer 514b of the data storage capacitor and
a dielectric layer 514a of the charge storage capacitor. Also, the
bottom electrode layer 511 is patterned by photolithography and
reactive ion etching to form a bottom electrode 511a of the charge
storage capacitor and a bottom electrode 511b of the data storage
capacitor, as shown in FIG. 5D.
[0061] Once the bottom electrodes 511a and 511b and the PZT-E
layers 514a and 514b are formed, an interlayer dielectric layer 550
is deposited. Thereafter, the interlayer dielectric layer 550 and
the PZT-E layer 514b formed on the data storage capacitor in 510b
are etched through to form an opening to provide access to the top
electrode 513b of the data storage capacitor. Simultaneously, the
interlayer dielectric layer 550 formed on the charge storage
capacitor in 510a is etched, without etching the PZT-E layer 514a,
to form an opening therein, as shown in FIG. 5F.
[0062] Thereafter, a local interconnect layer 515 is deposited and
patterned by photolithography and reactive ion etching to formed a
local interconnect electrode 515b of the ferroelectric memory cell
in 510b and a local interconnect electrode 515a of the charge
storage capacitor in 510a, as shown in FIG. 5G. The local
interconnect electrode 515a is a second electrode of the charge
storage capacitor. The local interconnect layer can be made of
conductive materials, such as TiN and Al, for example.
[0063] The charge storage capacitor in this embodiment has a
similar structure to the structure of the second embodiment of the
present invention, except for the bottom electrode 511a being a
first electrode of the charge storage capacitor in this embodiment.
The charge storage capacitor in this embodiment includes both the
PZT-F layer 512a and the PZT-E layer 514a, with the bottom
electrode 511a being the first electrode and the local interconnect
electrode 515a being the second electrode of the charge storage
capacitor. In this embodiment, there is no electrical connection to
the top electrode 513a. The top electrode 513a is effectively a
floating electrode. Effectively, there are two capacitors connected
in series. The entire stack, including the bottom electrode 511a,
the PZT-F layer 512a, the top electrode 513a, the PZT-E layer 514a,
and the local interconnect electrode 515a, is electrically active.
The charge storage capacitor of this embodiment provides improved
linearity and higher breakdown voltage in comparison with a
capacitor formed with only a PZT-F layer.
[0064] In the present invention, the PZT-E layer can be replaced
with other materials, such as other Pb-based perovskite
dielectrics, aluminum oxide, tantalum oxide, BaTiO.sub.3, or other
dielectrics, for example.
[0065] The charge storage capacitor of the present invention can be
used as part of the ferroelectric memory cell or as part of the
circuitry in the periphery outside the ferroelectric memory
cell.
[0066] By using the structures and the methods described above, a
memory cell with an encapsulation layer and a charge storage
capacitor using the encapsulation layer as a dielectric can be
formed simultaneously, thus providing a simplified manufacturing
process. Further, by using the structures and the methods described
above, charge pumps or other charge storage capacitors having a
high permittivity dielectric can be formed.
[0067] It will be apparent to those skilled in the art that various
modifications and variations can be made in the charge storage
capacitor of the present invention without departing from the
spirit or scope of the invention. Thus, it is at the present
invention covers the modifications and variations of on if they
come within the scope of any claims and their equivalents.
* * * * *