U.S. patent application number 09/895554 was filed with the patent office on 2002-10-24 for flip chip interconnected structure and a fabrication method thereof.
Invention is credited to Lee, Shih-Chang.
Application Number | 20020155637 09/895554 |
Document ID | / |
Family ID | 21678019 |
Filed Date | 2002-10-24 |
United States Patent
Application |
20020155637 |
Kind Code |
A1 |
Lee, Shih-Chang |
October 24, 2002 |
Flip chip interconnected structure and a fabrication method
thereof
Abstract
A flip chip interconnected structure comprises a chip having an
active surface in which a plurality of bonding pads are formed on
the active surface of the chip. A substrate has a surface and a
chip locating region. The chip locating region is on the surface of
the substrate and a plurality of nodes are formed on the chip
locating region. A plurality of solder balls are respectively
connected to the bonding pads and the nodes. The solder balls have
various sizes. The chip is bonded to the chip locating region of
the substrate by the solder balls.
Inventors: |
Lee, Shih-Chang; (Kaohsiung,
TW) |
Correspondence
Address: |
J.C. Patents, Inc.
4 Venture, Suite 250
Irvine
CA
92618
US
|
Family ID: |
21678019 |
Appl. No.: |
09/895554 |
Filed: |
June 28, 2001 |
Current U.S.
Class: |
438/108 ;
257/738; 257/778; 257/E21.511; 257/E23.021; 438/613 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 24/81 20130101; H05K 3/284 20130101; H05K 2201/094 20130101;
H05K 3/3436 20130101; H01L 2224/13111 20130101; H01L 2924/01033
20130101; H01L 2224/05573 20130101; H01L 2224/05571 20130101; H01L
2224/16 20130101; H01L 2224/13 20130101; H01L 2224/1703 20130101;
H01L 2224/73204 20130101; H01L 2924/01082 20130101; H01L 2924/01322
20130101; H05K 2201/10992 20130101; H05K 2203/0465 20130101; H05K
2201/10674 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2224/81801 20130101; H01L 24/10 20130101; H01L 24/13
20130101; H01L 2924/00014 20130101; H01L 2224/13099 20130101; H01L
2924/014 20130101; H01L 2924/3511 20130101; Y02P 70/613 20151101;
Y02P 70/50 20151101; H01L 2224/17051 20130101; H01L 2924/0105
20130101; H05K 2201/10977 20130101; H01L 2924/14 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00 20130101; H01L 2224/13 20130101; H01L
2924/00 20130101; H01L 2924/181 20130101; H01L 2924/00 20130101;
H01L 2924/00014 20130101; H01L 2224/05599 20130101 |
Class at
Publication: |
438/108 ;
438/613; 257/778; 257/738 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50; H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 20, 2001 |
TW |
90109499 |
Claims
What is claimed is:
1. A flip chip interconnected structure, comprising: a substrate
having a first surface, a chip locating region and a plurality of
nodes, wherein the chip locating region is on the first surface of
the substrate and the nodes are formed on the chip locating region;
a chip having an active surface on which a plurality of bonding
pads are formed, the active surface of the chip corresponding to
the first surface of the substrate; and a plurality of solder
balls, wherein each solder ball respectively connects to one of the
bonding pads and one of the nodes, and sizes of the solder balls
are varied to allow the chip to bond to the chip locating region of
the substrate.
2. The structure of claim 1, wherein the structure further
comprises an encapsulating material filled in between the chip and
the substrate, and encapsulating the solder balls.
3. The structure of claim 1, wherein the solder balls are arranged
in a matrix, and sizes of the solder balls located at a center
region of the chip locating region are smaller than sizes of the
solder balls located at a peripheral region of the chip locating
region.
4. The structure of claim 1, wherein each solder ball is made of a
solder paste and a bump, wherein the solder paste covers the bump,
and the bump is made of a tin/lead alloy containing a high
percentage of lead.
5. The structure of claim 4, wherein the bump is made of the
tin/lead alloy with a ratio of 5/95, and the solder paste is made
of a tin/lead alloy with a ratio of 63/37.
6. The structure of claim 4, wherein a size of the solder paste
located at a center region of the chip locating region is smaller
than a size of the solder paste located at a peripheral region of
the chip locating region.
7. A flip chip interconnected structure, comprising: a substrate
having a first surface, a chip locating region and a plurality of
nodes, wherein the chip locating region is on the first surface of
the substrate and the nodes are formed on the chip locating region,
and the chip locating region further comprises a solder mask layer
having a plurality of solder mask openings, and the nodes are
exposed by the solder mask openings, wherein sizes of the solder
mask openings are varied; a chip having an active surface and a
plurality of bonding pads formed on the active surface, wherein the
active surface of the chip corresponds to the first surface of the
substrate; and a plurality of solder balls, wherein each solder
ball is respectively connected to one of the bonding pads and one
of the nodes, wherein sizes of the solder balls are varied to allow
the chip to bond to the chip locating region of the substrate.
8. The structure of claim 7, wherein the flip chip interconnected
structure further comprises an encapsulating material filled in
between the chip and the substrate, and encapsulating the solder
balls.
9. The structure of claim 7, wherein sizes of the solder mask
openings located at a center region of the chip locating region are
larger than sizes of the solder mask openings located at a
peripheral region of the chip locating region.
10. A method of fabricating a flip chip interconnected structure,
the steps of the method comprising: providing a chip having an
active surface, wherein a plurality of bonding pads are formed on
the active surface, and a plurality of bumps are formed on the
bonding pads; providing a substrate having a first surface, wherein
a chip locating region is on the first surface, and a plurality of
nodes are formed on the chip locating region; applying a solder
paste to cover the nodes of the chip locating region, wherein the
solder paste forms a plurality of solder structures with various
sizes; and performing a bonding process, wherein the active surface
of the chip is bonded to the surface of the substrate by bonding
the bumps to the solder structures, and a heating process is
carried out to combine the bumps and the solder structures to form
a plurality of solder balls, wherein each solder ball is bonded
respectively to one of the bonding pads and one of the nodes, and
the chip is bonded to the chip locating region of the substrate
through the solder balls.
11. The method of claim 10, wherein the bonding process further
comprises an encapsulating process, wherein an encapsulating
material is filled in between the chip and the substrate, and
encapsulating the solder balls.
12. The method of claim 10, wherein the step of applying the solder
paste further comprises: providing a stencil printing board having
a plurality of openings, wherein the stencil printing board is
located on the substrate and the nodes of the chip locating region
are exposed by the openings; filling the openings with the solder
paste by a screen printing method; forming solder structures with
various sizes according to different sizes of the openings and
positions of the solder structures corresponding to positions of
the nodes.
13. The method of claim 12, wherein the openings are arranged in a
matrix, and sizes of the openings located at a peripheral region of
the stencil printing board are larger than sizes of the openings
near a center region of the stencil printing board, thereby the
amount of the solder paste filled in the opening at the peripheral
region is more than the amount of the solder paste filled in the
openings at the center region.
14. The method of claim 10, wherein the bonding process further
comprises a reflow method to combine the bumps and the solder
structures.
15. The method of claim 10, wherein the solder balls are arranged
in a matrix, and sizes of the solder balls located at a center
region of the chip locating region are smaller than sizes of the
solder balls located at a peripheral region of the chip locating
region.
16. The method of claim 10, wherein each solder ball is made of a
tin/lead alloy containing a high percentage of lead.
17. A method of fabricating a flip chip interconnected structure,
the steps of the method comprising: providing a chip having an
active surface, wherein a plurality of bonding pads are formed on
the active surface, and a plurality of bumps are formed on the
bonding pads; providing a substrate having a first surface, wherein
a chip locating region is on the first surface, and a solder mask
layer and a plurality of nodes are formed on the chip locating
region, wherein a plurality of solder mask openings having various
sizes are formed on the solder mask layer, and the nodes are
exposed by the solder mask openings; applying a solder paste to
cover the node of the chip locating region; and performing a
bonding process, wherein the active surface of the chip is bonded
to the surface of the substrate by bonding the bumps to the solder
paste, and a heating process is carried out to combine each bump
and each solder paste to form a solder ball, wherein a plurality of
solder balls are formed and are bonded respectively to one of the
bonding pads and one of the nodes, and the chip is bonded to the
chip locating region of the substrate through the solder balls.
18. The method of claim 17, wherein the bonding process further
comprises an encapsulating process, wherein an encapsulating
material is filled in between the chip and the substrate, and
encapsulating the solder balls.
19. The method of claim 17, wherein sizes of the solder mask
openings located at a center region of the chip locating region are
larger than sizes of the solder mask openings located at a
peripheral region of the chip locating region.
20. The method of claim 17, wherein the bonding process further
comprises a reflow method to combine the bumps and the solder
structures.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 90109499, filed on Apr. 20, 2001.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates generally to a flip chip
interconnected structure and a fabrication method thereof. More
particularly, the present invention relates to an improved flip
chip interconnected structure having good electrical connection and
a fabrication method thereof.
[0004] 2. Description of the related Art
[0005] With the increasing need for high-density devices for use in
lightweight, portable electronics, there has been a gradual shift
in sizes of integrated circuits and their package configurations.
This gradual shift has resulted in developing various techniques
for different package types.
[0006] A flip chip interconnected technology utilizes solder bumps
on bonding pads of a chip to electrically connect to a substrate.
Comparing the flip chip interconnected method to a wire bonding
method and a tape automatic bonding method, the circular path of
the flip chip interconnected package is shorter and the electrical
properties are better. The bumps are arranged in a matrix shape;
thus, the amount of pin outs of the chip is significantly
increased. Since the flip chip technique is faster, denser,
thinner, lighter and provides a low cost package, one can expect
the flip chip technique to replace wire bonding.
[0007] FIGS. 1 and 2 illustrate schematic views of a conventional
flip chip package. Referring to FIG. 1, a chip 110 has an active
surface 112, and a plurality of bonding pads 114 are arranged on
the active surface 112. A plurality of bumps 116 are formed on the
bonding pads 114 of the chip 110. A substrate 120 has a surface
122, and a plurality of nodes 124 are formed on the surface 122. A
position of each node 124 corresponds to a position of each bump
116. A stencil printing process is carried out to apply solder
paste onto the substrate 120. A plurality of solder structures 130
are formed on the nodes 124 of the substrate 120. Referring to
FIGS. 1 and 2, a bonding process is performed to bond the chip 110
to the substrate 120. The bumps 116 of the chip 110 are bonded to
the solder structures 130 of the substrate 120 in a reflow oven. A
reflow method allows the bumps 116 to combine with the solder
structures 130 to form a plurality of solder balls 140. The chip
110 is electrically connected to the substrate 120 by the solder
balls 140.
[0008] Referring to FIG. 2, a filling process is carried out to
fill a gap between the chip 110 and the substrate 120 with a
molding compound 150, and the molding compound 150 encapsulates the
solder balls 140.
[0009] However, in the reflow process, the substrate 120 will bend
due to the heating in the reflow process. The distance between the
chip 110 and the substrate 120 at a center region is closer due to
the bending effect, and the distance between the chip 110 and the
substrate 120 at the end regions is greater. Stress caused by the
bending effect can affect the bonding between the chip 110 and the
substrate 120. The solder balls 140 will easily detach from the
nodes 124, and the stress due to the bending can also affect the
reliability of the device. Thus the electrical connection and the
reliability of the product are affected.
[0010] A conventional method utilizes a clamp (not shown) to hold
the chip 110 and pre-heat the chip 110 for a while during a bonding
process. Once the heat is transferred to the bumps 116, the bumps
116 will combine with the solder structures 130 to form the solder
balls 140. Thus the chip 110 is electrically connected to the
substrate 120. Although this method can prevent the substrate from
bending, the pre-heating process on the chip 110 can damage the
chip 110 because the chip is pre-heated for about 20 to 30 seconds
at a temperature of about 200.degree.. The conventional method
complicates the fabrication process and the quality of the product
is not reliable.
SUMMARY OF THE INVENTION
[0011] To achieve the foregoing and other objects and in accordance
with the purpose of the present invention, the present invention
provides a flip chip interconnected structure comprising a
substrate having a surface, a chip locating region and a plurality
of nodes. The chip locating region is on the surface of the
substrate and the nodes are formed on the chip locating region. A
chip is provided and has an active surface, on which a plurality of
bonding pads are formed. The active surface of the chip corresponds
to the surface of the substrate. A plurality of solder balls are
respectively connected to the bonding pads and the nodes, wherein
sizes of the solder balls are varied to allow the chip to bond to
the chip locating region of the substrate. A molding compound is
filled in between the chip and the substrate and is used to
encapsulate the solder balls. The solder balls are arranged in a
matrix, and sizes of the solder balls located at a center region of
the chip locating region are smaller than sizes of the solder balls
located at a peripheral region of the chip locating region.
[0012] It is another object of the present invention to provide a
flip chip interconnected structure comprising a chip that has an
active surface on which a plurality of bonding pads are formed. A
substrate also is provided and has a surface, a chip locating
region and a plurality of nodes. The chip locating region is on the
surface of the substrate and the nodes are formed on the chip
locating region. The chip locating region further comprises solder
mask openings, and the nodes are exposed by the solder mask
openings. Sizes of the solder mask openings are varied. A plurality
of solder balls are respectively connected to the bonding pads and
the nodes. The chip is bonded to the chip locating region of the
substrate by the solder balls. The active surface of the chip
corresponds to the surface of the substrate. A molding compound is
filled in between the chip and the substrate and is used to
encapsulate the solder balls. The solder mask openings are arranged
in a matrix, and sizes of the solder mask openings located at a
center region of the chip locating region are larger than sizes of
the solder mask openings located at a peripheral region of the chip
locating region.
[0013] It is another object of the present invention to provide a
method of fabricating a flip chip interconnected structure. The
steps of the method comprise first providing a chip that has an
active surface. A plurality of bonding pads are formed on the
active surface, and a plurality of bumps are formed on the bonding
pads. A substrate is provided, which has a surface and a chip
locating region. The chip locating region is on the surface of the
substrate, and a plurality of nodes are formed on the chip locating
region. Solder paste is used to cover the chip locating region and
the nodes. The solder paste forms a plurality of solder structures
with various sizes. A bonding process is performed to bond the
active surface of the chip to the surface of the substrate by
bonding the bumps to the solder structures. A heating process is
carried out to combine the bumps and solder structures to form a
plurality of solder balls. The solder balls are bonded respectively
to the bonding pads and the nodes. The chip is bonded to the chip
locating region of the substrate through the solder balls. A
stencil printing board has a plurality of openings. The stencil
printing board is located on the substrate and the nodes are
exposed by the openings. The openings are filled with the solder
paste by a screen printing method. Positions of the solder paste
correspond to positions of the nodes. The solder paste forms solder
structures with various sizes because the sizes of the openings are
different. The openings are arranged in a matrix, and sizes of the
openings located at a peripheral region of the stencil printing
board are larger than sizes of the openings near a center region of
the stencil printing board. Therefore, the amount of solder paste
filled in the opening at the peripheral region is more than the
amount of solder paste filled in the openings at the center
region.
[0014] It is another object of the present invention to provide a
method of fabricating a flip chip interconnected structure. The
steps of the method comprise first providing a chip having an
active surface. A plurality of bonding pads are formed on the
active surface, and a plurality of bumps are formed on the bonding
pads. A substrate having a surface is provided, wherein a chip
locating region is on the surface. A solder mask layer and a
plurality of nodes are formed on the chip locating region. A
plurality of solder mask openings are formed on the solder mask
layer, and the nodes are exposed by the solder mask openings,
wherein the solder mask openings have various sizes. Solder paste
is used to cover the chip locating region and the nodes. A bonding
process is performed to bond the active surface of the chip to the
surface of the substrate by bonding the bumps to the solder paste.
A heating process is carried out to combine the bumps and solder
paste to form a plurality of solder balls. The solder balls are
bonded respectively to the bonding pads and the nodes. The chip is
bonded to the chip locating region of the substrate through the
solder balls. Sizes of the solder mask openings located at a center
region of the chip locating region are larger than sizes of the
solder mask openings located at a peripheral region of the chip
locating region.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are included to provide a further
understanding of the present invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention. In the
drawings,
[0016] FIGS. 1 and 2 are schematic views of a conventional flip
chip package.
[0017] FIG. 3 is a schematic view of a flip chip interconnected
structure in accordance with a preferred embodiment of the present
invention.
[0018] FIG. 3A is a schematic top view of a stencil printing
board.
[0019] FIG. 4 is a cross-sectional view of a flip chip
interconnected structure in accordance with a preferred embodiment
of the present invention.
[0020] FIG. 4A is a schematic magnified view of a solder ball in
accordance with a preferred embodiment of the present
invention.
[0021] FIG. 5 is a cross-sectional view of a flip chip
interconnected structure in accordance with a preferred embodiment
of the present invention.
[0022] FIGS. 6, 7 and 8 are schematic cross-sectional views of a
flip chip interconnected structure in accordance with another
preferred embodiment of the present invention.
[0023] FIG. 6A is a schematic top view of solder mask openings on a
substrate.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] FIG. 3 illustrates a schematic view of a flip chip
interconnected structure in accordance with a preferred embodiment
of the present invention. Referring to FIG. 3, a chip comprises an
active surface 212. A plurality of bonding pads 214, which are
formed on the active surface 212 have a plurality of bumps 216. A
substrate 220 comprises a surface 222 and a chip locating region
224 on which a chip is located. A plurality of nodes 226 are formed
on the chip locating region 224.
[0025] FIG. 3A illustrates a schematic top view of a stencil
printing board. Referring to FIG. 3A, a stencil printing board 230
has a plurality of openings 232. The stencil printing board 230 is
located on a substrate 220, and the nodes 226, which are located at
the chip locating region 224, are exposed by the openings 232. The
openings 232 are filled with solder paste by a screen printing
method. When the screen printing process is carried out, the
stencil printing board 230 is removed and the solder paste 240
located in the openings are remained on the surface 222 of the
substrate. Positions of the solder paste 240 correspond to
positions of the nodes 226. The openings 232 are arranged in a
matrix shape, and sizes of the openings 232 located at a peripheral
region of the stencil printing board 230 are larger than sizes of
the openings near a center region of the stencil printing board
230. Therefore, the amount of solder paste filled in the opening
232 at the peripheral region is more than the amount of solder
paste filled in the openings 232 at the center region.
[0026] FIG. 4 illustrates a cross-sectional view of a flip chip
interconnected structure in accordance with a preferred embodiment
of the present invention. Referring to FIGS. 3 and 4, a bonding
process is carried out to bond the active surface 212 of the chip
210 to the surface of the substrate 222. A reflow process is
utilized to bond the bumps 216 to the solder paste 240 into solder
balls 250, which are bonded to the bonding pads 214 and the nodes
226. The active surface 212 of the chip 210 is bonded onto the
surface of chip locating region 224 by the solder balls 250. Since
the sizes of the openings 232 are larger at the peripheral region
than at the center region, sizes of solder balls 250 are larger at
a peripheral region of the chip locating region 224 than at a
center region of the chip locating region 224.
[0027] FIG. 4A illustrates a schematic magnified view of a solder
ball in accordance with a preferred embodiment of the present
invention. Referring to FIG. 4A, the bumps 216 are made of a
material such as a tin/lead alloywith a ratio of about 5/95 and an
eutectic point of approximately 312.degree.. The solder paste 240
is made of a material such as a tin/lead alloy with a ratio of
about 63/37 and an eutectic point of approximately 183.degree..
During the reflow process, a temperature in a reflow oven (not
shown) is about 200.degree.. Therefore the bumps 216 will not melt
but the solder paste 240 will melt and cover the periphery of the
bumps 216 to form the solder balls 250. Thus, the chip 210 is
bonded to the substrate 220.
[0028] FIG. 5 illustrates a cross-sectional view of a flip chip
interconnected structure in accordance with a preferred embodiment
of the present invention. Referring to FIG. 5, a molding process is
performed to encapsulate a gap between the active surface 212 of
the chip 210 and the chip locating region 224 of the substrate 222
with an encapsulating material including a molding compound 260.
The molding compound 260 encapsulates the solder balls 250.
[0029] From the above-mentioned fabrication of a flip chip, the
substrate 220 will bend after the reflow process, and a deformation
will occur. Therefore, a gap at a center region of the chip 210 and
the chip locating region 224 is smaller than a gap at the ends of
the chip 210 and the chip locating region 224. However, the
openings 232 of the screen printing board 230 of the present
invention are designed in such a way that the sizes of the openings
232 are larger at the peripheral region than at the center region.
Thus, the sizes of solder balls 250 are larger at a peripheral
region of the chip locating region 224 than at a center region of
the chip locating region 224. The bonding between the chip 210 and
the substrate 220 is much stronger at the peripheral region than at
the center region. Therefore, even though bending of the substrate
occurs, the bending effect does not affect the chip and the
substrate. The electrical connection and the reliability between
the chip 210 and the substrate 220 are improved.
[0030] However, the present invention is not limited to the
above-mentioned fabrication method and structure. FIGS. 6, 7 and 8
illustrate schematic cross-sectional views of a flip chip
interconnected structure in accordance with another preferred
embodiment of the present invention. A chip 410, which is provided,
has an active surface 412. A plurality of bonding pads 414 are
formed on the active surface 412 of the chip 410. Bumps 416 are
formed on the bonding pads 414. FIG. 6A illustrates a schematic top
view of solder mask openings on a substrate. Referring to FIGS. 6
and 6A, a substrate 420 has a surface 422. The surface 422 of the
substrate 420 has a chip locating region 424. A solder mask layer
426 is formed on the surface 422 of the substrate 420. A plurality
of solder mask openings 428 are formed in the solder mask layer 426
and each opening 428 exposes a node 430. The solder mask openings
428 are arranged in a matrix shaped, and sizes of the solder mask
openings 428 located at a center region of the chip locating region
424 are larger than sizes of the solder mask openings 428 located
at a peripheral region of the chip locating region 424.
[0031] Referring to FIG. 6, the solder mask openings 428 are filled
with solder paste by a screen printing method, wherein the
formation of the solder paste 440 corresponds to locations of the
nodes 430 of the chip locating region 424.
[0032] FIG. 7 illustrates a schematic cross-sectional view of a
flip chip interconnected structure in accordance with another
preferred embodiment of the present invention. Referring to FIGS. 6
and 7, a bonding process is carried out to bond the active surface
412 of the chip 410 to the surface 422 of the substrate 420. The
bumps 416 are bonded to the solder paste 440 and a reflow process
is performed to combine the bumps 416 with the solder paste 440 to
form a plurality of solder balls 450. The solder balls 450 are
respectively bonded to the bonding pads 414 and the nodes 430. The
sizes of the solder mask openings 428 located at the center region
of the chip locating region 424 are larger than the sizes of the
solder mask openings 428 located at the peripheral region of the
chip locating region 424. Thus, during the bonding process, bending
occurs at edges of the substrate 420. Due to the stress of the
bending of the substrate 420, the solder balls 450 at the
peripheral region of the chip locating region 424 will form into a
cylindrical shape. However, the solder balls 450 at the center
region of the chip locating region 424 will form into a circular
shape. Therefore, the shapes of the solder balls 450 are varied
along the chip location region according to the sizes of the solder
mask openings 428. Since the solder mask openings 428 have various
sizes, the amount of the solder paste 440 in the solder mask
openings 428 are different. By utilizing the different sizes of the
solder mask openings 428 and the amount of the solder paste 440,
the solder balls 450 are formed into various shapes; thus, the
bonding between the chip 410 and the substrate 420 is improved to
overcome the stress caused by the bending effect. Because the sizes
of the solder mask openings 428 at the center region are larger
than the sizes of the solder mask openings 428 at the peripheral
region, after the formation of the solder balls 450, the solder
balls located at the center region of the chip locating region 424
are shorter than the solder balls located at the peripheral region
of the chip locating region 424.
[0033] From the above-mentioned, the substrate 420 will bend after
the reflow process, and a deformation will occur. Therefore, a gap
at a center region of the chip 410 and the chip locating region 424
is smaller than a gap at the ends of the chip 410 and the chip
locating region 224. However, the solder mask openings 428 of the
present invention are designed in such a way that the sizes of the
solder mask openings 428 at the center region of the chip locating
region 424 are larger than the solder mask openings 428 located at
the peripheral region of the chip locating region 424. Thus, the
present invention utilizes the various sizes of the solder mask
openings 428 to control the sizes of the solder balls 250. As a
matter of fact, the solder balls 450 at the center region of the
chip locating region 424 are shorter than the solder balls 450 at
the peripheral region of the chip locating region 424. Therefore,
despite the stress caused by the bending effect, the bonding
between the substrate 420 and the chip 410 is strong enough both at
the peripheral region and the center region. Therefore, the gap
along the chip locating region 424 varies, but shorter solder balls
450 at the center region and higher solder ball 450 at the
peripheral region allow the substrate 420 to bond strongly to the
chip 410. Thus, the bonding between the solder balls 450, the
bonding pads 414 and the nodes 430 are significantly improved.
[0034] However, the present invention can combine the
above-described methods in both embodiments to fabricate the flip
chip interconnected structure, and the bonding effect between the
solder balls, chip and the substrate can be significantly
improved.
[0035] Other embodiments of the invention will appear to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein. It is intended that the
specification and examples to be considered as exemplary only, with
a true scope and spirit of the invention being indicated by the
following claims.
* * * * *