U.S. patent application number 09/797153 was filed with the patent office on 2002-10-24 for fast-setting, low power, jammer insensitive, biasing apparatus and method for single-ended circuits.
Invention is credited to Gharpurey, Ranjit, Sirna, Gugliemo.
Application Number | 20020153955 09/797153 |
Document ID | / |
Family ID | 26940008 |
Filed Date | 2002-10-24 |
United States Patent
Application |
20020153955 |
Kind Code |
A1 |
Gharpurey, Ranjit ; et
al. |
October 24, 2002 |
FAST-SETTING, LOW POWER, JAMMER INSENSITIVE, BIASING APPARATUS AND
METHOD FOR SINGLE-ENDED CIRCUITS
Abstract
A single-ended circuit, such as an LNA (300), in accordance with
the present invention includes an input power matching circuit
(310) and a bias circuit (305) connected to an output transistor
(Q.sub.in) which provides the amplification. A degeneration
inductance (L.sub.e) and load impedance (L.sub.o) couple to the
emitter and collector of the output transistor (Q.sub.in),
respectively. The bias circuit (305) is configured to eliminate
base shot-noise of the output transistor (Q.sub.in) which generates
the amplification. The bias circuit (305) in accordance with the
present invention also eliminates the noise of the bias resistor
(R.sub.x1) that is included within the bias circuit (305).
Specifically, the bias circuit (305) includes a current reference
source (I.sub.ref) and an emitter follower circuit (315) connected
to a current mirror circuit (Q.sub.1, Q.sub.2, R.sub.x2) that
connects to a bias resistor(R.sub.x1). This bias circuit (305) can
be implemented in a wide-class of single-ended circuits.
Inventors: |
Gharpurey, Ranjit; (Plano,
TX) ; Sirna, Gugliemo; (Richardson, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
26940008 |
Appl. No.: |
09/797153 |
Filed: |
March 1, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60249370 |
Nov 16, 2000 |
|
|
|
Current U.S.
Class: |
330/296 ;
330/302 |
Current CPC
Class: |
H03F 2200/372 20130101;
H03F 2200/294 20130101; H03F 1/302 20130101 |
Class at
Publication: |
330/296 ;
330/302 |
International
Class: |
H03F 003/191 |
Claims
What is claimed is:
1. A low noise amplifier, having an input node and an output node
comprising: an input power matching circuit including a filter and
a blocking capacitor, the input node coupled to the filter, the
filter coupled to the blocking capacitor; an output transistor
having a base, collector and emitter, the base coupled to the
blocking capacitor, the collector coupled to the output node; a
bias circuit having a bias resistor, the bias circuit coupled to
the base of the output transistor such that the bias circuit
eliminates base shot-noise of the output transistor and noise of
the bias resistor; a degeneration inductance coupled to the emitter
of the output transistor; and a load impedance coupled to the
output node.
2. The low noise amplifier as recited in claim 1, wherein the
filter comprises a capacitor and an inductor, the capacitor coupled
to the input node, the inductor coupled to the blocking
capacitor.
3. The low noise amplifier as recited in claim 1, wherein the bias
circuit comprises a current mirror circuit, a current reference
source, the bias resistor, and an emitter follower circuit, the
current reference source coupled to the current mirror circuit, the
emitter follower circuit coupled to the current mirror circuit, the
current mirror circuit coupled to the bias resistor.
4. The low noise amplifier as recited in claim 3 wherein the
emitter follower circuit comprises a current source, a capacitor,
and a first transistor having a base, a collector and a emitter,
the current source and the capacitor coupled to the emitter of the
first transistor.
5. The low noise amplifier as recited in claim 3 wherein the
current mirror circuit includes a second resistor, a first and
second current mirror transistor each having a respective base,
collector and emitter, the base of the first current mirror
transistor and the collector of the second current mirror
transistor coupled to the reference current source, the second
resistor coupled between the base of the second current mirror
transistor and the emitter of the first current mirror transistor,
the emitter of the first current mirror transistor coupled to the
bias resistor.
6. A single-ended circuit, having an input node, an output node, a
power supply rail and ground, comprising: (a) a first inductor
coupled to the input node; (b) a first capacitor coupled between
the first resistor and ground; (c) a blocking capacitor coupled in
series to the first inductor; (d) a biasing circuit comprising: (i)
a first transistor, having a base, emitter and collector, the
collector of the first transistor coupled to the power supply rail;
(ii) a first current source coupled between the emitter of the
first transistor and ground; (iii) a reference current source
coupled between the power supply rail and the base of first
transistor; (iv) a second transistor, having a base, emitter and
collector, the collector of the second transistor coupled to the
reference current source, and the emitter of the second transistor
coupled to ground; (v) a second capacitor coupled between the
emitter of the first transistor and the base of the second
transistor; (vi) a third transistor, having a base, emitter and
collector, the collector coupled to the power supply rail, the base
coupled to the collector of the first transistor; and (vii) a
second resistor coupled between the base of the second transistor
and the emitter of the third transistor; (e) a third resistor
coupled between the second resistor and the blocking capacitor; (f)
a fourth transistor, having a base, emitter and collector, the base
coupled to the third, the collector coupled to the output node; (g)
a second inductor coupled between the emitter of the fourth
transistor and ground; and (h) a third inductor coupled between the
power supply rail and the output node.
7. A bias circuit to filter noise comprising: (a) an emitter
follower circuit comprising (i) a first transistor having a base,
collector and emitter; (ii) a current source coupled between the
emitter of first transistor and ground; and (iii) a capacitor
coupled to the emitter of the first transistor; (b) a current
mirror circuit coupled to the emitter follower circuit, the current
mirror circuit comprising (i) a second transistor having a base,
collector and emitter, the collector of the second transistor
coupled to the power supply rail, the base of the second transistor
coupled to the base of the first transistor; and (ii) a third
transistor having a base, collector and emitter, the collector of
the third transistor coupled to the base of the second transistor,
the base of the third transistor coupled to the capacitor, the
emitter of the third transistor coupled to ground; and (iii) a
resistor coupled between the emitter of the second transistor and
the base of the third transistor; and (c) a current reference
source coupled between the power supply rail and the base of the
second and third transistors.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices, and,
more particularly, to a fast-settling, low power, biasing circuit
for single-ended circuits.
BACKGROUND OF THE INVENTION
[0002] Radio Frequency (RF) receivers include preamplifiers to
boost an incoming signal level prior to the frequency conversion
process. The presence of intermodulation products produced by large
interfering signals compromises the receiver's ability to process
very weak signals. This is what is conventionally known as
desensitization. Third-order intermodulation occurs when two
interfering signals at differing frequencies combine in the
amplifier third-order nonlinearity to produce an intermodulation
product close to the desired signal.
[0003] Desensitization may also occur when a single large
interfering signal (i.e. a blocker or jammer) is present. The
reduction in sensitivity arises through two separate mechanisms.
The first, gain compression, is caused by third-order nonlinearity
in the circuit, allowing the existing noise source in the amplifier
and mixer to exert a larger influence, thus degrading the overall
noise performance. The second mechanism, second-order nonlinearity
in the circuit, promotes mixing between relatively low-frequency
noise sources in the amplifier and the interfering signal. As a
result, low-frequency noise is up-converted to the desired signal
frequency which degrades the circuit noise performance. More on the
study of blocking and desensitization can be found in "Blocking and
Desensitization in RF Amplifiers," R. G. Meyer and A. K. Wong, IEEE
(1995), which is incorporated by reference herein.
[0004] Particularly, desensitization occurs in single-ended
circuits, such as single-ended front-end Low-Noise Amplifiers
(LNAs) for wireless receivers, that operate in the presence of
jammers due to an increase in the noise floor at the output of the
circuit and gain compression. Essentially, distortion in the
circuit causes an up-conversion of low-frequency noise into the
band of interest. This added noise increases the noise-floor of the
circuit, that causes the Signal-to-Noise Ratio (SNR) at the output
of the amplifier to degrade considerably in the presence of large
amplitude jammers.
[0005] A primary source of low-frequency noise is noise generated
in the bias circuit of the single-ended circuit. A new technique
for reducing bias noise in a conventional LNA circuit is presented
in FIG. 1a. The bias circuit shown prevents desensitization from
occurring. This single-transistor LNA circuit includes a transistor
Q.sub.in as its primary gain device. As shown, power supply P.sub.s
applies a voltage input to the circuit. An output is observed at
output node P.sub.out. The bias circuit is composed of transistors
Q.sub.1 and Q.sub.2, that act as mirror devices. If the device area
of transistors Q.sub.in and Q.sub.1 is A.sub.in and A.sub.1,
respectively, then the current flowing through transistor Q.sub.in
is I.sub.ref(A.sub.in/A.sub.1). A resistor R.sub.x1 is added in
series with the bias circuit, to ensure that the incoming Radio
Frequency (RF) power is not diverted into the bias circuit and is
supplied primarily to transistor Q.sub.in for proper amplification.
Since a base current flows into transistor Q.sub.in, a static
voltage drop develops across resistor R.sub.x1. In order to balance
this drop, a resistor R.sub.x2 is added in series with the base of
transistor Q.sub.1. Note that the base current in transistor
Q.sub.in equals the base current of transistor Q.sub.1 multiplied
by A.sub.in/A.sub.1. Therefore in order to balance the base-current
drops, resistor R.sub.x2 must equal R.sub.x1(A.sub.in/A.sub.1).
[0006] In practice, an RF signal represented by v.sub.a
cos(.omega.t) may be applied to the input of the LNA circuit;
meanwhile a jammer signal of strength v.sub.a'
cos((.omega.+.DELTA..omega.)t) may be applied to the input of the
LNA as well. The jammer is much larger than the incoming RF signals
in most wireless standards. For example, the Global System for
Global Communication (GSM) standard requires that the LNA should
not suffer any degradation in the output SNR in the presence of a
-23 dBm jammer that is at a frequency 3 MHz away from the incoming
RF signal having a power level of -98 dBm. With this level of
jammer signal, low-frequency noise can be up-converted as explained
above. At node 1, there exists low-frequency noise from the bias
circuit output. Due to second-order harmonic distortion inherent in
the LNA, the jammer tone beats with low-frequency noise at
frequency .DELTA..omega., and converts the noise upward to
.omega.+.DELTA..omega.+.DELTA..omega. and
.omega.+.DELTA..omega.-.DELTA..omega.. The latter term is at the
same frequency as the desired signal. Thus, the SNR ratio at the
desired output frequency suffers. It should be noted that this
effect scales with the strength of the jammer, such that is the SNR
degrades more for larger jammer strengths. This effect is shown in
FIGS. 1b and 1c.
[0007] The following noise sources impact the total noise at low
frequencies in the bias circuit: a) the noise of the reference bias
(I.sub.ref), b) the noise of bias resistor R.sub.x2, c) the base
shot-noise of transistor Q.sub.1, and d) the collector shot-noise
of transistor Q.sub.1. Several other noise sources, however, may
exist in a LNA circuit; yet, their impact is negligible. As a
consequence of the tightly coupled feedback loop formed by
transistors Q.sub.1 and Q.sub.2 and resistor R.sub.x2, the
impedance seen by the reference current source, I.sub.ref, is of
the order of the inverse of the transconductance g.sub.m of
transistor Q.sub.1. This is a small quantity in most bias circuits.
Consequently, the noise of the reference bias circuit is small at
its output, node X. In addition, as a result, the collector
shot-noise of transistor Q.sub.1 is mitigated. The remaining noise
sources noted above in b) and c) are major noise sources in the LNA
circuit shown in FIG. 1a, since this circuit presents these noise
sources with a relatively high impedance at the base of transistor
Q.sub.1. Thus, noise current at this node develops a large noise
voltage, which is effectively amplified by transistor Q.sub.1 at
its collector node. Since transistor's Q.sub.2 placement with
adjacent elements is such that it represents a voltage follower
circuit, any noise at its base appears on its emitter with little
attenuation. Hence, a large noise voltage develops at the base of
transistor Q.sub.in. As explained above, this low-frequency noise
can be up-converted to RF frequencies.
[0008] An approach that has been used to mitigate the noise
up-conversion, is the use of external passive LC filters at the
input node of the LNA circuit, or at the collector of transistor
Q.sub.1 is shown in FIG. 2. The indicated LC circuit including
inductor L.sub.n and capacitor C.sub.n creates a notch in the
frequency domain at the frequency equal to the difference between
the jammer and the signal-frequency. Thus, any noise on the bias
line is filtered off at this frequency. The notch LC filter is so
designed, that it appears as a very high impedance at the
radio-frequency, and hence has a minimal impact on circuit
performance. The LC notch circuit is effective in reducing the
influence of the jammer.
[0009] This approach, however, has several disadvantages. First, it
requires the use of external inductor and capacitor elements which
add to the total cost of the solution. Second, the value of the
capacitor in the notch filter is relatively high, since the
filtering action is required at low frequencies. As a consequence,
when the amplifier is powered on, it requires a long time to settle
to its steady state, often in the order of hundreds of
microseconds, which may be unacceptable in the overall system.
Third, parasitics introduced by the large external components can
degrade RF performance.
[0010] It should also be pointed out, that the solution of using a
tuned series LC circuit applied at the input of the amplifier is
very effective in suppressing the noise of resistor R.sub.x1 and
the base shot noise of transistor Q.sub.in as well, in addition to
suppressing the noise of the bias circuit. However, there are
several practical problems with this implementation as mentioned
above namely increase in the cost because of added external
components, slow turn-on time, and worsened RF performance due to
added parasitics of the external tank components. If a noise filter
is used at the collector of transistor Q.sub.1, it will show the
same small increase due to the noise from resistor R.sub.x1 and the
base shot noise of transistor Q.sub.in.
[0011] Thus, a need exists for a fast settling, low power biasing
technique for a single-ended circuit.
SUMMARY OF THE INVENTION
[0012] To address the above-discussed deficiencies of the biasing
circuitry for single-ended circuits, the present invention teaches
a fast settling, low power biasing circuit and method for
single-ended circuits. In particular, a LNA in accordance with the
present invention includes an input power matching circuit, an
output transistor, a bias circuit, a degeneration inductance, and a
load impedance. The input power matching circuit and the bias
circuit couple to the output transistor which provides the
amplification. The degeneration inductance and load impedance
couple to the emitter and collector of the output transistor,
respectively. The bias circuit is configured to eliminate base
shot-noise of the output transistor which generates the
amplification. The bias circuit in accordance with the present
invention also eliminates the noise of the bias resistor that is
included within the bias circuit.
[0013] Specifically, the bias circuit includes a current mirror
circuit, a current reference source, the bias resistor, and an
emitter follower circuit. The current reference source and the
emitter follower circuit are connected to the current mirror
circuit which connects to the bias resistor. This biasing circuit
can be implemented in a wide-class of single-ended circuits.
[0014] Advantages of this design include but are not limited to a
fully integratable solution which eliminates up-converted noise due
to the presence of jammer signals. Since an LNA circuit in
accordance with the present invention can be fully integrated
on-chip, the additional cost is negligible and, hence, acceptable.
Further, the turn-on time of the circuit is small, and acceptable
in most systems.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] For a more complete understanding of the present invention
and the advantages thereof, reference is now made to the following
description taken in conjunction with the accompanying drawings in
which like reference numbers indicate like features and
wherein:
[0016] FIG. 1a is a known embodiment of a low-noise amplifier
(LNA);
[0017] FIG. 1b is a diagram of the input power vs. frequency of the
noise and the up-converted noise in the presence of a jammer
signal;
[0018] FIG. 1c is a diagram of the input power vs. frequency of the
noise and the up-converted noise in the presence of a larger jammer
signal;
[0019] FIG. 2 is another known embodiment of a LNA;
[0020] FIG. 3 is a embodiment of a LNA in accordance with the
present invention;
[0021] FIG. 4 is a diagram of the capacitance of capacitor C.sub.m
vs. frequency in the presence of a jammer signal;
[0022] FIG. 5 is an alternate embodiment of a LNA; and
[0023] FIG. 6 is an alternate embodiment of a LNA.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0024] The proposed biasing apparatus 300 and technique, as shown
in FIG. 3, can be implemented in a wide-class of single-ended
circuits. A single-ended circuit, such as an LNA (300), in
accordance with the present invention includes an input power
matching circuit (310) and a bias circuit (305) connected to an
output transistor (Q.sub.in) which provides the amplification. A
degeneration inductance (L.sub.e) and load impedance (L.sub.o)
couple to the emitter and collector of the output transistor
(Q.sub.in), respectively.
[0025] The bias circuit (305) is configured to eliminate base
shot-noise of the output transistor (Q.sub.in) which generates the
amplification. The bias circuit (305) in accordance with the
present invention also eliminates the noise of the bias resistor
(R.sub.x1) that is included within the bias circuit (305).
Specifically, the bias circuit (305) includes a current reference
source (I.sub.ref) and an emitter follower circuit (315) connected
to a current mirror circuit (Q.sub.1, Q.sub.2, R.sub.x2) that
connects to a bias resistor (R.sub.x1). This bias circuit (305) can
be implemented in a wide-class of single-ended circuits.
[0026] More particularly, the design consists of a capacitor
C.sub.m, of a value that can be integrated on-chip using known
integrated circuit (IC) processes (.about.5-20 pf), and an emitter
follower circuit consisting of transistor Q.sub.m, where the
transistor Q.sub.m is biased with a small current of the order of a
tenth of a milli-ampere (I.sub.m). Transistor Q.sub.m is placed in
an emitter follower configuration that connects to the collector of
transistor Q.sub.1. Since emitter followers are ideally unity gain
voltage buffers, node X and node Y are ideally at the same
potential. In effect, a low-frequency pole is introduced at a
frequency of 1/2.pi.R.sub.x2C.sub.m. Since resistor R.sub.x2 is
usually a large resistance, the value of capacitance C.sub.m,
required on-chip is small and can be integrated on-chip (in the
order of 5-20 pF for most applications). In response to any current
noise, i.sub.bn, injected into the base of transistor Q.sub.1, the
voltage generated at the base is given by: 1 bn 2 i bn 2 ( ( R x 2
2 1 + 2 R x 2 2 C m 2 ) / ( g m 1 R c 1 ) 2 )
[0027] where resistance R.sub.c1 is the total load seen at the
collector of transistor Q.sub.1. The voltage at the collector of
transistor Q.sub.1 and hence at node X, is given by: 2 Xn 2 i bn 2
( ( R x 2 2 1 + 2 R x 2 2 C m 2 ) )
[0028] As shown, capacitor C.sub.m significantly attenuates the
noise. If the -3 dB corner frequency above is, for example, 1 MHz,
then at a 3 MHz offset, the noise will be attenuated by a factor of
10 or by 10 dB. In a similar fashion, the up-converted noise will
also be attenuated by 10 dB. Another notable characteristic is that
the attenuation increases with frequency.
[0029] Since the jammer in most systems is specified at a fixed
offset compared to the desired RF signal, capacitor C.sub.m can be
sized to provide adequate attenuation of the up-converted noise,
through simulation, or hand analysis.
[0030] FIG. 4 illustrates the current noise at the output of the
amplifier, with -90 dBm power input (no jammer) and -23 dBm input
(with jammer), with and without the noise filtering circuit
proposed here. Spectre RF was used for the simulation examples
shown. The following component values have been assumed: Iref=0.2
mA, R.sub.x2=32 k.OMEGA., R.sub.x1=2 k.OMEGA.. Three values of
capacitor C.sub.m are displayed, including -5 pF, 10 pF and 20
pF.
[0031] With no jammer applied at the input, the noise at an offset
of 3 MHz is approximately 82 pA/sqrt Hz. Without the solution
proposed here, the noise increases to approximately 390 pA/sqrt Hz,
due to the noise up-conversion process detailed earlier. In
conclusion, the circuit reduces this noise to approximately 120
pA/sqrt Hz. Note that there is still a minor increase in the noise
level compared to the case without a jammer due to a small increase
in the noise floor and low-frequency noise from resistor R.sub.x1
and transistor Q.sub.in. The level of increase, however is
acceptable in most systems, since in most wireless systems, a small
increase in the noise floor is acceptable with an applied jammer.
This implementation can be adapted by a circuit designer to meet
system requirements.
[0032] Advantages of this design include but are not limited to a
fully integratable solution which eliminates up-converted noise due
to the presence of jammer signals. Since an LNA circuit in
accordance with the present invention can be fully integrated
on-chip, the additional cost is negligible and, hence, acceptable.
Further, the turn-on time of the circuit is small, and acceptable
in most systems.
[0033] A second embodiment as shown in FIG. 5 is an approach that
reduces the noise because of the thermal noise of resistor R.sub.x2
and the base shot noise of transistor Q.sub.1, by placing a
capacitor, between node B and ground. However, note that because of
the tight feedback loop formed by transistor Q.sub.1 and Q.sub.2
around R.sub.x2, the net impedance at node B is approximately
resistance R.sub.x2 divided by the loop gain of the feedback loop.
The loop gain can be a large quantity, since it is set primarily by
the transconductance g.sub.m1, of transistor Q.sub.1. Thus, the
effective impedance at node B is small. Consequently, the
capacitance required at the base of transistor Q.sub.1 is too large
for effective filtering and cannot be integrated.
[0034] A third embodiment includes as shown in FIG. 6 an approach
of filtering the noise by placing a capacitor between nodes B and
X. While this is effective, it introduces a new problem. At radio
frequencies, this capacitor has a small impedance. Thus, the
isolation from current I.sub.ref to the RF input port is severely
compromised by this capacitor.
[0035] The reader's attention is directed to all papers and
documents which are filed concurrently with this specification and
which are open to public inspection with this specification, and
the contents of all such papers and documents are incorporated
herein by reference.
[0036] All the features disclosed in this specification (including
any accompany claims, abstract and drawings) may be replaced by
alternative features serving the same, equivalent or similar
purpose, unless expressly stated otherwise. Thus, unless expressly
stated otherwise, each feature disclosed is one example only of a
generic series of equivalent or similar features.
[0037] The terms and expressions which have been employed in the
foregoing specification are used therein as terms of description
and not of limitation, and there is no intention in the use of such
terms and expressions of excluding equivalents of the features
shown and described or portions thereof, it being recognized that
the scope of the invention is defined and limited only by the
claims which follow.
* * * * *