U.S. patent application number 09/836738 was filed with the patent office on 2002-10-17 for low voltage differential to single-ended converter.
Invention is credited to Kocaman, Namik.
Application Number | 20020149400 09/836738 |
Document ID | / |
Family ID | 25272618 |
Filed Date | 2002-10-17 |
United States Patent
Application |
20020149400 |
Kind Code |
A1 |
Kocaman, Namik |
October 17, 2002 |
Low voltage differential to single-ended converter
Abstract
Method and circuitry for converting a differential logic signal
to a single-ended logic signal eliminate slower PMOS transistors
and speed up the conversion process. In specific embodiments
differential logic signals of the type employed in, for example,
current-controlled complementary metal-oxide-semiconductor (C3MOS)
logic are converted to single-ended rail-to-rail CMOS logic levels
using a differential pair of NMOS transistors with resistors as
load devices and an NMOS current source transistor that provides
dynamically adjusted tail current.
Inventors: |
Kocaman, Namik; (Irvine,
CA) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Family ID: |
25272618 |
Appl. No.: |
09/836738 |
Filed: |
April 16, 2001 |
Current U.S.
Class: |
327/65 |
Current CPC
Class: |
H03K 19/018514 20130101;
H03K 19/01707 20130101; H03K 19/09429 20130101 |
Class at
Publication: |
327/65 |
International
Class: |
H03K 005/22 |
Claims
What is claimed is:
1. A circuit for converting a differential logic signal to a
single-ended logic signal, comprising: a first NMOS transistor
having a gate terminal coupled to receive a first half of the
differential logic signal, a source terminal and a drain terminal;
a second NMOS transistor having a gate terminal coupled to receive
a second half of the differential logic signal, a source terminal
coupled to the source terminal of the first NMOS transistor, and a
drain terminal; a first resistor coupled between the drain terminal
of the first NMOS transistor and a logic high node; a second
resistor coupled between the drain terminal of the second NMOS
transistor and the logic high node; and a third NMOS transistor
having a gate terminal coupled the drain terminal of the first NMOS
transistor, a source terminal coupled to a logic low node, and a
drain terminal coupled to the source terminals of the first and
second NMOS transistors.
2. The circuit of claim 1 wherein the first, second and third NMOS
transistors are of substantially the same size.
3. The circuit of claim 1 further comprising a fourth NMOS
transistor having its drain and source terminals coupled between
the source terminal of the third NMOS transistor and the logic low
node, and a gate terminal coupled to an enable signal.
4. The circuit of claim 1 further comprising a PMOS transistor
inserted between the logic high node and the first and second
resistors with a gate terminal coupled to an enable signal.
5. The circuit of claim 2 wherein the first and second resistors
are substantially made up of polysilicon material.
6. The circuit of claim 1 wherein the logic high node is a positive
power supply node, and the logic low node is ground.
7. The circuit of claim 6 wherein the positive power supply node
carries a voltage that is less than 1.5 volts.
8. The circuit of claim 1 further comprising a current source
device coupled to the drain terminal of the first NMOS
transistor.
9. The circuit of claim 8 wherein the current source device
comprises a fourth NMOS transistor having a drain terminal coupled
to the drain terminal of the first NMOS transistor, a source
terminal coupled to the logic low node, and a gate terminal coupled
to a bias voltage.
10. A complementary metal-oxide-semiconductor (CMOS) circuit
comprising: a first circuit implemented in current-controlled CMOS
(C.sup.3MOS) logic wherein logic levels are signaled by current
steering in one of two or more branches in response to a
differential input signal; a differential signal to single-ended
signal converter coupled to the first circuit, the converter
including a differential stage with resistive loads instead of PMOS
transistors and a dynamically adjusted tail current and configured
to convert the differential signal from the first circuit to a
single-ended CMOS logic signal; and a second circuit coupled to the
converter to receive the single-ended CMOS logic signal and
implemented in standard CMOS logic wherein substantially zero
static current is dissipated.
11. The CMOS circuit of claim 10 wherein the differential signal to
single-ended signal converter further comprises: a differential
pair of input NMOS transistors each coupled to a logic high node
via a respective load resistor; and a current source NMOS
transistor coupled between the differential pair of input NMOS
transistors and a logic low node, and having a gate coupled to a
drain terminal of one of the differential pair of input NMOS
transistors.
12. A method of converting a differential logic signal to a
single-ended logic signal comprising: receiving the differential
logic signal at inputs of a differential pair of NMOS transistors;
pulling up a signal at drain terminals of the pair of NMOS
transistors using resistors instead of PMOS transistors; and
feeding back an output signal to dynamically adjust a current
through the NMOS transistors.
13. The method of claim 12 further comprising disabling a current
flow through the NMOS transistors when conversion is not required.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates in general to integrated
circuits, and in particular to improved method and circuitry for
converting a differential logic signal of the type employed in, for
example, current-controlled complementary metal-oxide-semiconductor
(C.sup.3MOS) logic, to single-ended logic signal employed in
standard CMOS logic.
[0002] Converting signals from C.sup.3MOS format which is
differential in nature to standard CMOS format which is
single-ended with rail-to-rail amplitude is a difficult operation.
Most conversion circuits require careful optimization to "shape"
the single-ended rail-to-rail signal. FIG. 1 depicts a conventional
converter circuit with a conventional differential stage 100 that
receives a differential signal Vin+/Vin-. Two optimized CMOS
inverters 102 and 104 made up of transistors with skewed channel
width to length W/L ratios, shape the output signal of differential
stage 100. The rail-to-tail CMOS signal is obtained at output
V.sub.OUT.
[0003] There are a number of disadvantages associated with this
common signal level conversion technique. The two additional
inverters (102 and 104) introduce long delays that may become
unacceptable for ultra high speed applications such as those using
C.sup.3MOS logic. Further, the delay tends to be highly variant
with process corners and temperature. Moreover, the delay for the
high-to-low transition is typically not equal to the delay for the
low-to-high transition in the optimized inverters. This causes
timing problems and, for clock signals, duty cycles deviating from
50%. Other drawbacks of most CMOS differential to single-ended
converters are caused by the use of p-channel MOS (or PMOS)
transistors. PMOS transistors are inherently as much as three to
four times slower than NMOS transistors, and therefore aside from
problems such as duty cycle distortion that is caused by this
mismatch in speed, tend to slow down the overall operation of the
converter circuit. Moreover, when used as load devices (as is often
the case in CMOS level converter circuits), PMOS transistors
introduce additional parasitic capacitance that further slows down
certain internal nodes of the circuit.
[0004] There is therefore a need for differential to single ended
signal level converters that operate effectively at very high
speeds.
BRIEF SUMMARY OF THE INVENTION
[0005] The present invention provides method and circuitry for
converting a differential signal to a single-ended signal for
low-voltage high speed circuit applications. Broadly, the invention
eliminates PMOS transistors from the differential to single-ended
converter circuitry to reduce parasitic capacitive loading. Further
speed enhancements are achieved by employing a feedback mechanism
to adjust the tail current of the converter circuit. In a specific
embodiment, resistors replace load PMOS transistors, and the
circuit is configured to be disabled when not in use to eliminate
static current.
[0006] Accordingly, in one embodiment, the present invention
provides a circuit for converting a differential logic signal to a
single-ended logic signal, including: a first NMOS transistor
having a gate terminal coupled to receive a first half of the
differential logic signal, a source terminal and a drain terminal;
a second NMOS transistor having a gate terminal coupled to receive
a second half of the differential logic signal, a source terminal
coupled to the source terminal of the first NMOS transistor and a
drain terminal; a first resistor coupled between the drain terminal
of the first NMOS transistor and a logic high node; a second
resistor coupled between the drain terminal of the second NMOS
transistor and the logic high node; and a third NMOS transistor
having a gate terminal coupled to the drain terminal of the first
NMOS transistor, a source terminal coupled to a logic low node, and
a drain terminal coupled to the source terminals of the first and
second NMOS transistors.
[0007] In a more specific embodiment of the present invention the
converter further includes a first CMOS inverter having an input
terminal coupled to the drain terminal of the second NMOS
transistor; and a second CMOS inverter having an input terminal
coupled to an output terminal of the first inverter. In a yet more
specific embodiment, the converter includes a fourth NMOS
transistor coupled between the source terminal of the third NMOS
transistor and the logic low node with a gate terminal coupled to
an enable signal.
[0008] In another embodiment, the present invention provides a CMOS
circuit comprising: a first circuit implemented in C.sup.3MOS logic
wherein logic levels are signaled by current steering in one of two
or more branches in response to a differential input signal; a
differential signal to single-ended signal converter coupled to the
first circuit, the converter including a differential stage with
resistive loads instead of PMOS transistors and a dynamically
adjusted tail current configured to convert the differential signal
from the first circuit to a single-ended CMOS logic signal; and a
second circuit coupled to the converter to receive the single-ended
CMOS logic signal and implemented in standard CMOS logic wherein
substantially zero static current is dissipated.
[0009] In yet another embodiment the present invention provides a
method of converting a differential logic signal to a single-ended
logic signal including receiving a differential logic signal at
inputs of a differential pair of NMOS transistors; pulling up a
signal at drain terminals of the pair of NMOS transistors using
resistors instead of PMOS transistors; and feeding back an output
signal to dynamically adjust a current through the NMOS
transistors. The dynamic adjustment of the tail current speeds up
the switching operation and provides proper CMOS logic output
levels.
[0010] The detailed description and the accompanying drawings
provide a better understanding of the nature and advantages of the
signal level converter of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 shows a conventional CMOS differential to
single-ended converter circuit;
[0012] FIG. 2 shows one embodiment of the differential to
single-ended converter according to the present invention;
[0013] FIGS. 3A and 3B show alternative implementations for the
differential to single-ended logic signal converter according to an
embodiment that allows the converter to be disabled; and
[0014] FIG. 4 shows an exemplary circuit application for the
differential logic signal to single-ended logic signal converter
according to an illustrative embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0015] Signal levels used in CMOS logic are rail-to-rail, meaning
that the signal is typically single-ended with its high logic level
typically determined by the positive power supply (e.g., 1.8V) and
its low logic level determined by ground (or the negative power
supply). Certain types of logic circuitry, such as high speed
current-controlled CMOS logic (or C.sup.3MOS logic), use
differential logic signals. Differential C.sup.3MOS logic processes
differential signals that typically have amplitudes less than one
volt, e.g., 500 mV peak-to-peak single-ended. The present invention
provides fast and efficient method and circuitry for converting
such a differential logic signal to a rail-to-rail single-ended
one.
[0016] Referring to FIG. 2, there is shown one embodiment of the
present invention. According to this embodiment, no PMOS
transistors are used as part of the converter circuit 200. A pair
of NMOS transistors M1 and M2 receive the differential logic signal
INP and INN at their gate terminals, respectively. Resistors R1 and
R2 act as load devices for transistors M1 and M2, respectively,
connecting their drain terminals to the logic high node, or power
supply node VDD. Resistors R1 and R2 may be made of, for example,
polysilicon material or other similar resistive materials. A third
NMOS transistor M3 connects between the common source node of
transistors M1 and M2 and logic low node, or ground. The gate of
transistor M3 connects to the drain of transistor M1. The drain of
transistor M1 is a slower complementary output OUTB of converter
200, while the drain of transistor M2 provides the faster output
OUT of converter 200. The output of converter 200 may be followed
by a couple of CMOS inverters 202 and 204.
[0017] The operation of the converter circuit shown in FIG. 2 is as
follows. When the differential signal (INP-INN) is at a logic low
level, transistor M2 is turned on carrying the tail current, and
transistor M1 is turned off, pulling output node OUT close to
ground (or logic low). When (INP-INN) switches from logic low to
logic high, the tail current through transistor M3, I(M3), starts
to flow more through transistor M1. This causes a voltage drop
across load resistor R1 pulling the voltage at node OUTB down
toward ground. This in turn reduces the drive voltage at the gate
of transistor M3 reducing its current I(M3). As the current through
transistor M3 decreases, it requires a smaller (INP-INN) voltage to
switch transistor M2 off. This feedback mechanism therefore helps
to speed up transistor M2 switching off and node OUT rise toward
VDD through resistor R2.
[0018] In the other direction, when the differential input signal
(INP-INN) switches from logic high to logic low, transistor M3
starts with a low signal at its gate and therefore draws a small
amount of current I(M3). With a relatively small I(M3), it requires
a smaller (INP-INN) to steer the current from transistor M1 to
transistor M2. As the current starts to flow through transistor M2,
node OUT starts to move down toward ground and node OUTB moves up
toward VDD. This in turn increases the voltage at the gate of
transistor M3 causing a larger I(M3) to discharge OUT faster.
[0019] Thus, converter 200 operates to quickly charge and discharge
output node OUT between VDD and ground in response to the
differential input signal. The use of resistors R1 and R2 instead
of PMOS transistors eliminates parasitic capacitances at output
nodes OUT and OUTB. The feedback mechanism that adjusts the tail
current I(M3) further enhances the switching speed at output node
OUT. Node OUTB does not switch as fast as OUT in part because of
the capacitive loading introduced by the gate of transistor M3.
However, this does not adversely impact the switching speed of
output node OUT.
[0020] Converter 200 is particularly well suited for low voltage
applications. This is in part because by replacing the PMOS load
transistors with resistors, the circuit requires less voltage
headroom. That is, instead of three stacked transistors between the
power supplies, there only needs to be two plus the voltage drop
across R1 which can be minimized. Furthermore, because of the
feedback arrangement between OUTB and the gate of transistor M3, a
small swing at OUTB can provide sufficient change in the current
drive of transistor M3. The voltage at OUTB therefore may swing not
much more than a threshold voltage for an NMOS transistor.
Alternatively, if the circuit is to be used in a high voltage
application, an additional current source can be employed to adjust
the mid-point of the voltage swing at OUTB. This alternative
embodiment is depicted in phantom in FIG. 2 where NMOS transistor
M3' with its gate receiving a bias voltage VB provides the
additional current source.
[0021] Converter circuit 200 as shown in FIG. 2 dissipates some
static current. When used in a larger circuit, however, converter
200 may not need to be active at all times. To eliminate the static
current when the converter circuit is not in use, in an alternate
embodiment, the present invention inserts an enable transistor M4
between M3 and ground. This embodiment is shown in FIG. 3A. When
the signal ENABLE at the gate terminal of transistor M4 is low,
transistor M4 is turned off disconnecting the current path to
ground and disabling converter 200. In an alternative embodiment,
an ENABLE mechanism is provided using a PMOS transistor between
load resistors R1/R2 and output logic high (VDD) as shown in FIG.
3B. Since the drain terminal of PMOS transistor MP is a common mode
node, it will not slow down the switching operation. When disabled
(i.e., ENABLEB=logic high or VDD), PMOS transistor MP will
disconnect the positive power supply VDD from nodes OUT and OUTB.
This will cause OUT and OUTB nodes to get discharged down to ground
(or negative power supply), effectively turning off the static
power consumption. When enabled (ENABLEB logic low) during normal
operation, there will be a negligible voltage drop (e.g., .about.10
mV )across PMOS transistor MP which will not degrade the swing of
OUT significantly.
[0022] In an exemplary embodiment, the power supply for the
converter is at, e.g., 1.2V, resistors R1 and R2 may have values
of, e.g., 1K.OMEGA., and all NMOS transistors may have channel
sizes of, e.g., 4 .mu./0.13 .mu.. Such exemplary converter
circuitry can convert a differential signal to a single-ended 200
mV to 1.2V signal at very high speeds.
[0023] According to another embodiment of the present invention,
ultra high speed CMOS circuitry is implemented using the
differential to single-ended converter of the type shown in FIGS. 2
or 3. Ultra high speed circuit applications such as synchronous
optical network (SONET) process signals in the several GigaHertz
range. To implement such high speed circuitry using standard
silicon CMOS technology, the high speed signals are first processed
using the faster differential C.sup.3MOS logic and are then divided
down in frequency and converted to CMOS logic for further
processing by standard CMOS logic circuitry. This aspect of the
invention is further described in greater detail in
commonly-assigned co-pending patent application ser. No.
09/484,896, titled "Current-Controlled CMOS Logic Family," by
Hairapetian, filed Jan. 18, 2000, which is hereby incorporated by
reference in its entirety. Referring to FIG. 4, there is shown an
exemplary circuit application for the signal level converter
according to an embodiment of the present invention. In this
illustrative example, a high speed buffer 400 implemented in
C.sup.3MOS logic processes differential C.sup.3MOS logic signals
that are to be converted to standard rail-to-rail CMOS logic signal
for further processing by conventional CMOS logic. The differential
output of buffer 400 is applied to the differential input of
converter 402. Converter 402 is of the type shown in FIGS. 2 or 3
and converts the differential signal to a single-ended CMOS logic
signal that is then applied, in this example, to a divide-by-two
circuit 404. Divide-by-two circuit 404 is implemented using
standard CMOS logic and operates to divide down the frequency of
the signal for further processing by downstream CMOS logic
circuitry. It is to be understood that in other embodiments
C.sup.3MOS buffer 400 may be any other type of C.sup.3MOS logic
(e.g., flipflops, AND, OR, EXOR gates, and the like), and
divide-by-two circuit 404 may similarly be any other type of logic
circuitry using standard CMOS logic signals.
[0024] The present invention thus provides method and circuitry for
converting a differential signal to a single-ended signal for high
speed circuit applications. The invention eliminates PMOS
transistors from the converter circuitry and instead uses resistors
to reduce parasitic capacitive loading. Further speed enhancements
are achieved by employing a feedback mechanism to adjust the tail
current of the converter circuit. While the above provides a
complete description of specific embodiments of the present
invention, it is possible to use various alternatives,
modifications and equivalents. Therefore, the scope of the present
invention should not be limited to the specific and illustrative
embodiment described above, and should instead be determined with
reference to the appended claims along with their full scope of
equivalents.
* * * * *