U.S. patent application number 09/880784 was filed with the patent office on 2002-10-03 for 1-t memory structure capable of performing hidden refresh and an operating method applied thereto.
Invention is credited to Chou, Jonathan Y.P..
Application Number | 20020141268 09/880784 |
Document ID | / |
Family ID | 21677766 |
Filed Date | 2002-10-03 |
United States Patent
Application |
20020141268 |
Kind Code |
A1 |
Chou, Jonathan Y.P. |
October 3, 2002 |
1-T MEMORY STRUCTURE CAPABLE OF PERFORMING HIDDEN REFRESH AND AN
OPERATING METHOD APPLIED THERETO
Abstract
This invention relates to a 1-T memory structure capable of
performing hidden refresh and an operating method applied to the
structure, which uses a data latch and an electrically parallel
path to effectively solve the lost data problem in the art from the
collision of access actions and refresh actions. The structure
includes: a plurality of memory arrays for storing data signal; a
plurality of sense amplifiers for amplifying the data signal of the
respective memory array and temporarily storing the amplified data
signal; a selector for selecting the amplified data signal through
a bus based on a cycle-indicative signal; and a shared data latch
for receiving and storing the data signal from the selector.
Inventors: |
Chou, Jonathan Y.P.; (Taipei
Hsien, TW) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Family ID: |
21677766 |
Appl. No.: |
09/880784 |
Filed: |
June 15, 2001 |
Current U.S.
Class: |
365/222 |
Current CPC
Class: |
G11C 11/4091 20130101;
G11C 11/406 20130101 |
Class at
Publication: |
365/222 |
International
Class: |
G11C 007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 27, 2001 |
TW |
90107145 |
Claims
What is claimed is:
1. A 1-T memory structure capable of performing hidden refresh, the
1-T memory structure comprising: a plurality of memory arrays for
storing data signal; a plurality of sense amplifiers for amplifying
the data signal of the respective memory array and temporarily
storing the amplified data signal; a selector for selecting the
amplified data signal through a bus based on a cycle-indicative
signal; and a shared data latch for receiving and storing the data
signal from the selector.
2. The 1-T memory structure of claim 1, wherein the
cycle-indicative signal is a data access cycle signal.
3. The 1-T memory structure of claim 1, wherein the
cycle-indicative signal is a data refresh cycle signal.
4. The 1-T memory structure of claim 1, wherein the bus is a long
bitline pair.
5. A 1-T memory structure capable of performing hidden refresh, the
1-T memory structure comprising: a row address latch for receiving
a row address data signal externally input and outputting the
memory array address with the row address data signal; a timer for
outputting a timing signal to control a current row address; an
address counter for outputting the memory array address with the
current row address according to the timing signal; an address
comparator for comparing the memory array address with the
externally input row address and the memory array address with the
current row address; a command controller for outputting an
operating cycle signal according to the comparison from the address
comparator; a multiplexer for respectively receiving the addresses
from the row address latch and the address counter; a row address
decoder for decoding the row address from the multiplexer; a memory
array for outputting the corresponding data signal according to the
decoded row address; a sense amplifier for amplifying and
temporarily storing the data signal output from the memory array; a
selector for outputting the amplified data signal through a bus
according to the operating cycle signal; and a shared data latch
for receiving and storing the data signal output by the
selector.
6. The 1-T memory structure of claim 5, wherein the
cycle-indicative signal is a data refresh cycle signal.
7. The 1-T memory structure of claim 5, wherein the
cycle-indicative signal is a data access cycle signal.
8. The 1-T memory structure of claim 5, wherein the bus is a long
bitline pair.
9. An operating method having a 1-T memory structure capable of
performing hidden refresh, comprises the steps: determining if the
collision between data access and data refresh is addressed in the
same memory array; determining the currently operating mode if the
collision happened in the same memory array; if on the data access
cycle mode, concurrently refreshing a data signal through a
respective sense amplifier bank(SAB) and accessing another data
signal through a respective shared data latch(SDL); and if on the
data refresh cycle mode, first storing the data signal to be
refreshed in the shared data latch and then restoring the data
signal to be refreshed to the original memory array using a
cycle-stealing technique after the data access is completed.
10. An operating method of claim 9, wherein in the data access
cycle mode step, the access data signal is transmitted by a bus to
the shared data latch and accessed through the respective local
input and output bus and the respective main input and output
bus.
11. An operating method of claim 10, wherein the bus utilizes a
long bitline pair.
12. An operating method of claim 9, wherein in the data refresh
cycle mode step, the refresh data signal is transmitted by a bus to
the shared data latch.
13. An operating method of claim 12, wherein the bus utilizes a
long bitline pair.
14. An operating method of claim 9, wherein the cycle-stealing
technique utilizes the switch time between the cycle modes to
perform the restored action.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a memory structure, and
particularly to a 1-T memory structure capable of performing hidden
refresh, and an operating method applied to the structure, which
uses a data latch and an electrically parallel path to effectively
eliminate data loss in the prior art from the collision of access
actions and refresh actions.
[0003] 2. Description of the Related Art
[0004] FIG. 1 is a schematic diagram of a unit of cell of typical
1-Transistor memory. In FIG. 1, a 1-Transistor gate G.sub.1T and a
capacitor Cap are connected in serial. As shown in FIG. 1, when the
1-T gate G.sub.1T is turned on by a gate-controlled signal WL, a
data driver (not shown) powers the capacitor Cap through the
bitline selection line BL such that the capacitor Cap is charged to
a saturation state. The data signal stored in such a 1-T memory
formed of FIG. 1 is increasingly lost with passing time. That is,
the charge stored in the capacitor Cap is increasingly reduced.
Accordingly, a data refresh to such a 1-T memory is necessary. For
a 1-T Dynamic Random Access Memory (DRAM), the frequency of data
refresh is about once per 64 ms, and the required time for a data
refresh is about 80 ns. For a 1-T Static Random Access Memory
(DRAM), the frequency of data refresh is about once per 2 ms, and
the required time for a data refresh is about 80 ns. Refresh
actions of this frequency easily cause the collision between access
actions and refresh actions and further increase the complexity of
memory operations.
SUMMARY OF THE INVENTION
[0005] Therefore, an object of the invention is to provide a 1-T
memory structure capable of performing hidden refresh and an
operating method applied to the structure, which uses a data latch
to effectively eliminate data loss in the prior art from the
collision of access actions and refresh actions.
[0006] A further object of the invention is to provide a 1-T memory
structure capable of performing hidden refresh and an operating
method applied to the structure, which uses an electrically
parallel path with simple algorithm to reduce the operating
complexity and effectively solve the aforementioned data loss
problems.
[0007] To realize the above and other objects, the invention
provides a 1-T memory structure capable of performing hidden
refresh and an operating method applied to the structure, which
uses a data latch and an electrically parallel path to effectively
solve the aforementioned data loss problems. The structure
includes: a plurality of memory arrays for storing data signal; a
plurality of sense amplifiers for amplifying the data signal of the
respective memory array and temporarily storing the amplified data
signal; a selector for selecting the amplified data signal through
a bus based on a cycle-indicative signal; and a shared data latch
for receiving and storing the data signal come from the selector.
The operating method includes the following steps: determining if
the collision between data access and data refresh is addressed in
the same memory array; determining the currently operating mode if
the collision happens in the same memory array; if on the data
access cycle mode, concurrently refreshing a data signal through a
respective sense amplifier bank (SAB) and accessing another data
signal through a respective shared data latch (SDL); if on the data
refresh cycle mode, first storing the data signal to be refreshed
in the shared data latch and then restoring the data signal to be
refreshed to the original memory array using the cycle-stealing
technique after the data access is completed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The invention will be apparent by referring to the following
detailed description of a preferred embodiment with reference to
the accompanying drawings, wherein:
[0009] FIG. 1 is a schematic diagram of a unit of cell of the
typical 1-Transistor memory;
[0010] FIG. 2 is a schematic diagram of a 1-Transistor memory
structure of the invention;
[0011] FIG. 3 is a schematic diagram of hidden refresh circuit
portion of FIG. 2;
[0012] FIG. 4 is a diagram of the operating structure according to
the invention; and
[0013] FIG. 5 is a flowchart of FIG. 4 according to the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] FIG. 2 is a schematic diagram of a 1-Transistor memory
structure of the invention. In FIG. 2, the structure includes
memory arrays MATi to MATn, sense amplifier banks SABi to SABn,
sense amplifier selectors SAS, shared data latches SDLi to SDLn,
column selectors YS, and switches S.
[0015] As shown in FIG. 2, in the configuration, an operating unit
of memory includes a memory array MAT and a sense amplifier bank
SAB, which implements a pair of sense amplifier selectors SAS on
its two laterals, for example, MAT i, SAB i and two SASs i. The
selector SAS selects the collision solution path based on the cycle
signal ACCESS_MISS or ACCESS_HIT. If the signal ACCESS_MISS is
selected, the local input/output bus LIO is used, otherwise, if the
signal ACCESS_HIT is selected, the bitline is used. Moreover, two
operating units of memory are arranged in parallel and connected
with main input/output buses MIO, each having a switch S for
selecting the buses MIO or LIO to be used. A shared data latch SDL
is implemented with one to a plurality of operating units of memory
connected subsequently. For example, as shown in FIG. 2, the odd
and even memory arrays MATs located from MAT (i-1) to MAT n are
connected to SAB i and SAB n, respectively. A shared data latch is
normally implemented with respect to 8 memory sectors (arrays), but
this can be changed according to the actual environment in memory
implementation. Thus, the structure of FIG. 2 is completed.
[0016] FIG. 3 is a schematic diagram of the hidden refresh circuit
portion of FIG. 2. In FIG. 3, the hidden refresh circuit portion
includes part of the sense amplifier bank SAB i between memory
arrays MAT i and MAT i+1 and part of the shared data latch SDL i.
As shown in FIG. 3, the selector SAS i is formed of two AND gates
and two passgates PG. When signal MAT_SEL is logic 1, this MAT i is
selected for the memory data access. At this time, the cycle
signals ACCESS_HIT and ACCESS_MISS are used to determine if the
collision between the data access and refresh happened in this MAT
and further determine which data transmission path (bus) is used
according to the cycle signal. The signal ACCESS_HIT is indicative
that the collision happened in a data access cycle while the signal
ACCESS_MISS is indicative that the collision did not happen in a
data refresh cycle. As shown in FIGS. 2 and 3, if the collision
happened on the data access cycle, the access data signal amplified
by the sense amplifier bank SAB is sent to the respective data
latch SDL through the long bitline LNBL/LNBLB. Concurrently, the
data latch SDL outputs the access data signal through the main
input/output bus MIO and the respective local input/output bus LIOL
to complete the external access request. On the other hand, if the
collision happened on the data refresh cycle, the refresh data
signal amplified by the sense amplifier bank SAB is sent to the
respective data latch SDL through the long bitline LNBL/LNBLB.
Next, the data latch SDL is amplified in the sense amplifier bank
SAB and outputs the amplified access data signal through the main
input/output bus MIO. After completing the external access request,
the refresh data signal stored in the data latch SDL is restored to
the memory bank MAT through the original long bitline LNBL/LNBLB
and the original sense amplifier bank SAB to complete the refresh
action. For example, when the data signal MAT i has the collision
on the access cycle, the long bitline LNBL/LNBLB is enabled in
order to output the access data signal to the latch SDL i. When the
data signal in the array MAT i is refreshed in the bank SAB i, the
respective buses LIOLi and MIO of the latch SDL i are concurrently
enabled by the latch SDL i such that the access data signal stored
in the latch SDL i can be output through the two buses LIOLi and
MIO. Hence, the data access action and the data refresh action are
concurrently completed. When the data signal MAT i has the
collision on the refresh cycle, the long bitline LNBL/LNBLB is
enabled in order to output the refresh data signal to the latch SDL
i. The data signal in the array MAT i is amplified by the bank SAB
i and output through the bus MIO to complete the access action.
After the access action is completed, the long bitline LNBL/LNBLB
is enabled and the bus MIO is disabled. Thus, the refresh data
signal stored in the data latch SDL is restored to the memory bank
MAT through the enabled long bitline LNBL/LNBLB to complete the
refresh action.
[0017] FIG. 4 is a diagram of the operating structure according to
the invention. In FIG. 4, the operating structure includes a
command controller 41, a timer 42, a row address latch 43, an
address counter 441 a MAT address comparator 45, a multiplexer 46,
a row address decoder 47, a column address decoder 48 and a memory
array block 49. As shown in FIG. 4, when a collision appears, the
row address latch 43 receives an external row address and outputs
the MAT address EMAT having the external row address to the MAT
address comparator 45. The MAT address comparator 45 utilizes the
control signal CMD of the command controller 41 to compare the
address EMAT with the MAT address MATA come from the address
counter 44 according to the timer 42. Thus, the comparator 45
outputs the cycle signals ACCESS_HIT and ACCESS_MISS to determine
on which operating cycle the collision happens. At this point, the
latch 43 and the counter 44 input an internal row address IPA and a
row address RRA, respectively, to the multiplexer 46. The
multiplexer 46 controls the address decoding via the row address
decoder 47 and the column address decoder 48 and selects the memory
array block 49 (the structure as shown in FIG. 2) to perform hidden
refresh or access data function based on the decode. The
performance of hidden refresh or data access follows.
[0018] FIG. 5 is a flowchart of FIG. 4 according to the invention.
In FIG. 5, an operating method includes the following steps:
determining if the collision between data access and data refresh
is addressed in the same memory array (S1); determining the
currently operating mode if the collision happened in the same
memory array (S2); if on the data access cycle mode, concurrently
refreshing a data signal through a respective sense amplifier bank
(SAB) and accessing another data signal through a respective shared
data latch(SDL)(S3); if on the data refresh cycle mode, first
storing the data signal to be refreshed in the shared data latch
and then restoring the data signal to be refreshed to the original
memory array using the cycle-stealing technique after the data
access is completed(S4).
[0019] As shown in FIG. 5, the operating method is described with
reference to FIGS. 2, 3 and 4 as follows. First, in step S1,
determining if the collision between data access and data refresh
is addressed in the same memory array is performed with the
comparator by determining if EMAT=MATA as shown in FIG. 4. Then, in
step S2, if EMAT=MATA, the collision happened. At this time, the
comparator has to further determine which operating cycle mode is
on. That is, the cycle signals ACCESS_HIT and ACCESS_MISS output by
the comparator are used to determine the next processing, including
the bus path to be used to transmit the data to the data latch SDL.
The signal ACCESS_HIT is indicative that the collision happened in
a data access cycle while the signal ACCESS_MISS is indicative that
the collision did not happen in a data refresh cycle as shown in
FIGS. 2 and 3. Finally, in step S3, if the collision happened on
the data access cycle, the access data signal amplified by the
sense amplifier bank SAB is sent to the respective data latch SDL
through the long bitline LNBL/LNBLB. Concurrently, the data latch
SDL outputs the access data signal through the main input/output
bus MIO and the respective local input/output bus LIOL to complete
the external access request. On the other hand, in step S4, if the
collision happened on the data refresh cycle, the refresh data
signal amplified by the sense amplifier bank SAB is sent to the
respective data latch SDL through the long bitline LNBL/LNBLB.
Next, the data latch SDL is amplified in the sense amplifier bank
SAB and outputs the amplified access data signal through the main
input/output bus MIO. After the external access is completed, the
refresh data signal stored in the data latch SDL is restored to the
memory bank MAT through the original long bitline LNBL/LNBLB and
the original sense amplifier bank SAB to complete the refresh
action. The well-known cycle-stealing technique in the art, which
utilizes the switching time between the cycle modes to complete the
restored action, is used.
[0020] Although the invention has been described in its preferred
embodiment, it is not intended to limit the invention to the
precise embodiment disclosed herein. Those who are skilled in this
technology can still make various alterations and modifications
without departing from the scope and spirit of this invention.
Therefore, the scope of the invention shall be defined and
protected by the following claims and their equivalents.
* * * * *