U.S. patent application number 09/922786 was filed with the patent office on 2002-09-19 for semiconductor device and method of manufacturing the same.
This patent application is currently assigned to Fujitsu Limited. Invention is credited to Gamo, Yasuo, Takahashi, Koji.
Application Number | 20020132416 09/922786 |
Document ID | / |
Family ID | 18933492 |
Filed Date | 2002-09-19 |
United States Patent
Application |
20020132416 |
Kind Code |
A1 |
Gamo, Yasuo ; et
al. |
September 19, 2002 |
Semiconductor device and method of manufacturing the same
Abstract
To ensure sufficient electrical insulation between bit and word
lines and realize excellent charge holding characteristic by
suppressing undesirable bird's beak formation, a buried bit line
type flash memory includes bit lines formed by ion-implanting
impurities into a semiconductor substrate, said bit lines serving
also as sources and drains, and word lines crossing said bit lines
and serving also as gate electrodes. After the impurity ion
implantation for forming the bit lines and annealing for activating
the impurities, an ONO film having a three-layer structure of
silicon oxide film/silicon nitride film/silicon oxide film is
formed.
Inventors: |
Gamo, Yasuo; (Kawasaki,
JP) ; Takahashi, Koji; (Kawasaki, JP) |
Correspondence
Address: |
ARMSTRONG,WESTERMAN & HATTORI, LLP
1725 K STREET, NW.
SUITE 1000
WASHINGTON
DC
20006
US
|
Assignee: |
Fujitsu Limited
Kawasaki
JP
|
Family ID: |
18933492 |
Appl. No.: |
09/922786 |
Filed: |
August 7, 2001 |
Current U.S.
Class: |
438/216 ;
257/406; 257/411; 257/E21.268; 257/E21.269; 257/E21.679;
257/E27.103; 438/288 |
Current CPC
Class: |
H01L 21/28185 20130101;
H01L 21/3144 20130101; H01L 27/115 20130101; H01L 21/3145 20130101;
H01L 27/11568 20130101; H01L 29/518 20130101; H01L 21/28194
20130101; H01L 29/513 20130101 |
Class at
Publication: |
438/216 ;
257/406; 257/411; 438/288 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 16, 2001 |
JP |
2001-076585 |
Claims
What is claimed is:
1. A semiconductor device manufacturing method comprising: a first
step of introducing impurities into a surface layer in an active
region of a semiconductor substrate and annealing said
semiconductor substrate to form source and drain regions; after
said first step, a second step of forming a multilayer film so as
to cover said active region, said multilayer film being made up
from at least three layers, in which a first insulating film having
a charge trap function is sandwiched by second and third insulating
films from upper and lower sides of said first insulating film; and
a third step of depositing an electrode material on said multilayer
film and patterning said electrode material and said multilayer
film to form a gate electrode, said gate electrode being located
over said semiconductor substrate with said multilayer film being
interposed between them.
2. The method according to claim 1, wherein, in said third step,
said gate electrode is formed at the position between said source
and drain regions over said semiconductor substrate with said
multilayer film being interposed between said gate electrode and
said source and drain regions.
3. The method according to claim 1, wherein, in said first step,
after said impurities are introduced, a substance having an
accelerated oxidation suppressing function is subsequently
introduced into said active region, and then said semiconductor
substrate is annealed to form said source and drain regions.
4. The method according to claim 3, wherein said substance having
an accelerated oxidation suppressing function is one selected from
the group of nitrogen, carbon, and compounds containing nitrogen or
carbon.
5. The method according to claim 4, wherein, as said substance
having an accelerated oxidation suppressing function, nitrogen or
carbon ions are implanted into said active region.
6. The method according to claim 4, wherein said substance having
an accelerated oxidation suppressing function is one selected from
the group of NO.sub.2, NO, NH.sub.3, and C.sub.xH.sub.y (x and y
are appropriate numbers), and annealing is performed in an
atmosphere of said substance to dope said active region with said
substance.
7. The method according to claim 5, wherein said substance having
an accelerated oxidation suppressing function is ion-implanted
obliquely to a surface of said active region.
8. The method according to claim 1, wherein said first insulating
film having a charge trap function is a silicon nitride film.
9. A semiconductor device comprising: a semiconductor substrate;
source and drain regions formed in a surface layer of said
semiconductor substrate; a multilayer film formed on said
semiconductor substrate between said source and drain regions, said
multilayer film being made up from at least three layers, in which
a first insulating film having a charge trap function is sandwiched
by second and third insulating films from upper and lower sides of
said first insulating film; and a gate electrode formed on said
multilayer film, wherein said gate electrode extends between said
source and drain regions over said semiconductor substrate with
said multilayer film being interposed between said gate electrode
and said source and drain regions, and said source and drain
regions contain a substance having an accelerated oxidation
suppressing function, as well as impurities for conductivity.
10. The device according to claim 9, wherein said substance having
an accelerated oxidation suppressing function is one selected from
the group of nitrogen, carbon, and compounds containing nitrogen or
carbon.
11. The device according to claim 9, wherein said first insulating
film of said multilayer film is a capacitive insulating film, and
said semiconductor substrate and said gate electrode are
capacitively coupled with each other so that said device functions
as a semiconductor memory.
12. The device according to claim 9, wherein said second insulating
film as the lowermost layer of said multilayer film is formed
thicker at portions above said source and drain regions than at the
other portions.
13. The device according to claim 12, wherein the thickness of said
second insulating film above said source and drain regions falls
within the range of 30 to 50 nm.
14. A method of manufacturing a semiconductor device comprising: a
semiconductor substrate; source and drain regions formed in a
surface layer of said semiconductor substrate; a multilayer film
formed on said semiconductor substrate between said source and
drain regions, said multilayer film being made up from at least
three layers, in which a first insulating film having a charge trap
function is sandwiched by second and third insulating films from
upper and lower sides of said first insulating film; and a gate
electrode formed on said multilayer film, said method comprising
the steps of: introducing impurities into a surface layer in an
active region of said semiconductor substrate; annealing said
semiconductor substrate to form said source and drain regions; and
forming said multilayer film.
15. The method according to claim 14, wherein said gate electrode
is formed at the position between said source and drain regions
over said semiconductor substrate with said multilayer film being
interposed between said gate electrode and said source and drain
regions.
16. The method according to claim 14, wherein, after said
impurities are introduced, a substance having an accelerated
oxidation suppressing function is subsequently introduced into said
active region, and then said semiconductor substrate is annealed to
form said source and drain regions.
17. the method according to claim 16, wherein said substance having
an accelerated oxidation suppressing function is one selected from
the group of nitrogen, carbon, and compounds containing nitrogen or
carbon.
18. The method according to claim 17, wherein, as said substance
having an accelerated oxidation suppressing function, nitrogen or
carbon ions are implanted into said active region.
19. The method according to claim 17, wherein said substance having
an accelerated oxidation suppressing function is one selected from
the group of NO.sub.2, NO, NH.sub.3, and C.sub.xH.sub.y (x and y
are appropriate numbers), and annealing is performed in an
atmosphere of said substance to dope said active region with said
substance.
20. The method according to claim 18, wherein said substance having
an accelerated oxidation suppressing function is ion-implanted
obliquely to a surface of said active region.
21. The method according to claim 14, wherein said first insulating
film having a charge trap function is a silicon nitride film.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims priority of
Japanese Patent Application No. 2001-076585, filed on Mar. 16,
2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
[0002] The present invention relates to semiconductor devices
provided between semiconductor substrates and gate electrodes with
multilayer films each including an insulating film having a charge
trap function and sandwiched by upper and lower insulating films,
and methods of manufacturing the same.
DESCRIPTION OF THE RELATED ART
[0003] Conventionally, as a nonvolatile memory which can hold its
stored data even after the power is cut off, a semiconductor memory
has been devised, which includes an impurity diffusion layer formed
in a semiconductor substrate to serve as bit lines (buried bit
lines), and word lines formed over the semiconductor substrate with
a capacitive insulating film being interposed between them, so as
to run perpendicularly to the bit lines. The structure can be
simpler than a two-layer electrode structure such as an EEPROM and
is expected to cope with further size reduction and micropatterning
of elements.
[0004] In this type of semiconductor memories, the capacitive
insulating film preferably has a multilayer structure made up from
at least three layers, in which an insulating film having a charge
trap function, such as a silicon nitride film, is sandwiched by
upper and lower insulating films, such as silicon oxide films. As a
typical example of the multilayer film known is a structure of
silicon oxide film/silicon nitride film/silicon oxide film, i.e., a
so-called ONO film, in which a silicon nitride film having a charge
trap function is sandwiched by upper and lower silicon oxide
films.
[0005] In this type of semiconductor memories, since the word lines
cross the buried bit lines, which serve as sources and drains, with
the multilayer film being interposed between them, sufficient
electrical insulation must be ensured between the bit lines and the
word lines. Conventional methods of manufacturing semiconductor
memories having buried bit line structures will be described below
from the above viewpoint.
[0006] (Prior Art 1)
[0007] In this prior art, an ONO film is entirely used as an
electrical insulating film between bit and word lines.
[0008] More specifically, as shown in FIG. 14A, a silicon oxide
film 111, a silicon nitride film 112, and a silicon oxide film 113
are sequentially stacked in this order in an active region on,
e.g., a p-type silicon semiconductor substrate 101 to form an ONO
film 102. After a resist pattern 103 is formed on the ONO film 102,
n-type impurities such as arsenic are ion-implanted into a surface
layer of the semiconductor substrate 101 using the resist pattern
103 as a mask under such conditions that the ions can pass through
the ONO film 102.
[0009] The resist pattern 103 is then removed through an ashing
process or the like, and the semiconductor substrate 101 is
annealed, thereby forming buried bit lines 104 that serve also as
sources and drains.
[0010] As shown in FIG. 14B, an electrode material is deposited
onto the ONO film 102 and patterned to form word lines 105 that
cross the buried bit lines 104 with the ONO film 102 being
interposed between them. The word lines 105 serve also as gate
electrodes.
[0011] After that, post-processes such as formation of an
insulating interlayer, contact holes, and various electrical
interconnection layers are executed, thereby completing a
semiconductor memory.
[0012] (Prior Art 2)
[0013] In this prior art, only the lowermost silicon oxide film of
an ONO film on bit lines is made thicker to ensure electrical
insulation.
[0014] More specifically, as shown in FIG. 15A, an ONO film 102 is
formed in an active region on, e.g., a p-type silicon semiconductor
substrate 101. After a resist pattern 103 is formed on the ONO film
102, the upper silicon oxide film 113 and the silicon nitride film
112 of the ONO film 102 are patterned using the resist pattern 103
as a mask, thereby leaving only the lowermost silicon oxide film
111 as it is.
[0015] Impurities of n-type such as arsenic are then ion-implanted
into a surface layer of the semiconductor substrate 101 using the
resist pattern 103 as a mask under such conditions that the ions
can pass through the lowermost silicon oxide film 111.
[0016] The resist pattern 103 is then removed, and the
semiconductor substrate 101 is annealed in an oxidative atmosphere,
thereby forming buried bit lines 104 that serve also as sources and
drains. At this time, as shown in FIG. 15B, accelerated oxidation
occurs at portions of the silicon oxide film 111 above the bit
lines 104 through the annealing process due to the presence of
arsenic ions in the semiconductor substrate 101. The silicon oxide
film 111 thereby has a thickness of about 40 to 60 nm at those
portions.
[0017] As shown in FIG. 15C, an electrode material is then
deposited and patterned to form word lines 105 that cross the
buried bit lines 104 with the silicon oxide film 111 being
interposed between them. The word lines serve also as gate
electrodes.
[0018] After that, post-processes such as formation of an
insulating interlayer, contact holes, and various electrical
interconnection layers are executed, thereby completing a
semiconductor memory.
[0019] (Prior Art 3)
[0020] In this prior art, to ensure electrical insulation, bit
lines are formed with a thick silicon oxide film provided.
thereon.
[0021] More specifically, as shown in FIG. 16A, a thin sacrificial
oxide film 106 is formed in an active region on, e.g., a p-type
silicon semiconductor substrate 101. After a resist pattern 103 is
formed on the sacrificial oxide film 106, n-type impurities such as
arsenic are ion-implanted into a surface layer of the semiconductor
substrate 101 using the resist pattern 103 as a mask under such
conditions that the ions can pass through the sacrificial oxide
film 106.
[0022] As shown in FIG. 16B, the resist pattern 103 is then
removed, and the semiconductor substrate 101 is annealed in an
oxidative atmosphere, thereby forming buried bit lines 104 that
serve also as sources and drains. At this time, accelerated
oxidation occurs at portions of the sacrificial oxide film 106
above the bit lines 104 through the annealing process due to the
presence of arsenic ions in the semiconductor substrate 101. The
sacrificial oxide film 106 thereby has a thickness of about 40 to
60 nm at those portions.
[0023] As shown in FIG. 16C, after the portions of the sacrificial
oxide film 106 on the channel region is removed, an ONO film 102 is
formed on the active region. At this time, the thickness of the
sacrificial oxide film 106 above the bit lines 104 increases to
about 50 to 90 nm because of the influence of the annealing process
in forming the ONO film 102.
[0024] As shown in FIG. 16D, an electrode material is then
deposited and patterned to form word lines 105 that cross the
buried bit lines 104 with the sacrificial oxide film 106 being
interposed between them. The word lines serve also as gate
electrodes.
[0025] After that, post-processes such as formation of an
insulating interlayer, contact holes, and various electrical
interconnection layers are executed, thereby completing a
semiconductor memory.
[0026] By any of the above-described manufacturing methods, a
semiconductor memory having a buried bit line structure, which can
hold electrical insulation between the bit and word lines, may be
manufactured. However, the above manufacturing methods have the
following problems.
[0027] In the manufacturing method described in the prior art 1,
since electrical insulation between the bit lines 104 and the word
lines 105 are ensured only by the ONO film 102, the breakdown
voltage of the ONO film 102 must be made high. In this
manufacturing method, however, since arsenic ions are ion-implanted
through the ONO film 102 to form the bit lines 104, the ONO film
102 may be inevitably damaged. In addition, since the uppermost
silicon oxide film 113 of the ONO film 102 may be partially or
fully etched off through a post-process, it is hard to ensure a
sufficient breakdown voltage of the ONO film 102.
[0028] In the manufacturing method described in the prior art 2, in
thickening the silicon oxide film 111 above the bit lines 104 by
annealing, only the silicon oxide film 111 is present above the bit
lines 104. For this reason, bird's beaks may be formed on both
sides of each channel region due to the wraparound by oxygen. In
addition, since the peripheral circuit region is normally formed
simultaneously with formation of the memory cell region, the
silicon oxide film 111 above the bit lines 104 may become thicker
(about 100 to 150 nm) through several times of annealing processes
in forming the gate insulating films of transistors in the
peripheral circuit region, and accordingly, larger bird's beaks may
form.
[0029] In the manufacturing method described in the prior art 3,
due to accelerated oxidation through each annealing process for the
impurity diffusion to form the bit lines 104 and the formation of
the ONO film 102, the sacrificial oxide film 106 above the bit
lines 104 may increase its thickness, and large bird's beaks may
also grow.
[0030] As described above, in manufacturing a semiconductor memory
having a buried bit line structure, it is difficult to ensure
electrical insulation between the bit lines and the word lines, or
even when electrical insulation can be ensured, it may cause bird's
beak formation and considerably degrades the charge holding
characteristic. These are serious problems.
SUMMARY OF THE INVENTION
[0031] An object of the present invention is to provide a
semiconductor device that can sufficiently ensure electrical
insulation between bit lines and word lines and realize an
excellent charge holding characteristic by suppressing undesirable
bird's beak formation, and a method of manufacturing the
semiconductor device, in particular, to provide a semiconductor
memory having a buried bit line structure.
[0032] The present invention provides a semiconductor device in
which source and drain regions are formed in a surface layer of a
semiconductor substrate, and a gate electrode is formed between the
source and drain regions over the semiconductor substrate with a
multilayer film being interposed between the gate electrode and the
semiconductor substrate. The multilayer film is made up from at
least three layers, in which a first insulating film having a
charge trap function is sandwiched by second and third insulating
films from the upper and lower sides of the first insulating film.
The present invention also provides a method of manufacturing the
semiconductor device.
[0033] According to the present invention, there is provided a
semiconductor device manufacturing method comprising a first step
of introducing impurities into a surface layer in an active region
of a semiconductor substrate and annealing the semiconductor
substrate to form source and drain regions, a second step of, after
the first step, forming a multilayer film made up from at least
three layers, in which a first insulating film having a charge trap
function is sandwiched by second and third insulating films from
the upper and lower sides of the first insulating film, so as to
cover the active region, and a third step of depositing an
electrode material on the multilayer film and patterning the
electrode material and the multilayer film to form a gate electrode
over the semiconductor substrate with the multilayer film being
interposed between the gate electrode and the semiconductor
substrate.
[0034] Preferably in the first step, after the introduction of the
impurities, a substance having an accelerated oxidation suppressing
function is introduced into the active region, and the
semiconductor substrate is annealed to form the source and drain
regions.
[0035] In introducing the substance having the accelerated
oxidation suppressing function into the active region, the
substance is preferably ion-implanted obliquely to the surface of
the active region.
[0036] In the semiconductor device of the present invention, the
gate electrode is formed over the semiconductor substrate with the
multilayer film being interposed between them, to cross the source
and drain regions, and the source and drain regions contain the
substance having an accelerated oxidation suppressing function, as
well as the impurities.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] FIGS. 1A to 1C are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to the first embodiment of the present invention;
[0038] FIGS. 2A and 2B are schematic sectional views illustrating
manufacturing steps of the buried bit line type flash memory
according to the first embodiment, subsequent to FIG. 1C;
[0039] FIG. 3 is a schematic plan view showing a structure in which
bit lines and word lines perpendicularly cross each other;
[0040] FIG. 4 is a schematic sectional view illustrating a data
write operation in the flash memory according to the first
embodiment;
[0041] FIGS. 5A and 5B are schematic sectional views illustrating a
data erase operation in the flash memory according to the first
embodiment;
[0042] FIGS. 6A and 6B are schematic sectional views illustrating a
data read operation in the flash memory according to the first
embodiment;
[0043] FIG. 7 is a graph showing the relation between the leakage
current and the voltage between the source/drain and the gate
electrode in the flash memory according to each of the first
embodiment and comparative examples;
[0044] FIG. 8 is a graph showing the relation between the charge
holding characteristic and the number of times of data erase/write
operations in the flash memory according to each of the first
embodiment and the comparative examples;
[0045] FIGS. 9A to 9C are graphs each showing the relation between
the threshold voltage (V.sub.th) and the number of times of data
erase/write operations in the flash memory according to the first
embodiment and the comparative examples;
[0046] FIGS. 10A to 10C are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to the second embodiment of the present invention;
[0047] FIGS. 11A and 11B are schematic sectional views illustrating
manufacturing steps of the buried bit line type flash memory
according to the second embodiment, subsequent to FIG. 10C;
[0048] FIGS. 12A to 12C are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to the third embodiment of the present invention;
[0049] FIGS. 13A and 13B are schematic sectional views illustrating
manufacturing steps of the buried bit line type flash memory
according to the third embodiment, subsequent to FIG. 12C;
[0050] FIGS. 14A and 14B are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to prior art 1;
[0051] FIGS. 15A to 15C are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to prior art 2; and
[0052] FIGS. 16A to 16D are schematic sectional views illustrating
manufacturing steps of a buried bit line type flash memory
according to prior art 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0053] Hereinafter, preferred embodiments of the present invention
will be described in detail with reference to drawings.
FIRST EMBODIMENT
[0054] In this embodiment, as a semiconductor device according to
the present invention, a so-called buried bit line type flash
memory will be described. For convenience, the structure of the
flash memory will be described through the manufacturing
process.
[0055] FIGS. 1A to 1C and 2A and 2B are schematic sectional views
illustrating manufacturing steps of the buried bit line type flash
memory according to this first embodiment in order.
[0056] To manufacture this flash memory, first, as shown in FIG.
1A, a p-type silicon semiconductor substrate 1 is prepared. Field
oxide films (not shown) are formed in the element isolation regions
on the surface of the semiconductor substrate 1 through, e.g., a
LOCOS process for element isolation, thereby defining each active
region 2 within a memory cell region and each active region (not
shown) within a peripheral circuit region where a CMOS transistor
and the like are to be formed.
[0057] Instead of using such a LOCOS process, trenches (not shown)
may be formed in the element isolation regions of the semiconductor
substrate 1, and the trenches may be filled with an insulating
material to define active regions.
[0058] Annealing is then performed in an oxidative atmosphere at
900.degree. C. to 1,100.degree. C. to form an about 2 to 50
nm-thick sacrificial oxide film 3 on the active region 2. After
that, a resist is applied onto the sacrificial oxide film 3 and
processed by photolithography to form a resist pattern 4 with
band-shape portions separated at predetermined intervals.
[0059] As shown in FIG. 1B, using the resist pattern 4 as a mask,
n-type impurities such as arsenic (As) are ion-implanted into a
surface layer of the semiconductor substrate 1 under such
conditions that the ions can pass through the sacrificial oxide
film 3, in this example, at an acceleration energy of 50 keV and a
dose of 2 to 3.times.10.sup.15/cm.sup- .2. After the resist pattern
4 is removed by ashing or the like, annealing is performed in a
nitrogen atmosphere (or an inert gas atmosphere) at 1,050.degree.
C. for 10 min to activate the implanted arsenic ions, thereby
forming band-shape bit lines 5. These bit lines 5 serves also as
the sources and drains of the flash memory.
[0060] As shown in FIG. 1C, an ONO film 6 having a three-layer
structure of silicon oxide film/silicon nitride film/silicon oxide
film is formed on the semiconductor substrate 1.
[0061] More specifically, first, a silicon oxide film 21 having a
thickness of about 7 to 8 nm is formed on the semiconductor
substrate 1 by thermal oxidation. At this time, the portions of the
silicon oxide film 21 above the bit lines 5 is acceleratingly
oxidized through the annealing process due to the presence of
arsenic ions in the bit lines 5, thereby increasing the thickness
to about 30 to 50 nm.
[0062] A silicon nitride film 22 having a thickness of about 5 nm
is then formed on the silicon oxide film 21 through a CVD process
at 600.degree. C. to 800.degree. C. A silicon oxide film 23 having
a thickness of about 10 nm is then formed on the silicon nitride
film 22 through a CVD process. The ONO film 6 is formed thus.
[0063] The active region 2 of the memory cell region is masked by a
resist, and the portions of the ONO film 6 present on the active
regions of the peripheral circuit region are all removed using
CF.sub.4+CHF.sub.3/O.sub.2 gas or the like. After the resist on the
active region 2 is removed, a gate insulating film (not shown) is
formed on the active regions of the peripheral circuit region by
thermal oxidation. At this time, since the bit lines 5 are covered
with the ONO film 6, the influence of the annealing process in the
formation of the gate insulating film is little. Any further
accelerated oxidation of the silicon oxide film 21 at the portions
above the bit lines 5 is suppressed, and an increase in thickness
is hardly observed.
[0064] An amorphous silicon (DASi) film (not shown) doped with
n-type impurities, in this example, phosphorus (P), at a
concentration of 0.2 to 3.times.10.sup.21/cm.sup.3 and having a
thickness of about 100 to 150 nm is formed in each active region of
the memory cell region and the peripheral circuit region by
CVD.
[0065] As shown in FIGS. 2A and 3 (plan view), the DASi film is
then annealed to form a polysilicon film, and the polysilicon film
and the ONO film 6 are patterned by photolithography and subsequent
dry etching, thereby forming band-shap word lines 7 that
perpendicularly cross the bit lines 5 with the ONO film 6 being
interposed between them and serve also as gate electrodes. At this
time, a tungsten silicide (WSi) film may be formed on the
polysilicon film to form word lines having a polycide structure and
thereby decrease the resistance of electrical interconnections.
[0066] As shown in FIG. 2B, a high-temperature CVD oxide film (HTO
film) 8 and a BPSG film 9 are sequentially formed in this order to
cover the word lines 7. After contact holes (not shown) reaching
the word lines 7 and the like are formed, an aluminum alloy film is
formed by sputtering on the BPSG film 9, which has been planarized
by a reflow process, so as to fill the contact holes. The aluminum
alloy film is patterned by photolithography and subsequent dry
etching to form upper interconnecting lines 11.
[0067] After that, a protective film 12 is formed to cover the
upper interconnecting lines 11, and formation processes for an
insulating interlayer, contact holes (via holes), and
interconnecting lines are executed, thereby completing a buried bit
line type flash memory.
[0068] To write data in this flash memory, electrons are injected
into the drain terminal with channel hot electrons (CHEs) or drain
avalanche hot carriers (DAHCs), as shown in FIG. 4. In this case,
electrons can be injected into the source terminal by exchanging
the source and drain voltages with each other. That is, write
operations (electron injection) to two portions in one memory cell
can be executed.
[0069] To erase data in this flash memory, as shown in FIGS. 5A and
5B, charges are removed from the ONO film 6 by Fowler-Nordheim (FN)
tunneling, or holes generated in the tunnel between bands and hot
holes generated due to the electric field between the drain and the
substrate are injected into the ONO film 6. The illustrated example
shows the latter case by the tunnel between the bands. In this
example of erase, electrons are injected into the drain terminal.
When an identical voltage is applied also to the source, a flash
erase can be executed for the source terminal simultaneously with
the drain terminal.
[0070] A method of reading out data from this flash memory will be
described with reference to FIGS. 6A and 6B. While negative charges
are present in the silicon nitride film 22, the channel is cut off,
and no current flows between the source and the drain (FIG. 6A).
This state is defined as data "0". While no electrons are present
in the silicon nitride film 22, the channel is connected, and a
current flows (FIG. 6B). This state is defined as data "1".
EXPERIMENTAL EXAMPLES
[0071] Experimental results obtained by examining various
characteristics of the flash memory according to this first
embodiment in comparison with the above-described prior arts will
be described. FIGS. 7, 8, and 9A to 9C show the experimental
results, in which the above-described prior arts 1 and 2 are
respectively referred to as prior arts {circle over (1)} and
{circle over (2)} as comparative examples, and the first embodiment
of the present invention is referred to as invention {circle over
(1)}.
Experimental Example 1
[0072] The relation between the leakage current and the voltage
between the source/drain and the gate electrode in the flash memory
was examined. The experimental result is shown in FIG. 7. In FIG.
7, the leakage current is logarithmically plotted.
[0073] The breakdown voltage of the ONO film had to be about 15 V.
As shown in FIG. 7, in the present invention {circle over (1)}, the
ensured breakdown voltage was almost the same as that in prior art
{circle over (2)} which had the thickest silicon oxide film above
the bit lines (sources and drains).
Experimental Example 2
[0074] The relation between the charge holding characteristic and
the number of times of data erase/write operations in the flash
memory was examined. The experimental result is shown in FIG. 8. In
FIG. 8, the charge holding characteristic is plotted as relative
values.
[0075] After the erase and write process (cycle) was repeated, and
annealing was performed at 150.degree. C. for two hours, the charge
holding characteristic was examined. As shown in FIG. 8, in the
present invention {circle over (0)}, the obtained charge holding
characteristic was almost the same as that in prior art {circle
over (0)} which had the thinnest silicon oxide film above the bit
lines (sources and drains), and so the smallest bird's beak.
Experimental Example 3
[0076] The relation between the threshold voltage (V.sub.th) and
the number of times of data erase/write operations in the flash
memory was examined. The experimental results are shown in FIGS. 9A
to 9C.
[0077] The write conditions were set to Vd=5.9 V, Vg=9.5 V, and
write time=3 .mu.s, and the erase conditions were set to Vd=7.0 V,
Vg=-3.0 V, and erase time=10 ms. As shown in FIGS. 9A to 9C, no
difference in erase/write speed was observed between the present
invention {circle over (1)} and prior arts {circle over (1)} and
{circle over (2)}. On the basis of this experimental result, the
cycle in Experimental Example 2 was done under the same conditions
as those described above.
[0078] As described above, in this embodiment, the ONO film 6 is
formed after the impurities (arsenic) in the bit lines 5 are
activated. At the time of formation of the ONO film 6, the silicon
oxide film 21 as a component of the ONO film 6 is formed thick only
above the bit lines 5 by accelerated oxidation, so that sufficient
electrical insulation is ensured between the bit lines 5 and the
word lines 7. In this case, in various annealing processes
(formation of the gate insulating film in the peripheral circuit
region and the like) after formation of the ONO film 6, since the
thick portions of the silicon oxide film 21 above the bit lines 5
are covered with the other components (the silicon nitride film 22
and the silicon oxide film 23) of the ONO film 6, the thick
portions of the silicon oxide film 21 are not greatly
acceleratingly oxidized, and the bird's beaks can be suppressed to
a negligible level.
[0079] That is, in this embodiment, throughout the process until
the completion of the flash memory, the thickness of the ONO film 6
above the bit lines 5 is kept within an optimum range in which
sufficient electrical insulation is ensured between the bit lines 5
and the word lines 7 and no bird's beak that may degrade the charge
holding characteristic is formed. Hence, a very reliable flash
memory with improved transistor characteristics can be
implemented.
SECOND EMBODIMENT
[0080] In this second embodiment, a so-called buried bit line type
flash memory will be described, like the first embodiment, though
this second embodiment differs from the first embodiment in the bit
line formation process. The components of the flash memory
according to this second embodiment corresponding to those in the
first embodiment are denoted by the same reference numerals as
those in the first embodiment.
[0081] FIGS. 10A to 10C and 11A and 11B are schematic sectional
views illustrating manufacturing steps of the buried bit line type
flash memory according to this second embodiment in order.
[0082] To manufacture this flash memory, first, as shown in FIG.
10A, a p-type silicon semiconductor substrate 1 is prepared. Field
oxide films (not shown) are formed in the element isolation regions
on the surface of the semiconductor substrate 1 through, e.g., a
LOCOS process for element isolation, thereby defining each active
region 2 within a memory cell region and each active region (not
shown) within a peripheral circuit region where a CMOS transistor
and the like are to be formed.
[0083] Instead of using such a LOCOS process, trenches (not shown)
may be formed in the element isolation regions of the semiconductor
substrate 1, and the trenches may be filled with an insulating
material to define active regions.
[0084] Annealing is then performed in an oxidative atmosphere at
900.degree. C. to 1,100.degree. C. to form an about 2 to 50
nm-thick sacrificial oxide film 3 on the active region 2. After
that, a resist is applied onto the sacrificial oxide film 3 and
processed by photolithography to form a resist pattern 4 with
band-shape portions separated at predetermined intervals.
[0085] As shown in FIG. 10B, using the resist pattern 4 as a mask,
n-type impurities such as arsenic (As) are ion-implanted into a
surface layer of the semiconductor substrate 1 under such
conditions that the ions can pass through the sacrificial oxide
film 3, in this example, at an acceleration energy of 50 keV and a
dose of 2 to 3.times.10.sup.15/cm.sup- .2. Subsequently, a
substance having an accelerated oxidation suppressing function, in
this example, nitrogen ions are implanted at an acceleration energy
of 2 to 10 keV and a dose of 0.5 to 4.times.10.sup.15/cm.sup.2.
[0086] The substance having the accelerated oxidation suppressing
function can be one selected from nitrogen, carbon, and compounds
containing nitrogen or carbon. When annealing is performed in the
presence of these impurities, the impurities may concentrate in a
surface layer of the semiconductor substrate 1 to form SiN or SiC
and thereby suppress the diffusion of oxygen atoms into the
semiconductor substrate 1. Hence, carbon may suitably be
ion-implanted instead of nitrogen. In addition, the introducing
method of such a substance is not limited to the ion implantation
method. For example, annealing may be performed in an atmosphere of
such a substance to dope the semiconductor substrate 1 with the
substance. In this case, the substance having the accelerated
oxidation suppressing function is preferably selected from
NO.sub.2, NO, NH.sub.3, and C.sub.xH.sub.y (x and y are appropriate
numbers) due to the above-described reason for accelerated
oxidation suppression.
[0087] After the resist pattern 4 is removed by ashing or the like,
annealing is performed in a nitrogen atmosphere (or an inert gas
atmosphere) at 1,050.degree. C. for 10 min to activate the
implanted arsenic ions, thereby forming band-shape bit lines 5.
These bit lines 5 serves also as the sources and drains of the
flash memory.
[0088] As shown in FIG. 10C, an ONO film 6 having a three-layer
structure of silicon oxide film/silicon nitride film/silicon oxide
film is formed on the semiconductor substrate 1.
[0089] More specifically, first, a silicon oxide film 21 having a
thickness of about 7 to 8 nm is formed on the semiconductor
substrate 1 by thermal oxidation. At this time, the portions of the
silicon oxide film 21 above the bit lines 5 is acceleratingly
oxidized through the annealing process due to the presence of
arsenic ions in the bit lines 5, thereby increasing the thickness
to about 30 to 50 nm. In this case, however, the accelerated
oxidation suppressing function of the implanted nitrogen ions
further suppresses the increase in thickness of the silicon oxide
film 21 in comparison with the first embodiment in which no
nitrogen ion implantation is performed.
[0090] A silicon nitride film 22 having a thickness of about 5 nm
is then formed on the silicon oxide film 21 through a CVD process
at 600.degree. C. to 800.degree. C. A silicon oxide film 23 having
a thickness of about 10 nm is then formed on the silicon nitride
film 22 through a CVD process. The ONO film 6 is formed thus.
[0091] The active region 2 of the memory cell region is masked by a
resist, and the portions of the ONO film 6 present on the active
regions of the peripheral circuit region are all removed using
CF.sub.4+CHF.sub.3/O.sub.2 gas or the like. After the resist on the
active region 2 is removed, a gate insulating film (not shown) is
formed on the active regions of the peripheral circuit region by
thermal oxidation. At this time, since the bit lines 5 are covered
with the ONO film 6, the influence of the annealing process in the
formation of the gate insulating film is little. Any further
accelerated oxidation of the silicon oxide film 21 at the portions
above the bit lines 5 is suppressed, and an increase in thickness
is hardly observed.
[0092] An amorphous silicon (DASi) film (not shown) doped with
n-type impurities, in this example, phosphorus (P), at a
concentration of 0.2 to 3.times.10.sup.21/cm.sup.3 and having a
thickness of about 100 to 150 nm is formed in each active region of
the memory cell region and the peripheral circuit region by
CVD.
[0093] As shown in FIG. 11A, the DASi film is then annealed to form
a polysilicon film, and the polysilicon film and the ONO film 6 are
patterned by photolithography and subsequent dry etching, thereby
forming band-shape word lines 7 that perpendicularly cross the bit
lines 5 with the ONO film 6 being interposed between them and serve
also as gate electrodes. At this time, a tungsten silicide (WSi)
film may be formed on the polysilicon film to form word lines
having a polycide structure and thereby decrease the resistance of
electrical interconnections.
[0094] As shown in FIG. 11B, a high-temperature CVD oxide film (HTO
film) 8 and a BPSG film 9 are sequentially formed in this order to
cover the word lines 7. After contact holes (not shown) reaching
the word lines 7 and the like are formed, an aluminum alloy film is
formed by sputtering on the BPSG film 9, which has been planarized
by a reflow process, so as to fill the contact holes. The aluminum
alloy film is patterned by photolithography and subsequent dry
etching to form upper interconnecting lines 11.
[0095] After that, a protective film 12 is formed to cover the
upper interconnecting lines 11, and formation processes for an
insulating interlayer, contact holes (via holes), and
interconnecting lines are executed, thereby completing a buried bit
line type flash memory.
[0096] As described above, in this embodiment, the ONO film 6 is
formed after the impurities (arsenic) in the bit lines 5 are
activated, and nitrogen (carbon) having the accelerated oxidation
suppressing function is ion-implanted. At the time of formation of
the ONO film 6, the silicon oxide film 21 as a component of the ONO
film 6 is formed thick only above the bit lines 5 by accelerated
oxidation, so that sufficient electrical insulation is ensured
between the bit lines 5 and the word lines 7. In this case, in
various annealing processes (formation of the gate insulating film
in the peripheral circuit region and the like) after formation of
the ONO film 6, since the thick portions of the silicon oxide film
21 above the bit lines 5 are covered with the other components (the
silicon nitride film 22 and the silicon oxide film 23) of the ONO
film 6, in addition, due to the accelerated oxidation suppressing
function of nitrogen (carbon), the thick portions of the silicon
oxide film 21 are not greatly acceleratingly oxidized, and bird's
beak formation can be suppressed to a negligible level.
[0097] That is, in this embodiment, throughout the processe until
the completion of the flash memory, the thickness of the ONO film 6
above the bit lines 5 is kept within an optimum range in which
sufficient electrical insulation is ensured between the bit lines 5
and the word lines 7 and no bird's beak that may degrade the charge
holding characteristic is formed. Additionally, the thickness can
be controlled thinner by the accelerated oxidation suppressing
function of nitrogen (carbon). Hence, a very reliable flash memory
with improved transistor characteristics can be implemented.
Third Embodiment
[0098] In this third embodiment, a so-called buried bit line type
flash memory will be described, like the first embodiment, though
this third embodiment differs from the first embodiment in the bit
line formation process. The components of the flash memory
according to this third embodiment corresponding to those in the
first or second embodiment are denoted by the same reference
numerals as those in the first or second embodiment.
[0099] FIGS. 12A to 12C and 13A and 13B are schematic sectional
views illustrating manufacturing steps of the buried bit line type
flash memory according to this third embodiment in order.
[0100] To manufacture this flash memory, first, as shown in FIG.
12A, a p-type silicon semiconductor substrate 1 is prepared. Field
oxide films (not shown) are formed in the element isolation regions
on the surface of the semiconductor substrate 1 through, e.g., a
LOCOS process for element isolation, thereby defining each active
region 2 within a memory cell region and each active region (not
shown) within a peripheral circuit region where a CMOS transistor
and the like are to be formed.
[0101] Instead of using such a LOCOS process, trenches (not shown)
may be formed in the element isolation regions of the semiconductor
substrate 1, and the trenches may be filled with an insulating
material to define active regions.
[0102] Annealing is then performed in an oxidative atmosphere at
900.degree. C. to 1,100.degree. C. to form an about 2 to 50
nm-thick sacrificial oxide film 3 on the active region 2. After
that, a resist is applied onto the sacrificial oxide film 3 and
processed by photolithography to form a resist pattern 4 with
band-shape portions separated at predetermined intervals.
[0103] As shown in FIG. 12B, using the resist pattern 4 as a mask,
n-type impurities such as arsenic (As) are ion-implanted into a
surface layer of the semiconductor substrate 1 under such
conditions that the ions can pass through the sacrificial oxide
film 3, in this example, at an acceleration energy of 50 keV and a
dose of 2 to 3.times.10.sup.15/cm.sup- .2.
[0104] Subsequently, a substance having an accelerated oxidation
suppressing function, in this example, nitrogen ions are
ion-implanted obliquely to the surface of the semiconductor
substrate 1 at an acceleration energy of 2 to 30 keV and a dose of
1 to 5.times.10.sup.15/cm.sup.2. When x represents the distance
between neighboring resist pattern portions 4 (the width of each
bit line 5), and y represents the thickness of the resist pattern
4, using an angle .theta. that generally satisfies;
tan .theta.=x/y,
[0105] the angle .THETA. for implantation of nitrogen ions
preferably falls within the range of;
.theta.-10.degree..ltoreq..THETA..ltoreq..theta.+10.degree..
[0106] The substance having the accelerated oxidation suppressing
function can be one selected from nitrogen, carbon, and compounds
containing nitrogen or carbon. When annealing is performed in the
presence of these impurities, the impurities may concentrate in a
surface layer of the semiconductor substrate 1 to form SiN or SiC
and thereby suppress the diffusion of oxygen atoms into the
semiconductor substrate 1. Hence, carbon may suitably be
ion-implanted instead of nitrogen. In addition, the introducing
method of such a substance is not limited to the ion implantation
method. For example, annealing may be performed in an atmosphere of
such a substance to dope the semiconductor substrate 1 with the
substance. In this case, the substance having the accelerated
oxidation suppressing function is preferably selected from
NO.sub.2, NO, NH.sub.3, and C.sub.xH.sub.y (x and y are appropriate
numbers) due to the above-described reason for accelerated
oxidation suppression.
[0107] After the resist pattern 4 is removed by ashing or the like,
annealing is performed in a nitrogen atmosphere (or an inert gas
atmosphere) at 1,050.degree. C. for 10 min to activate the
implanted arsenic ions, thereby forming band-shape bit lines 5.
These bit lines 5 serves also as the sources and drains of the
flash memory.
[0108] As shown in FIG. 12C, an ONO film 6 having a three-layer
structure of silicon oxide film/silicon nitride film/silicon oxide
film is formed on the semiconductor substrate 1.
[0109] More specifically, first, a silicon oxide film 21 having a
thickness of about 7 to 8 nm is formed on the semiconductor
substrate 1 by thermal oxidation. At this time, the portions of the
silicon oxide film 21 above the bit lines 5 is acceleratingly
oxidized through the annealing process due to the presence of
arsenic ions in the bit lines 5, thereby increasing the thickness
to about 30 to 50 nm. In this case, however, the accelerated
oxidation suppressing function of the implanted nitrogen ions
further suppresses the increase in thickness of the silicon oxide
film 21 in comparison with the first embodiment in which no
nitrogen ion implantation is performed.
[0110] A silicon nitride film 22 having a thickness of about 5 nm
is then formed on the silicon oxide film 21 through a CVD process
at 600.degree. C. to 800.degree. C. A silicon oxide film 23 having
a thickness of about 10 nm is then formed on the silicon nitride
film 22 through a CVD process. The ONO film 6 is formed thus.
[0111] The active region 2 of the memory cell region is masked by a
resist, and the portions of the ONO film 6 present on the active
regions of the peripheral circuit region are all removed using
CF.sub.4+CHF.sub.3 /O.sub.2 gas or the like. After the resist on
the active region 2 is removed, a gate insulating film (not shown)
is formed on the active regions of the peripheral circuit region by
thermal oxidation. At this time, since the bit lines 5 are covered
with the ONO film 6, the influence of the annealing process in the
formation of the gate insulating film is little. Any further
accelerated oxidation of the silicon oxide film 21 at the portions
above the bit lines 5 is suppressed, and an increase in thickness
is hardly observed.
[0112] An amorphous silicon (DASi) film (not shown) doped with
n-type impurities, in this example, phosphorus (P), at a
concentration of 0.2 to 3.times.10.sup.21/cm.sup.3 and having a
thickness of about 100 to 150 nm is formed in each active region of
the memory cell region and the peripheral circuit region by
CVD.
[0113] As shown in FIG. 13A, the DASi film is then annealed to form
a polysilicon film, and the polysilicon film and the ONO film 6 are
patterned by photolithography and subsequent dry etching, thereby
forming band-shape word lines 7 that perpendicularly cross the bit
lines 5 with the ONO film 6 being interposed between them and serve
also as gate electrodes. At this time, a tungsten silicide (WSi)
film may be formed on the polysilicon film to form word lines
having a polycide structure and thereby decrease the resistance of
electrical interconnections.
[0114] As shown in FIG. 13B, a high-temperature CVD oxide film (HTO
film) 8 and a BPSG film 9 are sequentially formed in this order to
cover the word lines 7. After contact holes (not shown) reaching
the word lines 7 and the like are formed, an aluminum alloy film is
formed by sputtering on the BPSG film 9, which has been planarized
by a reflow process, so as to fill the contact holes. The aluminum
alloy film is patterned by photolithography and subsequent dry
etching to form upper interconnecting lines 11.
[0115] After that, a protective film 12 is formed to cover the
upper interconnecting lines 11, and formation processes for an
insulating interlayer, contact holes (via holes), and
interconnecting lines are executed, thereby completing a buried bit
line type flash memory.
[0116] As described above, in this embodiment, the ONO film 6 is
formed after the impurities (arsenic) in the bit lines 5 are
activated, and nitrogen (carbon) having the accelerated oxidation
suppressing function is ion-implanted. At the time of formation of
the ONO film 6, the silicon oxide film 21 as a component of the ONO
film 6 is formed thick only above the bit lines 5 by accelerated
oxidation, so that sufficient electrical insulation is ensured
between the bit lines 5 and the word lines 7. In this case, in
various annealing processes (formation of the gate insulating film
in the peripheral circuit region and the like) after formation of
the ONO film 6, since the thick portions of the silicon oxide film
21 above the bit lines 5 are covered with the other components (the
silicon nitride film 22 and the silicon oxide film 23) of the ONO
film 6, in addition, due to the accelerated oxidation suppressing
function of nitrogen (carbon), the thick portions of the silicon
oxide film 21 are not greatly acceleratingly oxidized, and bird's
beak formation can be suppressed to a negligible level.
[0117] Additionally, in this embodiment, since nitrogen (carbon) is
ion-implanted obliquely to the surface of the semiconductor
substrate 1, nitrogen (carbon) can be introduced also into the end
portions between the source and drain (channel) of the
semiconductor substrate 1. Hence, nitrogen can be more deeply
introduced into the channel ends, and thereby formation of bird's
beaks is suppressed. At the time of nitrogen ion implantation,
since the resist pattern 4 above the bit lines 5 serves as a mask,
it prevents nitrogen ion implantation. At these portions,
therefore, accelerated oxidation is not suppressed, and the silicon
oxide film 21 becomes thick and may contribute to ensure a
sufficient breakdown voltage. Hence, the interface level in the
region where electrons are injected upon a data write operation is
terminated, and the charge holding characteristic is improved.
[0118] That is, in this embodiment, throughout the process until
the completion of the flash memory, the thickness of the ONO film 6
above the bit lines 5 is kept within the optimum range in which
sufficient electrical insulation is ensured between the bit lines 5
and the word lines 7 and no bird's beak that may degrade the charge
holding characteristic is formed. Additionally, the thickness can
be controlled thinner by the accelerated oxidation suppressing
function of nitrogen (carbon). Furthermore, since nitrogen (carbon)
is obliquely ion-implanted, the charge holding characteristic can
be further improved. Hence, a very reliable flash memory with
improved transistor characteristics can be implemented.
[0119] The present invention is not limited to the above-described
first to third embodiments. The present invention can be applied
not only to single-level type memories that use data of "0" and
"1", but also to binary memories that use data of "00", "01", "10",
and "11", or to further multi-level type memories.
[0120] The present invention makes it possible to provide a
semiconductor device, in particular, a semiconductor memory having
a buried bit line structure, and a manufacturing method of the
same, wherein electrical insulation between bit and word lines is
sufficiently ensured and an excellent charge holding characteristic
is realized by suppressing undesirable bird's beak formation.
* * * * *