U.S. patent application number 09/942792 was filed with the patent office on 2002-09-19 for video signal timing in a multi-format environment.
This patent application is currently assigned to ADC Telecommunication, Inc.. Invention is credited to Meyer, Charles S..
Application Number | 20020130968 09/942792 |
Document ID | / |
Family ID | 23032139 |
Filed Date | 2002-09-19 |
United States Patent
Application |
20020130968 |
Kind Code |
A1 |
Meyer, Charles S. |
September 19, 2002 |
Video signal timing in a multi-format environment
Abstract
In a video broadcast or production plant including first and
second video sources which provide first and second digital video
signals respectively at integer related frame rates, the video
sources are operated so that the first and second video signals are
aligned at a reference time. Switch points for updating a router in
the plant are defined by measuring lapse of time from the reference
time.
Inventors: |
Meyer, Charles S.; (Nevada
City, CA) |
Correspondence
Address: |
MERCHANT & GOULD PC
P.O. BOX 2903
MINNEAPOLIS
MN
55402-0903
US
|
Assignee: |
ADC Telecommunication, Inc.
Minnetonka
MN
|
Family ID: |
23032139 |
Appl. No.: |
09/942792 |
Filed: |
August 29, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09942792 |
Aug 29, 2001 |
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09270632 |
Mar 17, 1999 |
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6292229 |
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Current U.S.
Class: |
348/426.1 ;
348/E11.021; 348/E5.014; 348/E5.057; 348/E5.114; 725/116; 725/90;
725/94 |
Current CPC
Class: |
H04N 11/20 20130101;
H04N 21/234309 20130101; H04N 5/268 20130101; H04N 5/46 20130101;
H04N 21/2665 20130101; H04N 21/242 20130101; H04N 5/073
20130101 |
Class at
Publication: |
348/426.1 ;
725/94; 725/90; 725/116 |
International
Class: |
H04N 007/173; H04N
007/12; H04N 011/02; H04N 011/04 |
Claims
1. A method of operating a video router in a plant including at
least first and second video sources which provide first and second
digital video signals respectively at integer related frame rates,
said method including: operating the first and second video sources
so that the first and second video signals are aligned at a
reference time, and defining switch points for updating the router
by measuring lapse of time from said reference time.
2. A method according to claim 1, further comprising converting the
first and second digital video signals to a common digital
interface format.
3. A method according to claim 1, wherein the first and second
digital video signals are high definition video signals and the
plant also includes a third video source which provides a standard
definition video signal under control of a master clock signal, and
wherein the master clock signal is used to control the first and
second video sources and to measure lapse of time.
4. A method according to claim 1, comprising generating a master
clock signal at a frequency that is equal to, or an integer
multiple of, the frame rate of the first digital video signal, and
measuring lapse of time by reference to the master clock signal and
periodically applied time offsets.
Description
BACKGROUND OF THE INVENTION
[0001] This invention relates to video signal timing in a
multi-format environment.
[0002] Until quite recently, the rules of the United States Federal
Communications Commission (FCC) required that video material should
be broadcast using the NTSC signal format. The NTSC video format is
an interlaced format, in which each frame is composed of two
fields. The frame rate of the NTSC video format is 30/M frames/sec
where M is a data rate divisor and is equal to 1.001.
[0003] In a television broadcast facility, several video signal
sources, each generating a signal in NTSC format, are connected to
respective inputs of a router, which supplies the video signals to
selected video signal destinations. The various signal sources are
controlled by a common timing signal so that they are in phase.
[0004] The router is composed of multiple input buses, connected to
the sources respectively, multiple output buses, connected to the
destinations respectively, and an array of crosspoint switches that
are operable selectively for connecting any one input bus to any
selected set of one or more output buses. The state of the ij th
crosspoint switch is ON (it connects output bus j to input bus i)
or OFF (it isolates output bus j from input bus i). The router
includes a memory having an addressable location associated with
each crosspoint switch. During each active interval of the video
signal, the memory is addressed to store in each location the
desired state of the corresponding crosspoint during the next
active interval. The desired state may be the same as the current
state or it may be the opposite state. During the vertical blanking
interval, the contents of the memory are used to update the entire
array of crosspoint switches.
[0005] In order to minimize degradation of the output signals of
the router, the update is made consistently on the same line of the
video signal frame. This line is referred to as the switch line,
and the time at which the crosspoints are updated is referred to as
the switch point. Nominally, the switch point is halfway through
the switch line, but SMPTE RP-168 defines a window of +/-5
.mu.s.
[0006] Since the NTSC video format is an interlaced format, there
are two vertical blanking intervals, and hence two switch lines,
per frame. In each field, the switch line is the first line of the
vertical blanking interval after the equalizing pulses. The switch
line is identified by continuously monitoring the video signal to
find vertical sync, and counting lines until the first line after
the equalizing pulses.
[0007] Current rules of the FCC allow broadcast of video material
in a high definition (HD) format, but require that a television
broadcaster who broadcasts video material in an HD format should
broadcast the same material in standard definition (SD) NTSC
format. One way for a broadcaster to meet this requirement would be
to generate the video material for broadcast in the HD domain and,
concurrently with broadcast of the HD material, convert the HD
material to SD and broadcast the SD material. An alternative, which
may be attractive for some purposes, would be to receive the source
material in both formats, process the SD material in an SD path to
generate the SD broadcast stream and concurrently process the HD
material in a separate, parallel HD path to generate the HD
broadcast stream, and broadcast the SD material and the HD material
simultaneously.
[0008] Although the SD video signals that are currently broadcast
are analog formats, the HD signals are in digital format and almost
all of the processing of SD and HD video signals is conducted in
the digital domain.
[0009] At least thirteen digital HD signal formats, designated by
SMPTE 292M Format ID's A-M, have been defined for HD video signals.
Several of the format parameters for these digital high definition
video signals are listed in Table I.
1TABLE I Reference SMPTE Standard 260 M 295 M 274 M 296 M Formal ID
A B C D E F G H I J K L M Lines per frame 1125 1125 1250 1125 1125
1125 1125 1125 1125 1125 1125 750 750 Total active lines 1035 1035
1080 1080 1080 1080 1080 1080 1080 1080 1080 720 720 Frame rate
(Hz) 30 30/M 25 30 30/M 25 30 30/M 25 24 24/M 60 60/M Fields per
frame 2 2 2 2 2 2 1 1 1 1 1 1 1
[0010] The U.S. broadcast facilities that simultaneously broadcast
HD and SD streams have each selected either format E or format M
for digital HD material. Format E is a 30/M frame/sec, 1125
lines/frame interlaced format and format M is a 60/M frame/sec, 750
lines/frame progressive scan format.
[0011] For some of the digital HD signal formats, there are
equivalent analog signal formats in which the blanking interval
includes equalizing pulses. Depending on the format, the equalizing
pulses occur in the first five or six lines of the vertical
blanking interval. With respect to a digital signal format having a
corresponding analog format, it has been proposed that the switch
line should be the first line after the vertical blanking interval.
It has also been proposed that the switch line for a digital signal
format for which there is no corresponding analog format should be
the same line as the switch line for the closest digital format for
which there is a corresponding analog format.
[0012] In video post production, a router is used to assemble
source material to produce a video stream which is supplied to a
broadcast facility to include in a broadcast stream. For example,
in post production several brief scenes might be assembled to form
a commercial message, which the broadcaster combines with other
commercial messages and program material to generate the broadcast
stream. In post production, the segments of the program source
material may be in different formats. It may be necessary to
combine a segment of a first format with a segment of a second
format and produce a program in a third format. Much of the
material used in post production is based on film, which is 24
frames/sec.
[0013] SMPTE 259 specifies the structure of a serial digital
interface (SDI) data stream derived from a 10-bit 4:2:2 component
digital signal or a 4f.sub.sc NTSC composite digital signal. The
SDI data stream was specified in order to facilitate
interconnection of equipment from different manufacturers. Each
line interval of the SDI data stream has four areas: EAV (end of
active video) for the previous line, blanking level or horizontal
ancillary data, SAV (start of active video) and digital active
line, which contains active picture or vertical ancillary data
depending on the location of the line in the frame.
[0014] Similarly, SMPTE 292M specifies the structure of a serial
digital interface data stream derived from 10-bit source data words
for HD digital signals. Digital video data in accordance with any
of the SMPTE HD formats defined in Table I can be distributed in a
serial data stream in accordance with SMPTE 292M.
[0015] The serial digital interface data stream specified in SMPTE
292 does not include a word that specifies the source format, e.g.
SMPTE format E or SMPTE format M, and accordingly it is not
possible to determine the source format without disassembling the
data stream and observing patterns in the source data.
Consequently, it is not possible to determine whether there is a
corresponding analog format and, if so, whether the equalizing
pulses of the corresponding analog format occupy the first five
lines or the first six lines of the vertical blanking interval.
SUMMARY OF THE INVENTION
[0016] The proposals that have hitherto been made regarding the
switch line for HD digital video signals miss an opportunity to
afford simplified timing and synchronization across a multi-format
facility. Further, it will be appreciated by those skilled in the
art that setting the switch point of a digital video signal by
reference to equalizing pulses of an analog equivalent signal
imposes restrictions on the choice of the switch point that are not
related to requirements of the digital signal format.
[0017] It has been suggested in accordance with the invention that
it would be desirable to switch HD video data in the SMPTE 292
domain instead of using SMPTE 292 only as an interface standard and
converting the SMPTE 292 signal to Format E or M, for example, for
switching. However, a barrier to implementation of this suggestion
is that it is not possible to distinguish source format in the
SMPTE 292 domain and therefore it is not possible to determine the
proper switch point.
[0018] For the time being, it will be assumed for the sake of
simplicity that the value of M is one, not 1.001. Under this
assumption, the frame rate of the NTSC signal is 30 Hz and the
frame rates of formats E, K and M are 30 Hz, 24 Hz and 60 Hz
respectively.
[0019] It has been observed in accordance with the invention that
there is a predictable and repeating sequence of time offsets
between a signal having a frequency of 30 Hz (or an integer
multiple of 30 Hz) and a signal at a frequency of 24, 25 or 60 Hz.
Accordingly, with a master clock signal running at 30 Hz, or an
integer multiple of 60 Hz, it is possible to set switch points not
only for 30 frame per second material but also for 24, 25 and 60
frame material provided that the different signal sources have a
known time offset, which may be zero, at an arbitrary time
t.sub.ref. In this event, the switch lines of each format occur at
exactly predictable points in time in a repeating sequence that is
reset every second.
[0020] In accordance with the present invention there is provided a
method of operating a video router in a plant including at least
first and second video sources which provide first and second
digital video signals respectively at integer related frame rates,
said method including operating the first and second video sources
so that the first and second video signals are aligned at a
reference time, and defining switch points for updating the router
by measuring lapse of time from said reference time.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] For a better understanding of the invention, and to show how
the same may be carried into effect, reference will now be made, by
way of example, to the accompanying drawings, in which
[0022] FIG. 1 is a simplified block diagram of a first television
broadcast facility in accordance with the present invention,
[0023] FIG. 2 is a simplified block diagram of a second television
broadcast facility in accordance with the present invention,
and
[0024] FIG. 3 is a simplified block diagram of a television post
production facility in accordance with the present invention.
DETAILED DESCRIPTION
[0025] FIG. 1 illustrates a broadcast facility including three
video sources 10, designated more specifically Source A, Source B
and Source C. Source A generates an SD NTSC signal whereas Sources
B and C generate HD signals in the broadcaster's selected HD
digital format, such as SMPTE Format E. The output signals of the
sources are supplied to a format converter 14, which generates an
HD signal from the SD input signal and generates SD signals from
the HD input signals, and converts the SD signals to SMPTE 259
format and the HD signals to SMPTE 292 format. The SD signals are
supplied to an SD router 18 and the HD signals are supplied to an
HD router 22. The sources operate under control of a master clock
generator 24, which generates a master clock at 60 Hz, such that at
a selected time t0, the start of line 1, field 1, frame 1 of the
three signals, generated by the three sources respectively, are
aligned. The master clock MCLK is supplied to the format converter
14 and is used to generate local clock signals for controlling the
operations performed by the format converter. By using the master
clock MCLK to control all operations performed by the format
converter, and using delays if necessary to compensate for
processing and propagation time, the output signals of the format
converter are aligned at time t.sub.1, where t.sub.1+t.sub.0
represents delay from the outputs of the sources 10 to the outputs
of the format converter 14.
[0026] The SD router provides SD output signals SDX and SDY by
switching among its input signals SDA, SDB and SDC. Similarly, the
HD router 22 provides output signals HDX and HDY by switching among
its input signals HDA, HDB and HDC. The video contents of the
signals HDX and HDY correspond to the contents of the signals SDX
and SDY respectively.
[0027] The master clock signal MCLK is also supplied to an SD
offsets circuit 26, which employs delay elements and multiplexers
to generate two SD router switching clock signals SDCLK1 and
SDCLK2, and to an HD offsets circuit 30, which employs delay
elements and multiplexers to generate two HD router switching clock
signals HDCLK1 and HDCLK2. The router switching clock signals are
used to control updating of the crosspoints of the two routers
respectively.
[0028] The two signals SDCLK1 and SDCLK2 each have a frequency of
30 Hz but they are offset in time. The signal SDCLK1 is used to
update the crosspoints of the router 18 during the blanking
interval of field 1 and has an active clock edge occurring halfway
through line 1 of each frame, at about t.sub.1+nH+31.75.mu.s, where
n represents frame number, and the signal SDCLK2 is used to update
the crosspoints during the blanking interval of field 2 and has an
active clock edge occurring halfway through line 263 of each frame,
at about t.sub.1+nH+16,730.16 .mu.s. The switch point of field 1
therefore occurs halfway through line 1 and the switch point of
field 2 occurs halfway through the first complete line of field 2.
It will be appreciated that the interval between the switch points
for field 1 and field 2 is not equal to half the frame interval and
therefore the 60 Hz clock cannot be used alone to time both switch
points.
[0029] Similarly, the two signals HDCLK1 and HDCLK2 each have a
frequency of 30 Hz but they are offset in time. The signal HDCLK1
is used to update the crosspoints of the router 22 during the
blanking interval of field 1 and has an active clock edge occurring
halfway through line 1 of each frame, at about t.sub.1+nH+24.75
.mu.s, and the signal HDCLK2 is used to update the crosspoints
during the blanking interval of field 2 and has an active clock
edge occurring halfway through line 563 of each frame, at about
t.sub.1+nH+16,716.17 .mu.s. The switch point of field 1 therefore
occurs halfway through line 1 and the switch point of field 2
occurs halfway through the first complete line of field 2.
[0030] It will therefore be seen that the two routers are operated
without explicit regard to time relative to the lines of the
respective video signals but by establishing a time reference point
and measuring lapse of time after the reference point.
[0031] The foregoing description of FIG. 1 has been based for
convenience on the assumption that all the crosspoints of each
router are updated simultaneously. However, routers are available
in which the crosspoints on a given input bus can be updated at a
different time from the crosspoints on a different input bus. Such
a router can be used for both the HD signals and the SD signals.
FIG. 2 shows such an arrangement. The SDCLK signals are used for
updating the crosspoints on the router input buses that receive the
SD signals and correspondingly the HDCLK signals are used for
updating the crosspoints on the router input buses that receive the
HD signals.
[0032] FIG. 3 illustrates schematically a post production facility
having three video sources 34, more specifically designated Source
P, Source Q and Source R which supply video signals in,
respectively, NTSC, SMPTE format K and SMPTE format M. The three
video signals are supplied to format converters 38, 40 and 42
respectively. The converter 38 converts the NTSC signal to SMPTE
format E and converts format E to SMPTE 292. The converter 40
converts SMPTE format K to SMPTE 292 and the converter 42 converts
SMPTE format M to SMPTE 292.
[0033] The three sources 34 operate under control of a master clock
generator 50, which generates a master clock MCLK at 60 Hz. The
master clock signal is used directly to control Source P and Source
R. A clock signal at 24 Hz is generated from the master clock
signal by integer multiplication and division and is used to
control Source Q. Since the same clock signal is used to control
all three sources, it is straightforward to align line 1, field 1,
frame 1 of the three sources at a reference time t0.
[0034] The master clock signal is also used to control the format
converters, so that the output signals of the format converters are
aligned at time t.sub.1, where t.sub.1-t.sub.0 represents delay
from the outputs of the sources 34 to the outputs of the format
converters.
[0035] The three SMPTE 292 signals P, Q and R are supplied to a
router 46, which selects among the three signals P, Q and R to
generate output signals U and V. The switch points for the router
46 are determined based on lapse of time from the reference time
t.sub.1. The first active edge of the master clock signal MCLK
coincides with the start of line 1, field 1, frame 1 of the three
signals P, Q and R.
[0036] The switch points for the interlaced format of signal P
(format E) are halfway through line 1 and halfway through the first
complete line of field 2. The field 1 switch points of format E are
at t.sub.1+(2n-2)*H+14.81 .mu.s, where H is the period of the
master clock signal and n is the frame number, and the field 2
switch points of format E are at t.sub.1+(2n-1)*H+29.64 .mu.s. Over
a five frame sequence, the frame 1 switch point of signal Q, which
is based on the progressive scan format K, is at t.sub.1+18.52
.mu.s, the frame 2 switch point is at t.sub.1+2H+8351.85 .mu.s, the
frame 3 switch point is at t.sub.1+5H, the frame 4 switch point is
at t.sub.1+7H+8351.85 .mu.s, and the frame 5 switch point is at
t.sub.1+10H. The frame n switch point of signal R, which is based
on the progressive scan format M, is t.sub.1+(n-1)*H+11.11
.mu.s.
[0037] It can be seen from the foregoing that the time offsets of
the switch points of the several formats are offset from the active
clock edges of the master clock signal MCLK in a predictable and
repeating fashion. It will be appreciated that similar
considerations apply to a 25 Hz frame rate.
[0038] It has been assumed in the foregoing discussion that the
value of M is one, not 1.001. Since each of the signal formats
mentioned in the foregoing discussion has a frame rate that is not
an integer number of frames per second but an integer divided by M
frames per second, the time offsets mentioned above would have to
be multiplied by M.
[0039] Further, although for the sake of simplicity the invention
has been described with reference to controlling the router so that
the switch line is the first line of the vertical blanking interval
of each field, the switch line could equally well be another line
of the vertical blanking interval. It is necessary only that the
several formats be aligned so that at an arbitrary time t.sub.ref
the beginning of a given line of each format is aligned in time
with the beginning of a line of each other format. When this is
achieved, the switch points can be controlled by measuring lapse of
time from the time t.sub.ref, without regard to line count.
[0040] It will be appreciated that the invention is not restricted
to the particular embodiment that has been described, and that
variations may be made therein without departing from the scope of
the invention as defined in the appended claims and equivalents
thereof.
* * * * *