U.S. patent application number 09/779234 was filed with the patent office on 2002-09-19 for delta sigma converter incorporating a multiplier.
This patent application is currently assigned to Ericsson Inc.. Invention is credited to Cairns, Douglas A., Fraleigh, Stephen.
Application Number | 20020130800 09/779234 |
Document ID | / |
Family ID | 25115755 |
Filed Date | 2002-09-19 |
United States Patent
Application |
20020130800 |
Kind Code |
A1 |
Fraleigh, Stephen ; et
al. |
September 19, 2002 |
Delta sigma converter incorporating a multiplier
Abstract
A delta-sigma converter including a multiplier. The delta-sigma
converter includes a feed-forward path and a feedback path
providing a feedback signal. The converter output signal is
multiplied in the feedback path by a mapping function, and the
multiplied signal is mapped to a digital feedback signal having the
same number of bits as the input signal. There is also provided a
digital-to-analog converter including a delta-sigma converter
consistent with the invention, and a method of multiplying a
digital signal.
Inventors: |
Fraleigh, Stephen; (Raleigh,
NC) ; Cairns, Douglas A.; (Durham, NC) |
Correspondence
Address: |
COATS & BENNETT, PLLC
P O BOX 5
RALEIGH
NC
27602
US
|
Assignee: |
Ericsson Inc.
|
Family ID: |
25115755 |
Appl. No.: |
09/779234 |
Filed: |
February 8, 2001 |
Current U.S.
Class: |
341/143 |
Current CPC
Class: |
H03M 7/3015
20130101 |
Class at
Publication: |
341/143 |
International
Class: |
H03M 003/00 |
Claims
What is claimed is:
1. A delta-sigma converter comprising: a feed-forward path for
receiving a feed-forward signal and providing an output signal; and
a feedback path comprising a multiplying mapping function, said
mapping function being configured to multiply said output signal
based on at least one multiplication factor and provide an
N.sub.FB-bit feedback signal representative of said multiplied
output signal, said feedback signal being combined with an N-bit
input signal to provide said feed-forward signal.
2. A delta-sigma converter according to claim 1, wherein said
mapping function is configured to provide said feedback signal in
accordance with: 2 y FB [ n ] = { 2 N - 1 if y q [ n ] = 1 - 2 N -
1 if y q [ n ] = 0 } where y.sub.FB[n] is a value of said feedback
signal at a discrete time n, y.sub.q[n] is a value of said output
signal at said discrete time n, and a is said at least one
multiplication factor.
3. A delta-sigma converter according to claim 2, wherein
0<.alpha.<1.
4. A delta-sigma converter according to claim 1, wherein said at
least one multiplication factor is a programmable value.
5. A delta-sigma converter according to claim 1, wherein said
output signal is a single-bit output signal.
6. A delta-sigma converter according to claim 1, wherein said
feed-forward path comprises a low pass filter and a quantizer, said
low pass filter for receiving said feed-forward signal and having
an output coupled to an input of said quantizer, said quantizer
being configured to provide said output signal.
7. A delta-sigma converter according to claim 6, wherein said low
pass filter comprises an integrator.
8. A delta-sigma converter comprising: a feed-forward path
comprising a low pass filter for receiving a feed-forward signal
and a quantizer coupled to an output of said low pass filter, said
quantizer being configured to provide an output signal; and a
feedback path comprising a multiplying mapping function, said
mapping function being configured to provide an N.sub.FB-bit
feedback signal in accordance with: 3 y FB [ n ] = { 2 N - 1 if y q
[ n ] = 1 - 2 N - 1 if y q [ n ] = 0 } where y.sub.FB[n] is a value
of said N.sub.FB-bit feedback signal at a discrete time n,
y.sub.q[n] is a value of said output signal at said discrete time
n, and .alpha. is a multiplication factor, said feedback signal
being combined with an N-bit input signal to provide said
feed-forward signal.
9. A delta-sigma converter according to claim 8, wherein
0<.alpha.<1.
10. A delta-sigma converter according to claim 8, wherein said
multiplication factor is a programmable value.
11. A delta-sigma converter according to claim 8, wherein said
output signal is a single-bit output signal.
12. A delta-sigma converter according to claim 8, wherein said low
pass filter comprises an integrator.
13. A digital-to-analog converter comprising a delta-sigma
converter configured to provide a digital output signal
representative of an N-bit digital input signal multiplied based on
at least one multiplication factor; and a digital to analog
converter for providing an analog output signal representative of
said digital output signal.
14. A digital-to-analog converter according to claim 13, wherein
said delta-sigma converter comprises: a feed-forward path for
receiving a feed-forward signal and providing said digital output
signal; and a feedback path comprising a multiplying mapping
function, said mapping function being configured to multiply said
digital output signal based on said at least one multiplication
factor and provide an N.sub.FB-bit feedback signal representative
of said multiplied output signal, said feedback signal being
combined with said N-bit digital input signal to provide said
feed-forward signal.
15. A digital-to-analog converter according to claim 14, wherein
said mapping function is configured to provide said feedback signal
in accordance with: 4 y FB [ n ] = { 2 N - 1 if y q [ n ] = 1 - 2 N
- 1 if y q [ n ] = 0 } where y.sub.FB[n] is a value of said
N.sub.FB-bit feedback signal at a discrete time n, y.sub.q[n] is a
value of said output signal at said discrete time n, and .alpha. is
said at least one multiplication factor.
16. A delta-sigma converter according to claim 15, wherein
0<.alpha.<1.
17. A digital-to-analog converter according to claim 13, wherein
said digital output signal is a single-bit output signal.
18. A digital-to-analog converter according to claim 14, wherein
said at least one multiplication factor is a programmable
value.
19. A digital-to-analog converter according to claim 14, wherein
said feed-forward path comprises a low pass filter and a quantizer,
said low pass filter for receiving said feed-forward signal and
having an output coupled to an input of said quantizer, said
quantizer being configured to provide said output signal.
20. A digital-to-analog converter according to claim 19, wherein
said low pass filter comprises an integrator.
21. A digital-to-analog converter according to claim 13, said
converter further comprising a low pass filter for receiving said
output signal and providing a filtered output signal.
22. A method of multiplying an N-bit digital signal comprising:
coupling said digital signal to a delta sigma converter, said
delta-sigma converter comprising a feed-forward path for receiving
a feed-forward signal and providing an output signal, and a
feedback path comprising a multiplying mapping function, said
mapping function being configured to multiply said output signal
based on at least one multiplication factor and provide an
N.sub.FB-bit feedback signal representative of said multiplied
output signal, said feedback signal being combined with said
digital signal to provide said feed-forward signal.
23. A method according to claim 22, wherein said mapping function
is configured to provide said feedback signal in accordance with: 5
y FB [ n ] = { 2 N - 1 if y q [ n ] = 1 - 2 N - 1 if y q [ n ] = 0
} where y.sub.FB[n] is a value of said N.sub.FB-bit feedback signal
at a discrete time n, y.sub.q[n] is a value of said output signal
at said discrete time n, and .alpha. is said at least one
multiplication factor.
24. A method according to claim 23, wherein 0<.alpha.<1.
25. A method according to claim 22, wherein said output signal is a
single-bit output signal.
26. A method according to claim 22, wherein said at least one
multiplication factor is a programmable value.
27. A method according to claim 22, wherein said feed-forward path
comprises a low pass filter and a quantizer, said low pass filter
for receiving said feed-forward signal and having an output coupled
to an input of said quantizer, said quantizer being configured to
provide said output signal.
28. A method according to claim 27, wherein said low pass filter
comprises an integrator.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to digital-to-analog
converters, and, more particularly, to a delta-sigma
digital-to-analog converter incorporating a multiplication
function.
[0002] Digital-to-analog (D/A) and analog-to-digital (A/D)
converters are widely used for converting electrical signals
between digital and analog formats. Communication systems, for
example, typically require extensive D/A and A/D conversion for
performing a variety of signal processing functions. These
converters may be implemented on an integrated circuit, such as an
application specific integrated circuit (ASIC).
[0003] In an ASIC implementation, a converter may be combined with
several other signal processing functions for performing the
desired ASIC function. One common function implemented on such an
ASIC is a multiplier function. There are several known techniques
for providing a multiplier on an ASIC. While implementation of a
multiplier is well understood and standard multiplier fabrication
methods exist, the multiplier typically requires a relatively large
area of the semiconductor chip on which the ASIC is formed. As a
result, the multiplier typically consumes a significant amount of
power.
BRIEF SUMMARY OF THE INVENTION
[0004] A delta-sigma converter consistent with the invention
includes a feed-forward path for receiving a feed-forward signal
and providing an output signal; and a feedback path comprising a
multiplying mapping function. The mapping function is configured to
multiply the output signal based on at least one multiplication
factor and to provide a feedback signal representative of the
multiplied output signal. The feedback signal is combined with an
input signal to provide the feed-forward signal. A method of
multiplying a digital signal consistent with the invention includes
coupling the digital signal as the input signal to a delta-sigma
converter consistent with the invention.
[0005] A digital-to-analog converter consistent with the invention
includes a delta-sigma converter configured to provide a digital
output signal representative of an N-bit digital input signal
multiplied based on at least one multiplication factor; and a
digital to analog converter for providing an analog output signal
representative of the digital output signal.
BRIEF DESCRIPTION OF THE DRAWING
[0006] Advantages of the present invention will be apparent from
the following detailed description of exemplary embodiments
thereof, which description should be considered in conjunction with
the accompanying drawings, in which:
[0007] FIG. 1 illustrates an exemplary digital-to-analog converter
consistent with the invention;
[0008] FIG. 2 illustrates an exemplary delta-sigma converter
consistent with the invention; and
[0009] FIG. 3 illustrates a sampled-data equivalent circuit for an
exemplary delta-sigma converter consistent with the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0010] With reference now to FIG. 1, there is illustrated an
exemplary digital-to-analog converter 100 consistent with the
invention. Those skilled in the art will recognize that a converter
consistent with the invention may be incorporated into a variety of
systems for achieving D/A conversion. A converter consistent with
the invention may, for example, be provided in transmitters and
receivers for a communication network, including wire-based and
cellular or wireless networks using air interfaces, such as GSM,
TDMA, CDMA or FDMA.
[0011] As shown, a D/A converter 100 consistent with the invention
may include:a linear system 102 for receiving a multi-bit input
signal x, i.e. a stream of digital words having a word length N; a
multiplying delta-sigma converter 104 for receiving the output
x.sub.a of the linear system; a digital-to-analog converter (DAC)
106 for receiving the output y.sub.q of the delta-sigma converter;
and a low- pass filter 108 for receiving the output y.sub.d of the
DAC. With the exception of the multiplying delta-sigma converter,
the illustrated converter 100 includes elements conventionally
provided in a delta-sigma-type D/A converter. A variety of
configurations for the linear system 102, the DAC 106, and the low
pass filter 108 will, therefore, be known to those skilled in the
art.
[0012] The linear system 102 may, for example, be a conventional
interpolator for changing the data rate of the incoming digital
signal x and suppressing spectral replicas of the data in the
frequency domain. In a case where an interpolator is not required,
however, the linear system may simply comprise a direct connection
of the digital input to the multiplying delta-sigma converter. In a
known manner, a feed-forward path of the delta-sigma converter
shortens the input word length, e.g. to a single bit, such that the
quantization noise introduced by this process is outside of the
signal baseband. As will be described in greater detail below, the
delta-sigma converter is also configured to multiply the digital
signal, thereby eliminating the need for a separate dedicated
multiplier circuit.
[0013] The DAC 106, typically a one-bit DAC, may be of conventional
construction and coupled to the output of the delta-sigma converter
104. The output y.sub.d of the DAC 106 is an analog representation
of the digital input signal y.sub.q, including an amount of noise
resulting from quantization error introduced by the delta-sigma
converter. The noise may be significantly suppressed by the
conventional low-pass filter 108 to provide an analog output y.
[0014] Turning now to FIG. 2, there is illustrated a block diagram
of an exemplary multiplying delta-sigma converter 200 consistent
with the invention. In general, the converter 200 incorporates a
multiplying mapping function in the feedback path of a known
delta-sigma converter configuration. For simplicity and ease of
explanation, the present invention will be described herein in
connection with a first-order delta-sigma converter configuration.
It is to be understood, however, that the present invention is
equally applicable to higher order delta sigma converters. Those
skilled in the art will also recognize that the present invention
is applicable to multi-bit, as well as single-bit, delta sigma
converters.
[0015] In the illustrated exemplary embodiment, the converter 200
has a feed-forward path including a low pass filter 202 and a
quantizer 204, and a feedback path including a multiplying
digital-to-digital mapping function (MDDMF) 206. The low pass
filter 202 may be provided in a variety of known configurations,
and is typically an integrator. The output of the low-pass filter
202 is provided to the quantizer 204, which also has a known
configuration. The quantizer is typically a two-level quantizer,
but may be a multi-level quantizer. The quantized output y.sub.q is
provided as the converter output and is fed back to the MDDMF
206.
[0016] In a manner to be described in more detail below, the MDDMF
206 is configured to map the quantized output, typically one bit,
to a full-scale digital signal Y.sub.FB representing the value of
the quantized output. The signal y.sub.FB may have a word size,
N.sub.FB, of at least the same number of bits, N, as the input
signal x.sub.a. The MDDMF 206 also multiplies the quantized output
based on a predetermined multiplication factor. The feedback signal
y.sub.FB is combined with the input signal x.sub.a. This feedback
through the MDDMF 206 forces the average value of the quantized
output y.sub.q to track the average value of the input signal
x.sub.a multiplied by the predetermined multiplication factor.
[0017] The operation of the MDDMF will be described in greater
detail in connection with FIG. 3, which illustrates the
sampled-data equivalent circuit for an ASIC implementation of an
exemplary delta-sigma converter 300 consistent with the invention.
As shown, the feed-forward section of the converter includes a
discrete time integrator 302 and a quantizer 304 that introduces
quantization error e[n]. The integrator 302 and the quantizer 304
function in a known manner.
[0018] In the illustrated embodiment, the MDDMF 306 maps the
quantizer output y.sub.q to a full-scale digital feedback signal
y.sub.FB[n] having the same number of bits as the input, e.g. a one
bit quantizer output y.sub.q may be mapped to a 12-bit feedback
value y.sub.FB[n]. The MDDMF 306 also multiplies the quantizer
output y.sub.q based on a predefined multiplication factor .alpha..
Consistent with the present invention, the MDDMF 306 may be
implemented as a lookup table indexed by the quantizer output
y.sub.q[n]. For example, in an exemplary embodiment y.sub.FB[n] may
be expressed as: 1 y FB [ n ] = { 2 N - 1 if y q [ n ] = 1 - 2 N -
1 if y q [ n ] = 0 }
[0019] where y.sub.FB[n] is the N.sub.FB-bit feedback value at a
discrete time n, y.sub.q[n] is the quantizer output, and a is the
desired multiplication factor. A delta sigma converter consistent
with the invention may thus be implemented for effecting both a D/A
conversion and a digital multiplication through use of an
appropriate MDDMF in the converter feedback path.
[0020] The multiplication factor a may be a single static value. It
is to be understood, however, that a converter consistent with the
invention may be configured to implement multiple and/or
programmable values for .alpha.. In the case of programmable
values, the mapping circuit may be configured to receive an input
from an .alpha. selector 308 for defining one or more values for
.alpha.. The selector may be integral with an IC on which the
converter is implemented or may comprise an external connection.
Those skilled in the art will recognize that a variety of
configurations may be provided to manage multiple static or
programmable a values. For example, lookup tables may be
constructed for .alpha..sub.0, .alpha..sub.1, . . . .alpha..sub.n
and concatenated to form one large lookup table.
[0021] Those skilled in the art will also recognize that
delta-sigma converters may produce artifacts if overdriven, i.e. if
x[n]>y.sub.FB[n]. In the illustrated exemplary embodiment, to
avoid such artifacts .alpha. may be selected such that
0<.alpha..ltoreq.1. For all values of .alpha.<1, the number
of bits N.sub.FB will exceed N. The summing junction, the feedback
path and the internal feed-forward paths should be configured to
accommodate the worst case of the digital feedback word size.
[0022] The embodiments that have been described herein, however,
are but some of the several which utilize this invention and are
set forth here by way of illustration but not of limitation. It is
obvious that many other embodiments, which will be readily apparent
to those skilled in the art, may be made without departing
materially from the spirit and scope of the invention.
* * * * *