U.S. patent application number 09/892995 was filed with the patent office on 2002-08-15 for interconnection structure of semiconductor element.
Invention is credited to Umemura, Eiichi.
Application Number | 20020111053 09/892995 |
Document ID | / |
Family ID | 18899918 |
Filed Date | 2002-08-15 |
United States Patent
Application |
20020111053 |
Kind Code |
A1 |
Umemura, Eiichi |
August 15, 2002 |
INTERCONNECTION STRUCTURE OF SEMICONDUCTOR ELEMENT
Abstract
An interconnection structure comprises: an interlayer insulating
film; and first interconnection layer to which low potential is
applied and second interconnection layer to which high potential is
applied when the interconnection structure is used, formed with the
interlayer insulating film therebetween; and a via hole formed in
the interlayer insulating film for electrically connecting the
first interconnection layer and second interconnection layer.
Overlap regions including regions of the first interconnection
layer and the second interconnection layer faced said via hole are
formed for both the first interconnection layer and second
interconnection layer. The shortest distance from the edge of the
via hole contact region to the end of the interconnection in the
overlap region of the first interconnection layer is greater than
the shortest distance from the edge of the via hole contact region
to the interconnection end in the overlap region of the second
interconnection layer, and is no more than 50 .mu.m. Also, the
interconnection resistance of the first interconnection layer is
greater than the interconnection resistance of the second
interconnection layer.
Inventors: |
Umemura, Eiichi; (Tokyo,
JP) |
Correspondence
Address: |
JONES VOLENTINE, L.L.P.
12200 Sunrise Vally Drive, Suite 150
Reston
VA
20191
US
|
Family ID: |
18899918 |
Appl. No.: |
09/892995 |
Filed: |
June 28, 2001 |
Current U.S.
Class: |
439/81 ;
257/E23.145; 257/E23.16 |
Current CPC
Class: |
H01L 23/5226 20130101;
Y10T 428/24917 20150115; H01L 23/53223 20130101; Y10T 428/2495
20150115; H01L 2924/0002 20130101; Y10T 428/24942 20150115; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
439/81 |
International
Class: |
H01R 012/00; H05K
001/00 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 14, 2001 |
JP |
036673/2001 |
Claims
What is claimed is:
1. An interconnection structure comprising: an interlayer
insulating film; and first interconnection layer to which a low
potential is applied and second interconnection layer to which a
high potential is applied, said interlayer insulating film being
interposed between said first interconnection and second
interconnection layers and said first interconnection and second
interconnection layers being electrically connected through a via
hole formed through said interlayer insulating film; wherein
overlap regions including regions facing said via hole are formed
for both said first interconnection and second interconnection
layers; the shortest distance from the edge of the via hole-faced
region to interconnection end in said overlap region of said first
interconnection layer is greater than the shortest distance from
the edge of the via hole-faced region to interconnection end in
said overlap region of said second interconnection layer; and the
interconnection resistance of said first interconnection layer is
greater than the interconnection resistance of said second
interconnection layer.
2. An interconnection structure, according to claim 1, wherein the
shortest distance from the edge of the via hole-faced region to the
interconnection end in said overlap region of said first
interconnection layer is no more than 50 .mu.m.
3. An interconnection structure, according to claim 1, wherein said
first interconnection layer is constituted with metal having a
higher melting point than that constituting said second
interconnection layer for increasing said interconnection
resistance.
4. An interconnection structure, according to claim 1, wherein the
width of said first interconnection layer is narrower than the
width of said second interconnection layer for increasing said
interconnection resistance.
5. An interconnection structure, according to claim 1, wherein said
overlap region of said first interconnection layer is constituted
with metal having a higher melting point than that of said second
interconnection layer for increasing said interconnection
resistance.
6. An interconnection structure, according to claim 1, wherein the
thickness of said first interconnection layer is thinner than the
thickness of said second interconnection layer for increasing said
interconnection resistance.
7. An interconnection structure comprising: an interlayer
insulating film; and first interconnection layer to which a low
potential is applied and second interconnection layer to which a
high potential is applied, said interlayer insulating film being
interposed between said first interconnection and second
interconnection layers and said first interconnection and second
interconnection layers being electrically connected through a via
hole formed through said interlayer insulating film; wherein heater
line is provided and is electrically insulated from said first
interconnection layer and second interconnection layer.
8. An interconnection structure, according to claim 6, wherein
heater line is provided at a position separated by a distance of no
more than 50 .mu.m from the edge of the via hole-faced region of
said second interconnection layer.
9. An interconnection structure, according to claim 6, wherein said
heater line is constituted with a layer of the same material as
said first interconnection layer.
10. An interconnection structure, according to claim 6, wherein the
interconnection width of said heater line is narrower than the
width of said first interconnection layer.
11. An interconnection structure, according to claim 6, wherein the
thickness of said heater line is thinner than the thickness of said
first interconnection layer.
12. An interconnection structure, according to claim 6, wherein
said heater line is constituted with a metal having a higher
melting point than that constituting said first interconnection
layer.
13. An interconnection structure, according to claim 6, wherein at
least the region of said heater line for conducting heat to said
second interconnection layer is constituted with a metal having a
higher melting point than that constituting said first
interconnection layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an interconnection
structure used in semiconductor elements, and more particularly to
a multilayer interconnection structure.
[0003] 2. Description of Related Art
[0004] FIG. 1 shows a typical constitution of an interconnection
structure wherein the upper interconnection layer and lower
interconnection layer are electrically connected through a via
hole.
[0005] Referring to FIG. 1, the lower interconnection layer 102 is
formed on a substrate 100. An interlayer insulating film 104 is
formed on the upper surface of the substrate 100 so as to cover
this lower interconnection layer 102. The upper interconnection
layer 106 is formed on the interlayer insulating film 104. The via
hole 108 is formed in the interlayer insulating film 104. The upper
interconnection layer 106 and lower interconnection layer 102 are
electrically connected through the via hole 108. The inner walls of
the via hole 108 are generally covered with a barrier metal 110.
For example, tungsten (W) 112 is laid on the surface of the barrier
metal 110 and the interior of the hole 108.
[0006] The following structures are known as the upper
interconnection layer 106 and lower interconnection layer 102
respectively: a two-layered structure of Al (aluminum) alloy layer
and high melting point metal layer formed as a barrier metal which
having a melting point higher than that of the Al alloy, or a
three-layered structure of the Al alloy layer held between the high
melting point metal layers. In the example shown in FIG. 1, the
upper interconnection layer 106 and lower layer interconnection 102
are the three-layered structure. Consequently, the lower
interconnection layer 102 has a structure wherein the Al alloy
layer 116 is held between the high melting point metal layer 120a
and 120b. The upper interconnection layer 106 has a structure
wherein the Al alloy layer 114 is held between the high melting
point metal layers 118a and 118b.
SUMMARY OF THE INVENTION
[0007] The interconnection structure according to the present
invention comprises an interlayer insulating film, first
interconnection layer provided on one surface thereof and second
interconnection layer on the other surface thereof. The interlayer
insulating film has formed therethrough a via hole. Voltage is
applied to the interconnection to become the first interconnection
lower potential, the second interconnection higher potential. The
first interconnection layer and second interconnection layer are
established with the interlayer insulating film interposed
therebetween and are electrically connected through the via
hole.
[0008] An overlap region including the region facing (or in contact
with) the via hole is formed in both the first interconnection and
second interconnection layers. In other words, this overlap region
is the region where the first interconnection and second
interconnection layers overlap with the interlayer insulating film
therebetween and the via hole is formed in the interlayer
insulating film within this region.
[0009] A barrier metal is formed in the first interconnection layer
and/or the second interconnection layer, in order to prevent from
moving metal atoms between the interconnection layers. In this type
of interconnection structure, the shortest distance from the edge
of the via hole-faced (or contact) region of the overlap region of
the first interconnection layer to the end of that interconnection
is no more than 50 .mu.m and is longer than the shortest distance
from the edge of the via hole contact region of the overlap region
of the second interconnection layer to the end of that
interconnection. The interconnection resistance of the first
interconnection layer is greater than the interconnection layer
resistance of the second interconnection layer.
[0010] When voltage is applied to this interconnection structure so
that the first interconnection layer is at a low potential and the
second interconnection layer is at a high potential, the amount of
Joule heating due to the current flow is greater in the first
interconnection layer than in the second interconnection layer
within the range of the interconnection thickness used in ordinary
LSI chips, because the interconnection resistance of the first
interconnection layer is greater than that of the second
interconnection layer. Accordingly, the temperature of the first
interconnection layer becomes greater than that of the second
interconnection layer. As a result, the temperature of the overlap
region of both sets of interconnection layers (perimeter of the via
hole-faced (or contact) region) becomes high temperature and the
temperature in the region of the second interconnection layer
(except overlap region) becomes low temperature. Consequently, the
temperature gradient at the boundary between the overlap region and
the second interconnection layer becomes large.
[0011] The migration velocity of the metal forming the
interconnection (also called "interconnection metal") changes
exponentially relative to the temperature. In the interconnection
structure, the migration velocity in the overlap region (high
temperature region) is high and the migration velocity in the
region of the second interconnection layer (low temperature region)
is low. Consequently, the migration velocity drops abruptly because
of the large temperature gradient at the boundary between the
overlap region and the second interconnection layer. Accordingly,
the vicinity of the above-mentioned boundary, wherein the
temperature gradient is large, becomes a barrier to migration.
Effects which are substantially the same as backflow effects can
thereby be attained with this barrier. Accordingly, the progression
of voids, due to movement of the interconnection metal in the
vicinity of the boundary, can be suppressed. Consequently, the EM
resistance of this interconnection layer structure can be
improved.
[0012] The shortest distance from the edge of the via hole contact
region of the overlap region of the first interconnection layer to
the end thereof is greater than the shortest distance from the edge
of the via hole contact region of the overlap region of the second
interconnection layer to the end thereof. As a result, heat
generated in the first interconnection layer can be conducted
efficiently to the second interconnection layer in the overlap
region of the first and second interconnection layers. Since the
shortest distance from the edge of the via hole contact region of
the overlap region of the first interconnection layer to the end
thereof is no more than 50 .mu.m, the boundary of the overlap
region and the region of second interconnection layer only can be
established at a position such that void progression can be
suppressed at an early stage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The foregoing and other objects, features and advantages of
the present invention will be better understood from the following
description taken in connection with the accompanying drawings, in
which:
[0014] FIG. 1 is a schematic diagram of the constitution of the
interconnection structure of the related art in a section through a
line running along the length of the interconnection layer;
[0015] FIG. 2A is a schematic diagram of the constitution of the
interconnection structure relating to the first embodiment of the
present invention in a section through a line running along the
length of the interconnection layer;
[0016] FIG. 2B is a schematic plane view of the disposition of the
interconnection layer in the interconnection structure seen from
above;
[0017] FIG. 2C is a temperature profile along the length of the
interconnection layer during use of the interconnection structure
relating to the first embodiment of the present invention;
[0018] FIG. 3 is a schematic diagram showing cross section of the
interconnection structure relating to the first embodiment of the
present invention;
[0019] FIG. 4 is a diagram of the properties showing measured
results from the first embodiment of the present invention;
[0020] FIG. 5 is a schematic diagram of the constitution of the
interconnection structure relating to a comparative example;
[0021] FIG. 6 is a diagram of the properties showing measured
results from the comparative example;
[0022] FIG. 7A is a schematic diagram of the constitution of the
interconnection structure relating to a second embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0023] FIG. 7B is a schematic plane view of the constitution of the
interconnection structure seen from above;
[0024] FIG. 7C is a temperature profile along the length of the
interconnection layer during use of the interconnection structure
relating to the second embodiment of the present invention;
[0025] FIG. 8A is a schematic diagram of the constitution of the
interconnection structure relating to a third embodiment of the
present invention in a section through a line running along the
length of an interconnection layer;
[0026] FIG. 8B is a temperature profile along the length of the
interconnection layer during use of the interconnection structure
relating to the third embodiment of the present invention;
[0027] FIG. 9A is a schematic diagram of the constitution of the
interconnection structure relating to a fourth embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0028] FIG. 9B is a temperature profile along the length of the
interconnection layer during use of the interconnection structure
relating to the fourth embodiment of the present invention;
[0029] FIG. 10A is a schematic diagram of the constitution of the
interconnection structure relating to a fifth embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0030] FIG. 10B is a schematic plane view of the constitution of
the interconnection layer in the interconnection structure seen
from above;
[0031] FIG. 10C is a temperature profile along the length of an
interconnection layer during use of the interconnection structure
relating to the fifth embodiment of the present invention;
[0032] FIG. 11A is a schematic diagram of the constitution of the
interconnection structure relating to a sixth embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0033] FIG. 11B is a schematic plane view of the constitution of
the interconnection layer in the interconnection structure seen
from above;
[0034] FIG. 11C is a temperature profile along the length of an
interconnection layer during use of the interconnection structure
relating to the sixth embodiment of the present invention;
[0035] FIG. 12A is a schematic diagram of the constitution of the
interconnection structure relating to a seventh embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0036] FIG. 12B is a temperature profile along the length of an
interconnection layer during use of the interconnection structure
relating to the seventh embodiment of the present invention;
[0037] FIG. 13A is a schematic diagram of the constitution of the
interconnection structure relating to an eighth embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0038] FIG. 13B is a schematic plane view of the constitution of
the interconnection layer in the interconnection layer structure
seen from above;
[0039] FIG. 13C is a temperature profile along the length of an
interconnection layer during use of the interconnection structure
relating to the eighth embodiment of the present invention;
[0040] FIG. 14A is a schematic diagram of the constitution of the
interconnection structure relating to a ninth embodiment of the
present invention in a cross section through a line running along
the length of an interconnection layer;
[0041] FIG. 14B is a schematic plane view of the constitution of
the interconnection layer in the interconnection structure seen
from above; and
[0042] FIG. 14C is a temperature profile along the length of an
interconnection layer during use of the interconnection structure
relating to the ninth embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0043] With reference to the drawings, embodiments of the present
invention will be explained below. Moreover, it should be noted
that these drawings show an outline of shapes, sizes, and
arrangement of the constituent elements only to an extent necessary
for appreciating the present invention and consequently, the
present invention is not limited to the examples shown in the
drawings. In the drawings, hatching (slanted lines) showing cross
sections is omitted from all but certain sections. In the plane
views, hatching is used in regions indicating specific constituent
elements in order to make the positional relationships between the
constituent elements easy to understand. In the following
description, an interconnection layer may be called
"interconnection" for short.
[0044] First Embodiment
[0045] The interconnection structure relating to a first embodiment
will be explained with reference to FIGS. 2A to 2C. FIG. 2A is a
cross sectional view of a section along a line in the direction in
which migration progresses (along the length of an interconnection
layer). FIG. 2B is a schematic plane view of the disposition of the
interconnection in the interconnection structure seen from above.
FIG. 2C is a temperature profile of the interconnection in the case
of current flowing in the interconnection structure in FIG. 2A. In
FIG. 2C, the horizontal axis shows the distance along the length of
the interconnection and the vertical axis shows the interconnection
temperature. The distance on the horizontal axis in FIG. 2C
corresponds to the distance from position a to position b in FIG.
2A.
[0046] The interconnection structure 10 relating to the present
invention comprises an interlayer insulating film 12, first
interconnection layer 14 and second interconnection layer 16. The
interlayer insulating film 12 has formed therethrough a via hole
18. The first interconnection layer 14 and second interconnection
layer 16 are formed with the interlayer insulating film 12
interposed therebetween; the interconnection layers 14 and 16 are
electrically connected by the via hole 18. Voltage is applied to
the first interconnection layer 14 such that the potential is low
when the interconnection structure 10 is used. Voltage is applied
to the second interconnection layer 16 such that the potential is
high when the interconnection structure 10 is used. Overlap regions
14a and 16a, including via hole contact regions 14x and 16x, are
formed in the first interconnection layer 14 and second
interconnection layer 16, respectively. The via hole contact
regions mean the regions facing the via hole and is called the via
hole-faced regions.
[0047] In the present embodiment, the first interconnection layer
14 is formed on the semiconductor substrate 20. The interlayer
insulating film 12 is formed on the semiconductor substrate 20 so
as to cover the first interconnection layer 14. The second
interconnection layer 16 is formed on the upper surface of the
interlayer insulating film 12. The first interconnection layer 14
is constituted with a high melting point metal (here, "high melting
point" means that the melting point is greater than that of
aluminum) that does not include aluminum (Al). In this example, the
first interconnection layer 14 is single-metal interconnection of
tungsten (W). The second interconnection layer 16 is layered
interconnection comprising an upper layer 22 constituted by an
alloy layer containing Al as the principal interconnection material
(also called an Al alloy layer) and a lower layer 24 constituted by
a high melting point metal as a barrier metal. In this example, the
lower layer 24 is constituted with a TiN film. The inner walls of
the via hole 18 are covered with the barrier metal 26. Furthermore,
the interior of the via hole 18 is filled with tungsten (W) 28.
[0048] In the overlap regions 14a and 16a of the first
interconnection layer 14 and second interconnection layer 16, the
shortest distance dl from the edge of the via hole contact region
14x of the first interconnection layer 14 to the interconnection
end 14e is greater than the shortest distance d2 from the edge of
the via hole contact region 16x of the second interconnection layer
16 to the interconnection end 16e. d1 is no more than 50 .mu.m (see
FIGS. 2A and 2B).
[0049] d1 is longer than d2 so that heat may be conducted
efficiently from the first interconnection layer 14 with high
interconnection resistance, through the via hole 18, to the second
interconnection layer 16. d1 is no more than 50 .mu.m so that the
boundary 16c between the overlap region 16a of the second
interconnection layer 16 and the region 16b of only the second
interconnection layer is formed at a position such that void
progression can be suppressed at an early stage.
[0050] Voltage is applied to this interconnection structure 10 so
that the first interconnection layer 14 is at a low potential and
the second interconnection layer 16 is at a high potential. Because
the first interconnection layer 14 is constituted with tungsten (W)
having a higher melting point than aluminum, the amount of Joule
heating due to current is greater in the first interconnection
layer 14 than in the second interconnection layer 16. Consequently,
as shown in FIG. 2C, the temperature of the region 14b of only the
first interconnection layer becomes high. Heat generated in the
first interconnection layer 14 is conducted from the overlap region
14a of the first interconnection layer to the via hole 18. This
heat is conducted to the second interconnection layer 16, also
through the interlayer insulating film 12. For this reason, the
temperature of the overlap region 16a of the second interconnection
layer 16 also rises. In the second interconnection layer 16, the
temperature of the region 16b outside the overlap region, is low.
In this case, the temperature distribution from the overlap region
14a of the first interconnection layer in a direction towards the
overlap region 16a of the second interconnection layer is as
follows. From the starting point of the overlap region 14a to the
end point of the overlap region 14a, the temperature gradually
falls and the temperature gradient is maximum in the vicinity of
that end point. In the second interconnection layer region, the
temperature falls with increasing distance from the overlap region
16a and gradually becomes a uniform temperature lower than that of
the first interconnection layer.
[0051] When current flows in the interconnection structure 10,
migration of Al occurs within the second interconnection layer 16.
Voids are thus created from one end 16e of the second
interconnection layer 16 and the voids progress towards the other
end.
[0052] The migration velocity of the Al changes exponentially in
relation to temperature.
[0053] In the second interconnection layer 16, as discussed above,
the temperature gradient in the vicinity of the boundary 16c
between the overlap region 16a and the region 16b outside the
overlap region is maximum.
[0054] Consequently, this temperature gradient can be used as a
barrier to migration. In other words, because the migration
velocity becomes high in high-temperature regions and the migration
velocity is low in low temperature regions, the migration velocity
of the Al can be abruptly reduced in the vicinity of the
above-mentioned boundary 16c. Since this is substantially the same
effect as the backflow effect, this can suppress void progression.
As a result, an increase in interconnection resistance can be
suppressed. Consequently, this interconnection structure 10 can
have improved EM resistance compared to conventional
structures.
FIRST EXAMPLE
[0055] Here, a first example is provided as a specific example of
the first embodiment and the effects are shown more clearly through
comparison with a comparative example.
[0056] FIG. 3 shows the constitution of the interconnection in the
first example. Referring to FIG. 3, as explained with the first
embodiment, the tungsten (W) film is formed as the first
interconnection layer 14 on the semiconductor substrate 20. The
interlayer insulating film (for example, an SiO.sub.2 film) 12 is
formed so as to cover the first interconnection layer 14. Layered
interconnection of a TiN film 24 and an Al alloy layer 22 is formed
as the second interconnection layer 16 on the upper surface of the
interlayer insulating film 12. Here, the second interconnection
layer 16 is formed in connection with the via hole 18. The inner
walls of the via hole 18 and the lower layer of the second
interconnection layer 16 are covered with the TiN films 24 and 26
of a barrier metal. The material embedded or buried in the via hole
18 and the upper layer of the second interconnection layer
connected thereto is constituted with Al alloy layers 22 and 28.
Due to the presence of the barrier metal 24 and 26, the
interconnection metal (for example, Al) does not migrate from the
second interconnection layer 16 to the first interconnection layer
14.
[0057] Here, the interval between the via holes 18 in the
interconnection structure relating to the first embodiment is 100
.mu.m.
[0058] Current was passed through this type of interconnection
structure under the following test conditions: J (current density)
of 2.times.10.sup.6 A/cm.sup.2 and T (interconnection temperature)
of 200 .degree. C. Current was applied for 300 hours. The
interconnection resistance of the entire interconnection structure
at the start of current application was measured as R.sub.0 and the
interconnection resistance at any time up to 300 hours as R. FIG. 4
shows these measurement results. In FIG. 4, the passage of time (0
to 300 hours) is shown on the horizontal axis and the percentage
increase in interconnection layer resistance at any time with
respect to the interconnection resistance at the start of current
application (R/R.sub.0.times.100 (%)) is shown on the vertical
axis.
[0059] Moreover, FIG. 4 shows the results of conducting the same
type of measurements on a plurality of interconnection structures
having the same constitution as the first example.
Comparative Example
[0060] The example for comparison with the first example will be
explained next with reference to FIGS. 5 and 6.
[0061] FIG. 5 is an example of the constitution of an
interconnection structure according to art relating to the present
invention. The first interconnection layer 30 is formed on the
semiconductor substrate 20. The interlayer insulating film 32 is
formed so as to cover this first interconnection layer 30. The
second interconnection layer 34 is formed on the interlayer
insulating film 32. A via hole 36 for electrically connecting the
second interconnection layer 34 and first interconnection layer 30
is formed in the interlayer insulating film 32. The interval
between the via holes is 100 .mu.m as in the first example. The
second interconnection layer 34 is formed integrally with the via
hole 36, as in the first example. In other words, the inner walls
of the via hole 36 and the lower layer of the second
interconnection layer 34 are covered with a TiN film 38 of a
barrier metal. The material embedded or buried in the via hole and
the upper layer of the second interconnection layer 34 is formed
with an Al alloy layer 40. In this way, the principal constitution
of the interconnection structure is the same as in the first
example, but in the comparative example, the first interconnection
layer comprises layered interconnection of an Al alloy layer 42 and
barrier metal (TiN film) 44 and 46 with this Al alloy layer 42
therebetween.
[0062] Measurements were made of this interconnection structure
relating to the comparative example under the same conditions as
for the first example.
[0063] FIG. 6 shows the measurement results. In FIG. 6, the passage
of time (0 to 200 hours) is shown on the horizontal axis and the
percentage of the interconnection resistance (R) at any time with
respect to the interconnection resistance at the start of current
application (R.sub.0) (R/R.sub.0.times.100 (%)) is shown on the
vertical axis. As with the first example, FIG. 6 shows the results
of conducting the same type of measurements on a plurality of
interconnection structures having the same constitution as the
comparative example.
[0064] The measurement results for the first example and the
measurement results for the comparative example are compared with
reference to FIGS. 4 and 6.
[0065] As a result, in the interconnection structure relating to
the first example, the percentage increase in interconnection
resistance even after 300 hours was 10% or less, while in the
interconnection structure relating to the comparative example, the
percentage increase in interconnection resistance for the entire
interconnection structure exceeded 10% after 140 hours.
[0066] For the interconnection structure in the first example, the
percentage increase in interconnection resistance could be kept to
one half or less that of the interconnection resistance of the
interconnection structure in the comparative example. In other
words, it could be confirmed that a great improvement in the EM
resistance of the interconnection was contrived with the
interconnection structure relating to the present invention.
[0067] Second Embodiment
[0068] The interconnection structure 50 relating to a second
embodiment will be explained with reference to FIGS. 7A to 7C. The
principal constitution of the interconnection structure 50 is the
same as in the first embodiment. In this example, the width (w1) of
the first interconnection layer 14 is made narrower than the width
(w2) of the second interconnection layer 16 for increasing the
interconnection resistance of the first interconnection layer
14.
[0069] Points at variance with the first embodiment are explained
next; a detailed explanation of similar points is omitted.
[0070] FIGS. 7A, 7B and 7C are a cross sectional view, plane view
and temperature profile, respectively, of the interconnection
structure 50 like those shown in FIGS. 2A, 2B and 2C, respectively.
Specifically, FIG. 7C is a temperature profile in the case of
passing current through the interconnection structure relating to
this embodiment. The distance on the horizontal axis in FIG. 7C
corresponds to the distance from position a to position b in FIG.
7A.
[0071] Referring to FIG. 7A, the interconnection structure 50 in
the present embodiment has the first interconnection layer 14
formed on the semiconductor substrate 20 as in the first
embodiment. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18 is formed in the interlayer insulating film 12 in
overlap regions 14a and 16a of the first interconnection layer 14
and second interconnection layer 16.
[0072] In this embodiment, the first interconnection layer 14 and
second interconnection layer 16 are both layered interconnection of
upper layers 52 and 22 comprising an alloy layer including Al and
lower layers 54 and 24 comprising TiN film. The inner walls of the
via hole 18 are covered with barrier metal 26. The interior of the
via hole 18 is filled with tungsten (W) 28. The first
interconnection layer 14 and second interconnection layer 16 are
thereby electrically connected.
[0073] In this embodiment, as shown in FIG. 7B, the width (w1) of
the first interconnection layer 14 is formed to be narrower than
the width (w2) of the second interconnection layer 16. w1 is
preferably from 10% to 80% of w2. Accordingly, a temperature
difference between the overlap region 16a of the second
interconnection layer 16 and the region 16b outside the overlap
region can be produced in the case where current flows through the
interconnection structure 50.
[0074] As in the first embodiment, voltage is applied to this
interconnection structure 50 so that the first interconnection
layer 14 is at a low potential and the second interconnection layer
16 is at a high potential. At this time, because the width (w1) of
the first interconnection layer 14 is narrower than the width (w2)
of the second interconnection layer 16, the interconnection
resistance of the first interconnection layer 14 becomes greater
than that of the second interconnection layer 16. As a result, the
amount of Joule heating due to the current flow is greater in the
first interconnection layer 14 than in the second interconnection
layer 16 and therefore the interconnection temperature becomes
higher in the first interconnection layer 14. Accordingly, as shown
in FIG. 7C, in the overlap regions 14a and 16a of the first
interconnection layer 14 and second interconnection layer 16, the
temperature becomes high because heat is conducted from the first
interconnection layer 14 through the via hole 18. Also, the heat is
conducted through the interlayer insulating film 12 to the second
interconnection layer 16. Meanwhile, the region 16b outside the
overlap region of the second interconnection layer 16 is at a low
temperature. Consequently, in the second interconnection layer 16,
the temperature gradient in the vicinity of the boundary 16c
between the overlap region 16a and the region 16b outside the
overlap region is the maximum. In other words, the temperature
distribution in the second embodiment is the temperature
distribution as explained with the first embodiment.
[0075] When voltage is applied to (current flows through) this
interconnection structure 50, migration of the Al atoms, that are
the material constituting the interconnection, occurs. Because of
this migration, voids occur at one end 16e of the second
interconnection layer 16 and these voids progress towards the other
end. In the second interconnection layer 16 in the present
embodiment, as in the first embodiment, the migration velocity of
the Al changes abruptly because of the temperature gradient (see
FIG. 7C) of the boundary 16c between the overlap region 16a and the
region 16b outside the overlap region. This temperature gradient
therefore becomes a barrier to migration. Accordingly, the same
type of effects as the backflow effect can be substantially
achieved. Consequently, this interconnection structure 50 can have
more than double the EM resistance of conventional structures.
[0076] Third Embodiment
[0077] The interconnection structure relating to a third embodiment
will be explained with reference to FIGS. 8A and 8B. The principal
constitution of the interconnection structure is the same as in the
first embodiment. In this embodiment, the overlap region of the
first interconnection layer is constituted with a metal having a
higher melting point than the second interconnection layer.
[0078] Points at variance with the first and second embodiments are
explained next; a detailed explanation of similar points is
omitted.
[0079] FIGS. 8A and 8B are a cross sectional view and temperature
profile, respectively, of the interconnection structure 50 like
those shown in FIGS. 2A and 2C, respectively. The distance on the
horizontal axis in FIG. 8B corresponds to the distance from
position a to position b of the interconnection structure in FIG.
8A.
[0080] Referring to FIG. 8A, the interconnection structure 60 in
the present embodiment has the first interconnection layer 14
formed on the semiconductor substrate 20 as in the first
embodiment. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18 is formed in the interlayer insulating film 12 in
overlap regions 14a and 16a of the first interconnection layer 14
and second interconnection layer 16.
[0081] In this embodiment, the region 14b outside the overlap
region of the first interconnection layer 14 and second
interconnection layer 16, for example, are both layered
interconnection of upper layers 52 and 22 comprising an alloy layer
including Al and lower layers 54 and 24 comprising TiN film. The
overlap region 14a of the first interconnection layer 14 is
interconnection of only the lower layer 54 comprising TiN film. The
overlap region 14a and region 14b outside the overlap region are
connected by the lower layer 54 and have a constitution wherein the
upper layer 52 is partially removed from only the overlap region
14a.
[0082] The inner walls of the via hole 18 are covered with barrier
metal 26. The interior of the via hole 18 is filled with tungsten
(W) 28. Consequently, the TiN film 54 of the first interconnection
layer 14 and the lower layer 24 of the second interconnection layer
16 are in contact with the via hole 18.
[0083] As in the first embodiment, voltage is applied to the
interconnection structure 60 so that the first interconnection
layer 14 is at a low potential and the second interconnection layer
16 is at a high potential. The overlap region 14a of the first
interconnection layer 14 is now constituted with only a TiN film
54. Consequently, the overlap region 14a has a higher
interconnection resistance than the region 14b outside the overlap
region, comprising the upper layer 52 and lower layer 54, and than
the second interconnection layer 16. As a result, the amount of
Joule heating occurring in the overlap region 14a of the first
interconnection layer 14 becomes high. For this reason, the
interconnection temperature of the overlap region 14a becomes high.
This heat is conducted through the via hole 18 from the overlap
region 14a of the first interconnection layer 14 to the overlap
region 16a of the second interconnection layer 16. Consequently, a
large temperature gradient (FIG. 8B) occurs at the boundary between
the overlap region 16a and the region 16b outside the overlap
region, because the overlap region 16a of the second
interconnection layer 16 is at a high temperature. In other words,
the temperature distribution in the overlap regions 14a and 16a
from the first interconnection layer 14 towards the second
interconnection layer 16 increases abruptly at the start of the
overlap of the first interconnection layer 14 and second
interconnection layer 16, becomes the maximum temperature
(temperature gradient of 0) in the middle, and at the end of the
overlap, becomes approximately equal to the temperature at the
start of the overlap. The temperature gradient is maximum at the
end of the overlap. With the increase in distance from the overlap
region 16a, the temperature of the second interconnection layer
drops and at the region 16b separated from the overlap region,
becomes a constant temperature lower than the temperature of the
portion 14b of the first interconnection layer.
[0084] When voltage is applied to this interconnection structure
60, migration of the Al atoms occurs in the upper layer 22 of the
second interconnection layer 16. Due to this migration, voids occur
at one end 16e of the second interconnection layer 16 and these
voids progress towards the other end. In the present embodiment,
the migration velocity of the Al drops abruptly at that boundary
because of the temperature gradient of the boundary 16c between the
overlap region 16a and the region 16b outside the overlap region.
In this way, this temperature gradient becomes a barrier to
migration. Accordingly, the same type of effects as the backflow
effect can be substantially achieved. Consequently, this
interconnection structure 60 can have better EM resistance than
conventional structures.
[0085] Fourth Embodiment
[0086] The interconnection structure 70 relating to a fourth
embodiment is explained next with reference to FIGS. 9A and 9B. The
principal constitution of the interconnection structure 70 is the
same as in the first embodiment. In this embodiment, the first
interconnection layer 14 is made thinner than the second
interconnection layer 16.
[0087] Points at variance with the first through third embodiments
are explained next; a detailed explanation of similar points is
omitted.
[0088] FIGS. 9A and 9B show a diagram and temperature profile,
respectively, which are similar to those shown in FIGS. 8A and 8B,
respectively. The distance on the horizontal axis in FIG. 9B
corresponds to the distance from position a to position b of the
interconnection structure in FIG. 9A.
[0089] Referring to FIG. 9A, the interconnection structure 70 in
the present embodiment has the first interconnection layer 14
formed on the semiconductor substrate 20 as in the first
embodiment. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18 is formed in the interlayer insulating film 12 in
overlap regions 14a and 16a of the first interconnection layer 14
and second interconnection layer 16.
[0090] In this embodiment, for example, the first interconnection
layer 14 and second interconnection layer 16 are both layered
interconnection of upper layers 52x and 22 comprising an alloy
layer including Al and lower layers 54 and 24 comprising TiN film.
The inner walls of via hole 18 are covered with barrier metal 26.
The surface of the barrier metal 26 in the via hole 18 is further
filled with tungsten (W) 28. Accordingly, the first interconnection
layer 14 and second interconnection layer 16 are electrically
connected by means of the via hole 18.
[0091] In this embodiment, the thickness (t1) of the Al alloy layer
52x, which is the upper layer of the first interconnection layer
14, is formed to be thinner than the thickness (t2) of the Al alloy
layer 22 of the second interconnection layer 16. The thickness (t1)
of the Al alloy layer 52x of the first interconnection layer 14 is
preferably from 10% to 80% of the thickness (t2) of the Al alloy
layer 22 of the second interconnection layer 16. Accordingly, a
temperature difference between the overlap region 16a of the second
interconnection layer 16 and the region 16b outside the overlap
region can be produced in the case where current flows through the
interconnection structure 70.
[0092] As in the first embodiment, voltage is applied to this
interconnection structure 70 so that the first interconnection
layer 14 is at a low potential and the second interconnection layer
16 is at a high potential. At this time, because the first
interconnection layer 14 is thinner than the second interconnection
layer 16, the interconnection resistance of the first
interconnection layer 14 becomes greater than that of the second
interconnection layer 16. As a result, the amount of Joule heating
due to the current flow is greater in the first interconnection
layer 14 than in the second interconnection layer 16 and therefore
the interconnection temperature becomes higher in the first
interconnection layer 14. Accordingly, as shown in FIG. 9B, in the
overlap regions 14a and 16a of the first interconnection layer 14
and second interconnection layer 16, the temperature becomes high
because heat is conducted from the first interconnection layer 14
through the via hole 18. Meanwhile, the region 16b outside the
overlap region of the second interconnection layer 16 is at a low
temperature. Consequently, in the second interconnection layer 16,
the temperature gradient in the vicinity of the boundary 16c
between the overlap region 16a and the region 16b outside the
overlap region becomes large. In this way, the same temperature
distribution as in the case of the first embodiment is obtained in
the case of the fourth embodiment.
[0093] Consequently, as in the first embodiment, the vicinity of
the boundary 16c is a barrier to migration and therefore, the same
type of effects as the backflow effect can also be achieved with
the interconnection structure 70 relating to the fourth embodiment.
Consequently, an interconnection structure 70 with EM resistance
superior to that of conventional interconnection structures is
obtained.
[0094] Fifth Embodiment
[0095] The interconnection structure 80 relating to a fifth
embodiment is explained with reference to FIGS. 10A to 10C.
[0096] FIGS. 10A, 10B and 10C are a cross sectional view, plane
view and temperature profile, respectively, of the interconnection
structure 50 which are similar to those shown in FIGS. 2A, 2B and
2C, respectively. Specifically, FIG. 10C is a temperature profile
in the case of passing current through the interconnection
structure relating to this embodiment. FIG. 10C is an
interconnection temperature profile when using (applying voltage
to) the interconnection structure 80 relating to this
embodiment.
[0097] The interconnection structure 80 in the present embodiment
comprises an interlayer insulating film 12, first interconnection
layer 14 and second interconnection layer 16. The interlayer
insulating film 12 has formed therethrough a via hole 18. The first
interconnection layer 14 and second interconnection layer 16 are
formed with the interlayer insulating film 12 interposed
therebetween; the interconnections 14 and 16 are electrically
connected by the via hole 18. The first interconnection layer 14 is
the interconnection to which voltage is applied such that the
potential is low when the interconnection structure 80 is used; and
the second interconnection layer 16 is the interconnection to which
voltage is applied such that the potential is high. Overlap regions
14a and 16a including via hole 18 contact regions 14x and 16x are
formed in the first interconnection layer 14 and second
interconnection layer 16, respectively.
[0098] In the present embodiment, the first interconnection layer
14 is formed on the semiconductor substrate 20, as in the first
embodiment. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover the first interconnection
layer 14. The second interconnection layer 16 is formed on the
upper surface of the interlayer insulating film 12.
[0099] As in the first embodiment, the first interconnection layer
14 is constituted with single-metal interconnection of tungsten
(W), as the high melting point metal which does not include Al. The
second interconnection layer 16 is layered interconnection
comprising an upper layer 22 constituted by an alloy layer (Al
alloy layer) including aluminum as the principal interconnection
material and a lower layer 24 constituted with a high melting point
metal (TiN film) of a barrier metal. The inner walls of the via
hole 18 are covered with the barrier metal 26. The surface of the
barrier metal 26 in this hole 18 is filled with tungsten (W) 28
(FIG. 1OA).
[0100] So that heat can be applied to the second interconnection
layer 16 at a position within 50 .mu.m from the edge of the region
16x in contact with the via hole 18, heater line 82 is established
and electrically insulated from the first interconnection layer 14
and second interconnection layer 16.
[0101] In the present embodiment, the heater line 82 is constituted
with a layer of the same material as the first interconnection
layer 14.
[0102] In the present embodiment, the heater line 82 comprising
tungsten (W) is formed on the lower side, of the second
interconnection layer 16, that is the upper surface of the
semiconductor substrate 20. The heater line 82 is formed at a
position no more than 50 .mu.m from the via hole contact regions
14x and 16x of the first interconnection layer 14 and second
interconnection layer 16. In this example, the heater line 82 is
provided so that the length of this heater line 82 is perpendicular
to the length of the second interconnection layer 16 (FIGS. 10A and
10B).
[0103] The position at which the heater line 82 is formed is no
more than 50 .mu.m from the edge of the via hole contact region 16x
in order that the progression of voids in the second
interconnection layer be suppressed within this distance. If this
distance is no more than 50 .mu.m, the increase in interconnection
resistance of the second interconnection layer 16 can be kept
within tolerance.
[0104] Voltage is applied to the interconnection structure 80 so
that the first interconnection layer 14 is at a low potential and
second interconnection layer 16 is at a high potential. In the
present embodiment, current flows through the heater line 82 as
well. Since the first interconnection layer 14 is constituted with
tungsten (W) which is a high melting point metal, the
interconnection resistance is higher than the second
interconnection layer 16 which is constituted with a TiN film 24
and an Al alloy layer 22. For this reason, the interconnection
temperature of the first interconnection layer 14 becomes greater
than the interconnection temperature of the second interconnection
layer 16 with the application of the above-mentioned voltage. The
interconnection temperature of the heater line 82 becomes high
because this interconnection is constituted with the same material
as the first interconnection layer 14. When voltage is applied, the
interconnection in the interconnection structure 80 is at a
temperature like that above, and therefore the interconnection
temperature characteristics as shown in FIG. 10C are attained. The
horizontal axis in FIG. 1C shows the distance along the length of
the interconnection. This distance corresponds to the distance from
the position a to position b in FIG. 10A.
[0105] Referring to FIG. 10C, the region 14b and the overlap region
14a of the first interconnection layer 14 are high in temperature
as in the first embodiment. The heat from the overlap region 14a of
the first interconnection layer 14 is conducted to the overlap
region 16a of the second interconnection layer 16 from the via hole
18; the overlap region 16a of the second interconnection layer 16
thereby also becomes high in temperature. Meanwhile, the region 16b
outside the overlap region of the second interconnection layer 16
is low in temperature. The region 82a to which heat is conducted
from the heater line 82 becomes high in temperature. Consequently,
in the present embodiment, as in the first embodiment, the large
temperature gradient is formed in the second interconnection layer
16 near the boundary 16c between the overlap region 16a and region
16b outside the overlap region. The temperature distributions of
the first interconnection layer and second interconnection layer
become the same distributions as in the case of the first
embodiment in overlap regions 14a, 16a and the vicinity thereof.
Furthermore, in this embodiment, in the region 82a to which heat is
conducted from the heater line 82, a large temperature change
occurs wherein the temperature becomes higher than in the
surrounding region. Accordingly, this temperature gradient and
region of temperature change are a two-stage barrier which reduces
the velocity of the migration of Al produced in the upper layer 22
of the second interconnection layer 16. Consequently, because
effects which are substantially the same as the backflow effect are
imparted to the second interconnection layer 16, the increase in
interconnection resistance is prevented because void progression
can be suppressed and the EM resistance can be improved.
[0106] Sixth Embodiment
[0107] The interconnection structure 85 relating to a sixth
embodiment will be explained with reference to FIGS. 11A to
11C.
[0108] FIGS. 11A, 11B and 11C are a cross sectional view, plane
view and temperature profile, respectively, which are similar to
those shown in FIGS. 10A, 10B and 10C, respectively.
[0109] The principal constitution of the interconnection structure
85 is the same as the conventional structure. Referring to the
FIGS. 11A and 11B, the first interconnection layer 14 is formed on
the semiconductor substrate 20. The interlayer insulating film 12
is formed on the semiconductor substrate 20 so as to cover this
first interconnection layer 14. The second interconnection layer 16
is formed on the upper surface of the interlayer insulating film
12. The via hole 18, electrically connecting the first
interconnection layer 14 and second interconnection layer 16, is
formed in the interlayer insulating film 12. In this embodiment,
the first interconnection layer 14 and second interconnection layer
16 are both layered interconnection of lower layers 88 and 24
comprising TiN film and upper layers 86 and 22 comprising an Al
alloy layer. The inner walls of the via hole 18 are covered with
the TiN film 26 of a barrier metal. The surface of the TiN film 26
in the via hole 18 is filled with tungsten (W) 28 (FIG. 11A).
[0110] In the present embodiment, as in the fifth embodiment,
heater line 87 is formed and electrically insulated from the first
interconnection layer 14 and second interconnection layer 16, so
that heat can be applied to the second interconnection layer 16 at
a position within 50 .mu.m from the edge of the region 16x in
contact with the via hole 18. The heater line 87 is constituted
with a layer of the same material as the first interconnection
layer 14 and second interconnection layer 16.
[0111] In the present embodiment, heater line 87 comprising a TiN
film 87x and Al alloy layer 87y is formed on the lower side of the
second interconnection layer 16 that is the upper surface of the
semiconductor substrate 20 (see FIG. 11A). In the present
embodiment, the width (wH) of this heater line 87 is made narrower
than the width (w1) of the first interconnection layer 14 (see
FIGS. 11A and 11B), and therefore the interconnection resistance of
the heater line 87 is greater than the interconnection resistance
of the first interconnection layer 14 and the second
interconnection layer 16. Consequently, when voltage is applied to
this interconnection structure 85 so that the first interconnection
layer 14 and heater line 87 are at a low potential and the second
interconnection layer 16 is at a high potential, the
interconnection temperatures show the temperature characteristics
as in FIG. 11C. The distance along the length of the
interconnection on the horizontal axis in FIG. 11C corresponds to
the distance from position a to position b in FIG. 11A.
[0112] Referring to FIG. 11C, the region 14b of only the first
interconnection layer and the region 16b of only the second
interconnection layer are at low temperatures. The overlap regions
14a and 16a of the first interconnection layer 14 and second
interconnection layer 16 are at low temperatures; however, the heat
generated in the first interconnection layer 14 is conducted to the
second interconnection layer 16 through the via hole 18 and
therefore the temperatures rise somewhat. Consequently, in this
case, the temperature distributions of the overlap regions 14a and
16a themselves achieve the temperature distribution which is high
in the central portions of the overlap regions, as in the
description of the third embodiment. However, because the heater
line 87 formed on the lower side of the second interconnection
layer 16 is at a high temperature, the heat generated is conducted
to the vicinity of the position where the second interconnection
layer 16 is provided (a position no more than 50 .mu.m from the via
hole contact region 16x) As explained with the fifth embodiment, a
region of great temperature change 87a is formed in the second
interconnection layer 16 and therefore, this temperature change
region 87a is a barrier which reduces the velocity of the migration
of Al produced in the upper layer 22 of the second interconnection
layer 16. Consequently, because effects which are substantially the
same as the backflow effect can be imparted to the second
interconnection layer 16, the increase in interconnection
resistance is prevented because void progression can be suppressed
and the EM resistance can be improved.
[0113] Seventh Embodiment
[0114] The interconnection structure 90 relating to a seventh
embodiment will be explained with reference to FIGS. 12A and
12B.
[0115] FIGS. 12A and 12B are a cross sectional view and temperature
profile, respectively, which are similar to those shown in FIGS.
11A and 11C, respectively.
[0116] The principal constitution of the interconnection structure
is the same as the conventional structure. Referring to FIG. 12A,
the first interconnection layer 14 is formed on the semiconductor
substrate 20. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18, electrically connecting the first interconnection
layer 14 and second interconnection layer 16, is formed in the
interlayer insulating film 12. In this embodiment, as in the sixth
embodiment, the first interconnection layer 14 and second
interconnection layer 16 are both layered interconnection of lower
layers 88 and 24 comprising TiN film and upper layers 86 and 22
comprising an Al alloy layer. The inner walls of the via hole 18
are covered with the TiN film 26 of a barrier metal. The surface of
the TiN film 26 of the inner walls of the via hole 18 is filled
with tungsten (W) 28 (FIG. 12A).
[0117] In the present embodiment, as in the fifth embodiment,
heater line 92 is established and electrically insulated from the
first interconnection layer 14 and second interconnection layer 16,
so that heat can be applied to the second interconnection layer 16
at a position within 50 .mu.m from the edge of the region 16x in
contact with the via hole 18. The heater line 92 is constituted
with a layer of the same material as the first interconnection
layer 14 and second interconnection layer 16.
[0118] In the present embodiment, heater line 92 comprising a TiN
film 92x and Al alloy layer 92y is formed on the lower side of the
second interconnection layer 16 that is the upper surface of the
semiconductor substrate 20 (FIG. 12A). This heater line 92 is
thinner than the thickness of the first interconnection layer 14
(FIG. 12A). Specifically, the thickness (tH) of the Al alloy layer,
which is the upper layer 92y of the heater line 92, is thinner than
the thickness (t1) of the upper layer 86 of the first
interconnection layer 14. Therefore the interconnection resistance
of the heater line 92 is greater than the interconnection
resistance of the first interconnection layer 14 and the second
interconnection layer 16. Consequently, when voltage is applied to
this interconnection structure 90 so that the first interconnection
layer 14 and heater line 92 are at a low potential and the second
interconnection layer 16 is at a high potential, current flows in
the interconnection structure 90. The interconnection temperatures
at this time show the temperature characteristics as in FIG. 12B.
The distance along the length of the interconnection on the
horizontal axis in FIG. 12B corresponds to the distance from
position a to position b in FIG. 12A.
[0119] Referring to FIG. 12B, the same temperature distribution is
attained as in the case of the sixth embodiment explained with
reference to FIG. 11C. In other words, the region 14b of the first
interconnection layer only and the region 16b of the second
interconnection layer only are at low temperatures. Since some heat
is conducted from the first interconnection layer 14 to the second
interconnection layer 16 through the via hole 18, the temperature
rises slightly in the overlap regions 14a and 16a of the first
interconnection layer 14 and second interconnection layer 16.
Because the heater line 92 formed on the lower side of the second
interconnection layer 16 is at a high temperature due to large
interconnection resistance, the heat generated there is conducted
to the vicinity of the position where the second interconnection
layer 16 is established (a position no more than 50 .mu.m from the
via hole contact region 16x). Because a region of great temperature
change 92a is formed in the second interconnection layer 16, this
temperature change region 92a provides a barrier which reduces the
velocity of the migration of Al produced in the upper layer 22 of
the second interconnection layer 16. Consequently, effects which
are substantially the same as the backflow effect can be imparted
to the second interconnection layer 16. Accordingly, the increase
in interconnection resistance is prevented because void progression
can be suppressed and the EM resistance can be improved.
[0120] Eighth Embodiment
[0121] The interconnection structure 95 relating to the eighth
embodiment will be explained with reference to FIGS. 13A to
13C.
[0122] FIGS. 13A, 13B and 13C show a diagram, plane view and
temperature profile, respectively, which are similar to those shown
in FIGS. 11A, 11B and 11C, respectively.
[0123] The principal constitution of the interconnection structure
95 is similar to the conventional structure. In FIGS. 13A and 13B,
the first interconnection layer 14 is formed on the semiconductor
substrate 20. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18, electrically connecting the first interconnection
layer 14 and second interconnection layer 16, is formed in the
interlayer insulating film 12. In this embodiment, as in the sixth
embodiment, the first interconnection layer 14 and second
interconnection layer 16 are both layered interconnection of lower
layers 88 and 24 comprising TiN film and upper layers 86 and 22
comprising an Al alloy layer. The inner wall of the via hole 18 is
covered with the TiN film 26. The surface of the TiN film 26 in the
via hole 18 is filled with tungsten (W) 28 (FIG. 13A).
[0124] In the present embodiment, as in the fifth embodiment,
heater line 96 is provided, while being electrically insulated from
the first interconnection layer 14 and second interconnection layer
16, at a position on the semiconductor substrate 20 where the
heater line 96 can heat the second interconnection layer 16, and
that is a position separated from the edge of the region 16x in
contact with the via hole 18 by a distance of 50 .mu.m. In the
present embodiment, the heater line 96 is formed as a layer of a
high melting point metal having a melting point higher than that of
Al. Consequently, the TiN film used as the lower layers 88 and 24
of the first interconnection layer 14 and second interconnection
layer 16 is formed, as the heater line 96, on the lower side of the
second interconnection layer 16 that is the upper surface of the
semiconductor substrate 20 (FIG. 13A). The heater line 96 is formed
on the substrate 20 so that the longitudinal direction thereof is
orthogonal to the direction along the length of the interconnection
(FIG. 13B).
[0125] Consequently, since the interconnection resistance of the
heater line 96 is greater than the interconnection resistance of
the first interconnection layer 14 and second interconnection layer
16, current flows through the interconnection structure 95 when a
voltage is applied to this interconnection structure 95 so that the
first interconnection layer 14 and heater line 96 are at a low
potential and the second interconnection layer 16 is at a high
potential. The interconnection temperature at this time shows the
temperature characteristics as in FIG. 13C. The distance along the
length of the interconnection on the horizontal axes in FIG. 13C
corresponds to the distance from position a to position b in FIG.
13A.
[0126] Referring to FIG. 13C, the same temperature distribution as
explained with the sixth and seventh embodiments is attained. In
other words, the region 14b of the first interconnection layer only
and the region 16b of the second interconnection layer only are at
low temperatures. In the overlap regions 14a and 16a of the first
interconnection layer 14 and second interconnection layer 16, the
temperature rises by a certain extent since the heat is conducted
from the first interconnection layer 14 to the second
interconnection layer 16 through the via hole 18. Since the heater
line 96 formed on the lower side of the second interconnection
layer 16 is at a high temperature because of its large
interconnection resistance, the heat generated there is conducted
to the vicinity of the position where the second interconnection
layer 16 is provided (position separated from the via hole 18
contact region 16x by a distance of 50 .mu.m or less), and a region
of great temperature change 96a is formed in the second
interconnection layer 16. This temperature change region 96a
becomes a barrier which reduces the velocity of the migration of Al
produced in the upper layer 22 of the second interconnection layer
16. Consequently, effects similar to the backflow effect can be
imparted to the second interconnection layer 16. Since void
progression can thus be suppressed, the increase in interconnection
resistance can be prevented and the EM resistance can be
improved.
[0127] Ninth Embodiment
[0128] The interconnection structure 97 according to the ninth
embodiment will be explained with reference to FIGS. 14A to
14C.
[0129] FIGS. 14A, 14B and 14C show a diagram, plane view and
temperature profile, respectively, which are similar to those shown
in FIGS. 13A, 13B and 13C, respectively.
[0130] The principal constitution of the interconnection structure
97 is the same as the conventional structure. In FIGS. 14A and 14B,
the first interconnection layer 14 is formed on the semiconductor
substrate 20. The interlayer insulating film 12 is formed on the
semiconductor substrate 20 so as to cover this first
interconnection layer 14. The second interconnection layer 16 is
formed on the upper surface of the interlayer insulating film 12.
The via hole 18, electrically connecting the first interconnection
layer 14 and second interconnection layer 16, is formed in the
interlayer insulating film 12. In this embodiment, as in the sixth
embodiment, the first interconnection layer 14 and second
interconnection layer 16 are both layered interconnection of lower
layers 88 and 24 comprising TiN film and upper layers 86 and 22
comprising an Al alloy layer. The inner walls of the via hole 18
are covered with the TiN film 26. The surface of the TiN film 26 in
the hole 18 is filled with tungsten (W) 28 (FIG. 14A).
[0131] In the present embodiment, as in the fifth embodiment,
heater line 98 is formed, while being electrically insulated from
the first interconnection layer 14 and second interconnection layer
16, at a position on the semiconductor substrate 20 where the
heater line 98 can heat the second interconnection layer 16, and
that is a position no more than 50 .mu.m from the edge of the
regions 14x and 16x in contact with the via hole 18. The heater
line 98 is formed on the substrate 20 as a laminated layer so that
the lengthwise direction is perpendicular to the direction along
the length of the interconnection (FIG. 14B). In the present
embodiment, the region 98b of the heater line 98, excluding the
region 98a for conducting heat to the second interconnection layer
16, is formed with the same material as the first interconnection
layer 14. In other words, this is a laminated layer of a lower
layer 98x comprising TiN film and an upper layer 98y comprising an
Al alloy layer. The region 98a for conducting heat to the second
interconnection layer is a region comprising only the TiN film 98x
with the upper layer removed, and therefore the region 98a
comprising only the TiN film 98x of the heater line 98 has an
interconnection resistance greater than that of the other region
98b (FIG. 14B). Consequently, current flows in the interconnection
structure 97 when voltage is applied to this interconnection
structure 97 so that the first interconnection layer 14 and heater
line 98 are at a low potential and the second interconnection layer
16 is at a high potential. The interconnection temperature at this
time shows the temperature characteristics as in FIG. 14C. The
distance along the length of the interconnection on the horizontal
axes in FIG. 14C corresponds to the distance from position a to
position b in FIG. 14A.
[0132] Referring to FIG. 14C, the same temperature distribution as
explained with the sixth through eighth embodiments is attained. In
other words, the region 14b of the first interconnection layer only
and the region 16b of the second interconnection layer only are at
low temperatures. Since heat is conducted from the first
interconnection layer 14 to the second interconnection layer 16
through the via hole 18, the temperatures rise in a certain extent
in the overlap regions 14a and 16a of the first interconnection
layer 14 and second interconnection layer 16, even if the first
interconnection layer 14 is at a low temperature. The region 98a
for conducting heat to the second interconnection layer, of the
heater line 98 formed on the lower side of the second
interconnection layer 16, is constituted with only the TiN film 98x
and becomes a high temperature because of the high interconnection
resistance. As a result, the heat generated is conducted to the
vicinity of the position where the second interconnection layer 16
is formed (a position no more than 50 .mu.m from the via hole 18
contact region 16x). Because a region of great temperature change
16h is formed in the second interconnection layer 16, this
temperature change region 16h becomes a barrier which reduces the
velocity of the migration of Al produced in the upper layer 22 of
the second interconnection layer 16. Consequently, effects which
are substantially the same as the backflow effect can be imparted
to the second interconnection layer 16. Accordingly, the increase
in interconnection resistance is prevented because void progression
can be suppressed and the EM resistance can be improved.
[0133] In the first through ninth embodiments discussed above, the
explanation has been made on examples of interconnection structures
with two layers of interconnection, but the interconnection
structures to which the present invention is applied are not
limited thereto and, needless to say, the present invention may
also be applied to multilayer interconnection with two or more
layers. Also, tungsten (W), TiN, and Al alloys were used as
examples of interconnection materials in the embodiments discussed
above, but the interconnection is not limited to these materials
and the present invention may be applied to materials generally
used for semiconductor elements.
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