U.S. patent application number 10/122322 was filed with the patent office on 2002-08-15 for semiconductor device and method of fabricating same.
This patent application is currently assigned to MITSUBISHI DENKI KABUSHIKI KAISHA. Invention is credited to Hirano, Yuuichi, Maeda, Shigenobu, Maegawa, Shigeto, Nishimura, Tadashi, Tsutsumi, Kazuhito.
Application Number | 20020110954 10/122322 |
Document ID | / |
Family ID | 12719953 |
Filed Date | 2002-08-15 |
United States Patent
Application |
20020110954 |
Kind Code |
A1 |
Maeda, Shigenobu ; et
al. |
August 15, 2002 |
Semiconductor device and method of fabricating same
Abstract
A semiconductor device for CSP mounting which avoids errors due
to alpha rays and is highly stress-resistant is provided. A buried
oxide film (107) is formed on a semiconductor substrate (101), and
a MOS transistor having an SOI structure is formed on the buried
oxide film (107). The MOS transistor comprises source and drain
regions (120a, 120b) formed in a semiconductor layer (120), and a
gate electrode (110). An aluminum pad (103) connected to any one of
the source and drain regions (120a, 120b) through a connecting
mechanism not shown, and a silicon nitride film (104) having an
opening on the top of the aluminum pad (103) are formed on an
interlayer insulation film (108). A layer of titanium (105) and a
layer of nickel (106) are formed extending from the aluminum pad
(103) to an end of the silicon nitride film (104). A solder bump
(11) is disposed on the layer of nickel (106).
Inventors: |
Maeda, Shigenobu; (Tokyo,
JP) ; Nishimura, Tadashi; (Tokyo, JP) ;
Tsutsumi, Kazuhito; (Tokyo, JP) ; Maegawa,
Shigeto; (Tokyo, JP) ; Hirano, Yuuichi;
(Tokyo, JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Assignee: |
MITSUBISHI DENKI KABUSHIKI
KAISHA
Tokyo
JP
|
Family ID: |
12719953 |
Appl. No.: |
10/122322 |
Filed: |
April 16, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10122322 |
Apr 16, 2002 |
|
|
|
09122863 |
Jul 27, 1998 |
|
|
|
Current U.S.
Class: |
438/106 ;
257/E23.021; 257/E23.115; 438/613 |
Current CPC
Class: |
H01L 23/3192 20130101;
H01L 2924/01006 20130101; H01L 2224/1148 20130101; H01L 23/556
20130101; H01L 2224/03914 20130101; H01L 2924/01033 20130101; H01L
2924/014 20130101; H01L 2924/01022 20130101; H01L 2224/131
20130101; H01L 2924/01018 20130101; H01L 24/03 20130101; H01L
2924/01082 20130101; H01L 2924/19043 20130101; H01L 2924/01075
20130101; H01L 2924/01004 20130101; H01L 2924/01013 20130101; H01L
2924/01079 20130101; H01L 2924/19041 20130101; H01L 24/12 20130101;
H01L 2224/1191 20130101; H01L 2224/11334 20130101; H01L 2224/13022
20130101; H01L 24/05 20130101; H01L 2924/0102 20130101; H01L
2924/3025 20130101; H01L 2924/01015 20130101; H01L 2924/01068
20130101; H01L 29/786 20130101; H01L 2924/00013 20130101; H01L
2924/01028 20130101; H01L 2924/05042 20130101; H01L 2924/13091
20130101; H01L 2924/01014 20130101; H01L 2224/0401 20130101; H01L
2924/01005 20130101; H01L 2924/0105 20130101; H01L 2224/05624
20130101; H01L 2924/181 20130101; H01L 2224/131 20130101; H01L
2924/014 20130101; H01L 2924/00013 20130101; H01L 2224/13099
20130101; H01L 2924/13091 20130101; H01L 2924/00 20130101; H01L
2924/181 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/106 ;
438/613 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 26, 1998 |
JP |
10-45459 |
Claims
We claim:
1. A semiconductor device comprising: a semiconductor layer
provided in an insulating layer and including a transistor having
an SOI structure formed therein; an electrode provided on said
insulating layer; and an electrically conductive bump provided on
said electrode.
2. The semiconductor device according to claim 1, wherein said
electrode includes a multilayer structure comprised of a layer of
titanium and a layer of nickel.
3. The semiconductor device according to claim 1, wherein said
transistor is a MOS transistor.
4. The semiconductor device according to claim 1, wherein said
transistor includes a plurality of transistors field-shield
isolated from each other and formed in said semiconductor
layer.
5. The semiconductor device according to claim 4, wherein said
electrode includes a multilayer structure comprised of a layer of
titanium and a layer of nickel.
6. A method of fabricating a semiconductor device, comprising the
steps of: (a) forming an electrode on a semiconductor substrate;
and (b) forming an electrically conductive bump on said electrode
and forming an insulating film for blocking an alpha ray and
covering an upper surface of said semiconductor substrate except
said electrode.
7. The method according to claim 6, wherein said electrode includes
a multilayer structure comprised of a layer of titanium and a layer
of nickel, and said insulating film is made of a polyimide.
8. The method according to claim 6, wherein said step (b) comprises
the steps of (b-1) forming said insulating film for blocking the
alpha ray and covering the upper surface of said semiconductor
substrate so that at least part of said electrode is exposed, and
(b-2) forming said electrically conductive bump on the exposed part
of said electrode.
9. The method according to claim 8, wherein said electrode includes
a multilayer structure comprised of a layer of titanium and a layer
of nickel, and said insulating film is made of a polyimide.
10. The method according to claim 6, wherein said step (b)
comprises the steps of (b-1) forming said bump on said electrode,
and (b-2) dropping the material of said insulating film for
blocking the alpha ray onto the upper surface of said semiconductor
substrate except onto said electrode.
11. The method according to claim 10, wherein said electrode
includes a multilayer structure comprised of a layer of titanium
and a layer of nickel, and said insulating film is made of a
polyimide.
12. A semiconductor device comprising: a semiconductor substrate;
an electrode disposed on said semiconductor substrate; an
electrically conductive bump provided on said electrode; a film
covering said semiconductor substrate except said bump and for
blocking an alpha ray; a first element disposed in said
semiconductor substrate in an area that is visible from said bump
without being obstructed by said film; and a second element
disposed in said semiconductor substrate in other than said area,
said second element being less resistant to the alpha ray than said
first element.
13. The semiconductor device according to claim 12, wherein said
bump is a solder bump.
14. The semiconductor device according to claim 13, wherein said
electrode includes a multilayer structure comprised of a layer of
titanium and a layer of nickel, and said insulating film is made of
a polyimide.
15. The semiconductor device according to claim 12, wherein said
first element is a MOS transistor having a body at a fixed
potential.
16. The semiconductor device according to claim 15, wherein said
bump is a solder bump.
17. The semiconductor device according to claim 16, wherein said
electrode includes a multilayer structure comprised of a layer of
titanium and a layer of nickel, and said insulating film is made of
a polyimide.
18. A semiconductor device comprising: a semiconductor substrate;
an electrode disposed on said semiconductor substrate; an
electrically conductive bump provided on said electrode; a film
covering said semiconductor substrate except said bump and for
blocking an alpha ray; an isolation oxide film disposed in said
semiconductor substrate in an a re a that is visible from said bump
without being obstructed by said film; and an element disposed in
said semiconductor substrate in other than said area.
19. The semiconductor device according to claim 18, wherein said
bump is a solder bump.
20. The semiconductor device according to claim 19, wherein said
electrode includes a multilayer structure comprised of a layer of
titanium and a layer of nickel, and said insulating film is made of
a polyimide.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device and,
more particularly, to a semiconductor device packaged in CSP (Chip
Size Package) form.
[0003] 2. Description of the Background Art
[0004] FIG. 9 is a schematic cross-sectional view showing
conventional CSP mounting. A semiconductor device 1 is directly
mounted in the form of a chip on a printed board 2 for the purpose
of reducing the area required to mount the semiconductor device 1
on the printed board 2. The semiconductor device 1 in chip form
comprises solder bumps 11 through which the semiconductor device 1
is connected to the printed board 2.
[0005] FIG. 10 is a schematic cross-sectional view showing another
type of conventional CSP mounting. As shown in FIG. 10, the
semiconductor device 1 in chip form is, in some cases, covered with
a molding resin 12 which allows the solder bumps 11 to be
exposed.
[0006] FIGS. 11 through 14 are cross-sectional views showing a
method of fabricating a conventional semiconductor device in the
order of sequential process steps. Referring to FIG. 11, diffusion
layers 101a and 101b functioning as a source and a drain are formed
in an upper surface of a semiconductor substrate 101 of silicon,
for example. An interlayer insulation film 102 made of, for
example, silicon oxide is formed on the semiconductor substrate
101. With a gate insulating film (equated with the interlayer
insulation film 102 for purposes of simplification of illustration)
therebetween, a gate 109 is opposed to the upper surface of a
portion of the semiconductor substrate 101 which lies between the
diffusion layers 101a and 101b. An aluminum pad 103 is connected to
the diffusion layer 101b through a connecting mechanism not shown,
for example, a contact hole.
[0007] A silicon nitride film 104 is formed on the structure shown
in FIG. 11 by the plasma CVD process. Part of the silicon nitride
film 104 which overlies the aluminum pad 103 is selectively removed
by the photolithography and etching to provide the structure shown
in FIG. 12.
[0008] A layer of titanium 105 and a layer of nickel 106 are
deposited on the structure shown in FIG. 12 by the sputtering
process. The photolithography and etching processes are performed
so that the layer of titanium 105 and the layer of nickel 106 are
left only in an area extending from the aluminum pad 103 to an end
of the silicon nitride film 104, thereby to provide the structure
shown in FIG. 13.
[0009] A solder bump 11 is disposed on a multilayer structure
consisting of the aluminum pad 103, the layer of titanium 105, and
the layer of nickel 106 in the structure shown in FIG. 13 to
provide the structure shown in FIG. 14.
[0010] It is well known in the art that, when irradiated with an
alpha ray 91, electrons 93 and holes 92 generated in semiconductor
cause operation errors of a semiconductor device. Although the
molding resin 12 covers the semiconductor device with the solder
bumps 11 exposed as shown in FIG. 10, there has been a need to use
a polyimide resin, for example, which is less pervious to alpha
rays than the material of the typical molding resin 12 to shield
and protect the semiconductor device against the alpha rays.
[0011] Unfortunately, it has been difficult for the polyimide resin
to shield and protect the semiconductor device in chip form used in
the conventional CSP mounting against the alpha rays. The
production of a polyimide in place of or on the silicon nitride
film 104 might result in the removal of the layer of titanium 105
and the layer of nickel 106 and the generation of the uneven or
rough surfaces thereof.
[0012] These problems result from a film-deposition temperature
exceeding 300.degree. C. at which the layer of titanium 105 and the
layer of nickel 106 are deposited by the sputtering process. In
general, a polyimide is produced by dehydrating carboxylic
polyamide in a liquid state by heating at a temperature of
300.degree. C. to 350.degree. C. to cause polymerization to occur.
However, it is difficult to completely remove moisture contained in
the carboxylic polyamide. The moisture remaining in the polyimide
might be released during the sputtering of the layer of titanium
105 and the layer of nickel 106 to result in the problems of the
removal thereof and the generation of the uneven surfaces
thereof.
[0013] Further, stresses are applied between the semiconductor chip
and the printed board since the printed board generally has greater
thermal expansion properties than the semiconductor chip. In the
CSP mounting, there are no stress-relieved lead frames in lead
frame type packaging, resulting in difficulties in relieving
stresses after packaging. The difficulties in the stress relief
present the likelihood of cracks generated in the semiconductor
substrate 101. The diffusion layers 101a and 101b are generally
formed in an impurity diffusion region known as a well. The
generation of cracks in the well significantly degrades transistor
characteristics.
SUMMARY OF THE INVENTION
[0014] According to a first aspect of the present invention, a
semiconductor device comprises: a semiconductor layer provided in
an insulating layer and including a transistor having an SOI
structure formed therein; an electrode provided on the insulating
layer; and an electrically conductive bump provided on the
electrode.
[0015] Preferably, according to a second aspect of the present
invention, in the semiconductor device of the first aspect, the
transistor includes a plurality of transistors field-shield
isolated from each other and formed in the semiconductor layer.
[0016] A third aspect of the present invention is also intended for
a method of fabricating a semiconductor device. According to the
present invention, the method comprises the steps of: (a) forming
an electrode on a semiconductor substrate; and (b) forming an
electrically conductive bump on the electrode and forming an
insulating film for blocking an alpha ray and covering an upper
surface of the semiconductor substrate except the electrode.
[0017] Preferably, according to a fourth aspect of the present
invention, in the method of the third aspect, the step (b)
comprises the steps of (b-1) forming the insulating film for
blocking the alpha ray and covering the upper surface of the
semiconductor substrate so that at least part of the electrode is
exposed, and (b-2) forming the electrically conductive bump on the
exposed part of the electrode.
[0018] Preferably, according to a fifth aspect of the present
invention, in the method of the third aspect, the step (b)
comprises the steps of (b-1) forming the bump on the electrode, and
(b-2) dropping the material of the insulating film for blocking the
alpha ray onto the upper surface of the semiconductor substrate
except onto the electrode.
[0019] According to a sixth aspect of the present invention, a
semiconductor device comprises: a semiconductor substrate; an
electrode disposed on the semiconductor substrate; an electrically
conductive bump provided on the electrode; a film covering the
semiconductor substrate except the bump and for blocking an alpha
ray; a first element disposed in the semiconductor substrate in an
area that is visible from the bump without being obstructed by the
film; and a second element disposed in the semiconductor substrate
in other than the area, the second element being less resistant to
the alpha ray than the first element.
[0020] Preferably, according to a seventh aspect of the present
invention, in the semiconductor device of the sixth aspect, the
first element is a MOS transistor having a body at a fixed
potential.
[0021] The semiconductor device of the first and second aspects of
the present invention may perform the so-called CSP mounting
wherein the conductive bump is connected to a printed board.
Additionally, the transistor has the SOI structure, and electrons
and holes generated due to an alpha ray in the semiconductor layer
in which the transistor is formed are in amounts which do not
influence the operation of the transistor. Further, there is a low
likelihood of cracks generated in the semiconductor layer because
of stresses resulting from the difference in thermal expansion
coefficient between the printed board and the semiconductor device
which have been a problem in the CSP mounting.
[0022] In accordance with the method of the third to fifth aspects
of the present invention, if the alpha ray blocking film made of a
polyimide which is not resistant to heating after being formed is
used as the insulating film, influences of the increase in
temperature during the formation of the electrode upon the
insulating film are avoided since the formation of the electrode
underlying the bump precedes the formation of the insulating
film.
[0023] In accordance with the semiconductor device of the sixth
aspect of the present invention, the first element which is highly
resistant to an alpha ray is formed in the area wherein no film
blocks the alpha ray coming from the bump. This allows effective
area use and avoids adverse effects resulting from the alpha
ray.
[0024] In accordance with the semiconductor device of the seventh
aspect of the present invention, the body of the MOS transistor
serving as the first element is at the fixed potential. This
suppresses parasitic bipolar effects to further increase the
resistance to the alpha ray.
[0025] It is therefore an object of the present invention to
provide a semiconductor device for CSP mounting which avoids errors
resulting from an alpha ray or which is highly resistant to
stresses.
[0026] These and other objects, features, aspects and advantages of
the present invention will become more apparent from the following
detailed description of the present invention when taken in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a cross-sectional view illustrating a structure of
a semiconductor device according to a first preferred embodiment of
the present invention;
[0028] FIG. 2 is a cross-sectional view illustrating another
structure of the first preferred embodiment;
[0029] FIGS. 3 through 5 are cross-sectional view showing a method
of fabricating the semiconductor device in the order of sequential
process steps according to a second preferred embodiment of the
present invention;
[0030] FIG. 6 is a cross-sectional view showing the method of
fabricating the semiconductor device according to a third preferred
embodiment of the present invention;
[0031] FIG. 7 is a cross-sectional view illustrating a structure of
the semiconductor device according to a fourth preferred embodiment
of the present invention;
[0032] FIG. 8 is a cross-sectional view illustrating a structure of
the semiconductor device according to a fifth preferred embodiment
of the present invention;
[0033] FIG. 9 is a schematic cross-sectional view showing
conventional CSP mounting;
[0034] FIG. 10 is a schematic cross-sectional view showing another
type of conventional CSP mounting; and
[0035] FIGS. 11 through 14 are cross-sectional views showing a
method of fabricating a conventional semiconductor device in the
order of sequential process steps.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0036] First Preferred Embodiment
[0037] FIG. 1 is a cross-sectional view illustrating a structure of
a semiconductor device according to a first preferred embodiment of
the present invention. A buried oxide film 107 is formed on a
semiconductor substrate 101 of silicon, for example. A MOS
transistor having an SOI (Semiconductor On Insulator) structure is
formed on the buried oxide film 107. The MOS transistor comprises
source and drain regions 120a and 120b formed in a semiconductor
layer 120 of silicon, for example, and a gate electrode 110. The
semiconductor layer 120 and the gate electrode 110 are covered with
an interlayer insulation film 108 made of, for example, BPTEOS
(Boro Phospho Tetra Ethyl Ortho Silicate) and NSG (Non-doped
Silicate Glass) and formed on the buried oxide film 107.
[0038] An aluminum pad 103 connected to any one of the source and
drain regions 120a and 120b through a connecting mechanism not
shown, and a silicon nitride film 104 having an opening on the top
of the aluminum pad 103 are formed on the interlayer insulation
film 108. A layer of titanium 105 and a layer of nickel 106 are
formed only in an area extending from the aluminum pad 103 to an
end of the silicon nitride film 104. A solder bump 11 is disposed
on the layer of nickel 106.
[0039] A lower part (including the semiconductor substrate 101) of
such a structure which lies below and includes the interlayer
insulation film 108 may be provided using the technique of forming
a conventional SOI transistor. An upper part (including the solder
bump 11) of such a structure which lies above the interlayer
insulation film 108 may be formed by the conventional technique
shown in FIGS. 11 through 14.
[0040] Electrons 93 and holes 92 are generated in the semiconductor
layer 120 and the semiconductor substrate 101 when the structure of
FIG. 1 is irradiated with an alpha ray 91. However, since the
semiconductor layer 120 is provided for the SOI transistor, the
thickness of the semiconductor layer 120 may be reduced to a
thickness level required for channel formation. Thus, the electrons
93 and holes 92 generated in the semiconductor layer 120 are much
smaller in number than those generated in the semiconductor
substrate 101. For this reason, the SOI transistor is less affected
adversely by the alpha ray 91 than a so-called bulk transistor such
as that shown in FIG. 14.
[0041] Additionally, when such a structure is cooled after the
heating of the solder bump 11 and the CSP mounting, stresses are
produced so that the printed board having a higher thermal
expansion coefficient than the semiconductor chip shrinks by a
greater amount. However, since the semiconductor layer 120 is thin
in thickness and short in length, the probability of cracks
generated in the semiconductor layer 120 is lower than those
generated in the semiconductor substrate 101. This achieves a
semiconductor chip has greater resistance to stresses than the
structure shown in FIG. 14 without impairing size reduction which
is characteristic of CSP.
[0042] FIG. 2 is a cross-sectional view illustrating another
structure of the semiconductor device according to the first
preferred embodiment of the present invention. The semiconductor
layer 120 extends perpendicularly to the direction of a channel
length not shown (that is, in the direction of a channel width). FS
gates 111 are provided for FS isolation (Field Shield isolation) of
a plurality of transistors arranged in the direction of the channel
width. The semiconductor layer 120, even if elongated in this
manner, is much thinner than the semiconductor substrate 101.
Therefore, stresses are prone to be relieved and few cracks are
generated in the semiconductor layer 120. Cracks, if any, in the
semiconductor substrate 101 exert no influences upon the
characteristics of the transistor formed in the semiconductor layer
120. Thus, the structure of FIG. 2 including the elongated
semiconductor layer 120 for FS isolation does not impair the
effects of the present invention, as compared with the structure of
FIG. 1.
[0043] Second Preferred Embodiment FIGS. 3 through 5 are
cross-sectional views showing a method of fabricating the
semiconductor device in the order of sequential process steps
according to a second preferred embodiment of the present
invention.
[0044] Referring to FIG. 3, an interlayer insulation film 102 is
formed on the semiconductor substrate 101, and a multilayer
structure consisting of the aluminum pad 103, the layer of titanium
105, and the layer of nickel 106 is formed on the interlayer
insulation film 102. The aluminum pad 103 is electrically connected
to source and drain regions not shown. The local triple metal layer
structure as shown in FIG. 3 may be accomplished by the
semiconductor fabrication techniques known in the art.
[0045] Thereafter, the silicon nitride film 104 and a polyimide
layer 203 are deposited, and an opening is formed therein on the
top of the layer of nickel 106 (FIG. 4). A multilayer film 201
comprised of the silicon nitride film 104 and the polyimide layer
203 serves as a film for blocking alpha rays. Further, the solder
bump 11 is formed in the opening. Then, the semiconductor device in
chip form is provided (FIG. 5). This structure comprising the
polyimide layer 203 for preventing the alpha rays from entering the
semiconductor substrate 101 may avoid errors resulting from the
alpha rays if a bulk transistor is formed in the semiconductor
substrate 101. Alpha rays coming from below the semiconductor
substrate 101 (where the interlayer insulation film 102 is not
provided) do not reach the diffusion layers 101a and 101b under
normal conditions and, hence, substantially need not be taken into
consideration.
[0046] The polyimide layer 203 is formed after the layer of
titanium 105 and the layer of nickel 106 are formed. Temperature
increases up to about 200.degree. C. in the step of providing the
solder bump 11. Therefore, the background art problem of the
moisture released from the polyimide layer 203 which has already
been formed is avoided.
[0047] Third Preferred Embodiment
[0048] FIG. 6 is a cross-sectional view showing the method of
fabricating the semiconductor device according to a third preferred
embodiment of the present invention. Carboxylic polyamide is
dropped onto the conventional structure shown in FIG. 14 except
onto the solder bump 11. Thereafter, the resultant structure is
heated to form the polyimide layer 203 except on the solder bump
11. This prevents alpha rays without interfering with the
connection between the solder bump 11 and the printed board.
[0049] Of course, the material used in the above described
technique is not limited to carboxylic polyamide, but any material
that is capable of preventing alpha rays and permitted to drop down
may be used.
[0050] Fourth Preferred Embodiment
[0051] FIG. 7 is a cross-sectional view illustrating a structure of
the semiconductor device according to a fourth preferred embodiment
of the present invention. An isolation oxide film 400 including an
area AR, and diffusion layers 101a and 101b serving as source and
drain regions are formed in the upper surface of the semiconductor
substrate 101. The interlayer insulation film 102 surrounding gate
electrodes 109 is formed on the semiconductor substrate 101. The
multilayer structure comprised of the aluminum pad 103, the layer
of titanium 105, and the layer of nickel 106 is locally formed on
the interlayer insulation film 102. The solder bump 11 is disposed
on the multilayer structure. The film 201 is formed on the
interlayer insulation film 102 except on the solder bump 11 The
formation of the film 201 may be achieved using the process step of
forming the polyimide film 203 shown in the second or third
preferred embodiment.
[0052] The presence of the film 201 and the solder bump 11
precludes an alpha ray coming through the air from entering the
semiconductor substrate 101. However, since solder generally
contains lead as an ingredient and radioactive isotopes as an
impurity in no small amounts, there is a likelihood that an alpha
ray enters the semiconductor substrate 101 from the solder bump 11
itself.
[0053] To prevent this, the area AR that is visible from the solder
bump 11 without being obstructed by the film 201 is established at
the upper surface of the semiconductor substrate 101. An element
whose operation is influenced by a slight increase in electric
charge, such as a transistor and a capacitor, is not formed in the
area AR which might be entered by the alpha ray from the solder
bump 11. For example, a capacitor formed in the semiconductor
device employed in the CSP mounting is tens of femtocoulombs, and
the operation of such a capacitor is influenced by the generation
of a small number of electron-hole pairs.
[0054] The isolation oxide film 400, for example, is formed in the
area AR. Alternatively, the SOI transistor highly resistant to the
alpha rays which is shown in the first preferred embodiment or a
resistance element may be formed in the area AR. Since the film 201
prevents the alpha ray coming from the solder bump 11 as well as
the alpha ray coming through the air from reaching the transistor
formed in other than the area AR, errors in the transistor due to
the alpha rays are avoided.
[0055] Specifically, an element which has greater resistance to
alpha rays than the element provided in other than the area AR may
be formed in the area AR to allow effective area use without
impairing the resistance of the entire semiconductor device to the
alpha rays.
[0056] Fifth Preferred Embodiment
[0057] FIG. 8 is a cross-sectional view illustrating a structure of
the semiconductor device according to a fifth preferred embodiment
of the present invention. Like the first preferred embodiment, the
semiconductor device of the fifth preferred embodiment comprises a
plurality of SOI transistors 121 to 123. The SOI transistor 121
includes source and drain regions 121a and 121b, a body portion
121c, and a gate electrode 121d. The SOI transistor 122 includes
source and drain regions 122a and 122b, a body portion 122c, and a
gate electrode 122d. The SOI transistor 123 includes source and
drain regions 123a and 123b, a body portion 123c, and a gate
electrode 123d. The body portions 121c and 122c are floating, and
the body portion 123c is at a potential fixed by the known
technique not shown.
[0058] For formation of a MOS SOI transistor in the area AR, fixing
the potential of the body portion of the transistor using the known
technique precludes the parasitic bipolar effects of the electrons
and holes generated by alpha rays and allows the effective area use
while further increasing the resistance to the alpha rays.
[0059] Variation
[0060] For avoiding the generation of an alpha ray from the solder
bump 11, a solder bump made of a lead-free alloy of gold and tin
may be employed.
[0061] While the invention has been described in detail, the
foregoing description is in all aspects illustrative and not
restrictive. It is understood that numerous other modifications and
variations can be devised without departing from the scope of the
invention.
* * * * *