U.S. patent application number 10/105296 was filed with the patent office on 2002-08-01 for thin film transistor and method of fabricating the same.
Invention is credited to Chen, Jr-Hong, Lu, I-Min.
Application Number | 20020102773 10/105296 |
Document ID | / |
Family ID | 24733108 |
Filed Date | 2002-08-01 |
United States Patent
Application |
20020102773 |
Kind Code |
A1 |
Lu, I-Min ; et al. |
August 1, 2002 |
Thin film transistor and method of fabricating the same
Abstract
A thin film transistor (TFT) and method of fabricating the same.
A planarization layer of polymer is formed on the interlayer to
reduce short-circuit. The planarization layer further reduces the
capacitance of the crossover capacitor and the delay time of the
LCD panel using the TFT is therefor minimized. A gate thereof can
be design under the data line to increase aperture ratio.
Inventors: |
Lu, I-Min; (Taipei, TW)
; Chen, Jr-Hong; (Hsinchu, TW) |
Correspondence
Address: |
RABIN & CHAMPAGNE, PC
1101 14TH STREET, NW
SUITE 500
WASHINGTON
DC
20005
US
|
Family ID: |
24733108 |
Appl. No.: |
10/105296 |
Filed: |
March 26, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10105296 |
Mar 26, 2002 |
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09680935 |
Oct 10, 2000 |
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Current U.S.
Class: |
438/139 ;
257/E29.283 |
Current CPC
Class: |
H01L 29/78636
20130101 |
Class at
Publication: |
438/139 |
International
Class: |
H01L 021/332 |
Foreign Application Data
Date |
Code |
Application Number |
May 11, 2000 |
TW |
89109389 |
Claims
What is claimed is:
1. A method of fabricating a TFT, comprising: providing a silicon
substrate; forming a channel region, a first S/D region, and a
second S/D region; forming a gate insulating layer; forming a gate;
forming an interlayer; forming a planarization layer; forming a
fist via hole and a second via hole, wherein the first via hole and
the second via hole pass through the planarization layer and the
interlayer to connect with the first S/D region and the second S/D
region, respectively; p1 depositing and defining a metal layer to
form a first S/D region metal line and a second S/D region metal
line; forming a passivation layer; defining an opening, which
passes through the passivation layer to connect with the first S/D
region metal line; and forming a conductive layer.
2. The method of claim 1, wherein the silicon substrate is a quartz
substrate.
3. The method of claim 1, wherein the silicon substrate is a glass
substrate.
4. The method of claim 1, further comprising: forming a buffer
layer above the silicon substrate and below the first S/D region
and the second S/D region.
5. The method of claim 1, wherein the gate insulating layer is
formed, using Silicon Oxide as material.
6. The method of claim 1, wherein the gate insulating layer is
formed by depositing Silicon Nitride, using Plasma Enhanced
Chemical Vapor Deposition.
7. The method of claim 1, wherein the planarization layer is formed
by coating a layer of polymer.
8. The method of claim 7, wherein the interlayer has a dielectric
constant of about 1.5-3.5.
9. The method of claim 7, wherein the polymer is BCB.
10. The method of claim 7, wherein the polymer us PC403.
11. The method of claim 2, wherein the conductive layer is an ITO
layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of copending application
serial number 09/680,935, which was filed on Oct. 10, 2000
BACKGROUND OF THE INVENTION
[0002] This application incorporates by reference Taiwanese
application Ser. No. 89109389, Filed on May 11, 2000.
[0003] 1. Field of the Invention
[0004] The invention relates in general to the structure and the
manufacturing method of a thin film transistor (TFT), and more
particularly to a structure and a manufacturing method of a thin
film transistor device, which reduces the short-circuit between
different metal layers.
[0005] 2. Description of the Related Art
[0006] Liquid Crystal Displays (LCDs) are turning up everywhere
these days. The LCD, a light, slender display, with a beautiful
image that does not tire the eyes even when viewed for hours at a
time, is finding its way into many products.
[0007] Specific applications with significant growth potential for
LCD, include portable computers, desktop computers, audio visual
equipment.
[0008] Super-Twisted Nematic mode LCD (STN LCD) and Thin Film
Transistor LCD (TFT LCD) are the two popular types of LCDs
nowadays. They are usually applied in different devices. Due to the
wide view angle of the TFT
BACKGROUND OF THE INVENTION
[0009] This application incorporates by reference Taiwanese
application Ser. No. 89109389, Filed on May 11, 2000.
[0010] 1. Field of the Invention
[0011] The invention relates in general to the structure and the
manufacturing method of a thin film transistor (TFT), and more
particularly to a structure and a manufacturing method of a thin
film transistor device, which reduces the short-circuit between
different metal layers.
[0012] 2. Description of the Related Art Liquid Crystal Displays
(LCDs) are turning up everywhere these days. The LCD, a light,
slender display, with a beautiful image that does not tire the eyes
even when viewed for hours at a time, is finding its way into many
products.
[0013] Specific applications with significant growth potential for
LCD, include portable computers, desktop computers, audio visual
equipment.
[0014] Super-Twisted Nematic mode LCD (STN LCD) and Thin Film
Transistor LCD (TFT LCD) are the two popular types of LCDs
nowadays. They are usually applied in different devices. Due to the
wide view angle of the TFT LCD, the TFT LCD is more widely
incorporated.
[0015] FIG. 1 shows the equivalent circuit of the LCD panel. For
the purpose of clearly illustrating, only 3 scan lines 101 and 3
data lines are shown herein. However, it is apparent that the real
LCD panel includes more than that.
[0016] As shown in FIG. 1, there is a crossover capacitor at the
crossover of each scan line 101 and data line 102. The crossover
capacitor determines the delay time of the LCD panel. Larger
capacitance of the crossover capacitor causes longer delay time. On
the other hand, lower capacitance of the crossover capacitor causes
shorter delay time.
[0017] FIG. 2 is the cross-section view of the crossover capacitor
of a conventional TFT. The crossover capacitor region 200 is
composed of a scan line layer 201, an interlayer 202 and a data
line 203. The scan line layer 201 and the data line layer 203 are
both metal layers. As it can be referred form the names, the scan
line layer 201 and the data line layer 203 in FIG. 2 respectively
form the scan line and data line in FIG. 1. The scan line layer 201
can be, for example, the gate of the TFT. The source region and the
drain region thereof can be easily referred and therefore are
omitted in FIG. 2.
[0018] The manufacturing methods of the interlayer 202 include at
least the following:
[0019] 1. depositing silicon oxide (SiOx) and performing hydrogen
plasma hydrogenation; and
[0020] 2. depositing silicon nitride (SiNx) by PECVD and high
temperature annealing.
[0021] During the fabrication of the TFT, the problem of
short-circuit should be overcome, in addition to other basic
requirements of the device property like the follow of current and
the value of threshold voltage. Short-circuit between two different
metal layers causes heavy loading of the system during driving,
which therefore interrupts the normal procedure.
[0022] FIG. 3 is the cross-sectional view of a crossover capacitor
region, having pin holes, of a conventional TFT. The crossover
capacitor region 300 includes a scan line layer 301, an interlayer
302 and a data line layer 303. The chief defect of the TFT in FIG.
3 is the pin holes 304, which are formed at the edge of the scan
line layer 301 during the formation of the interlayer 302. The pine
holes 304 could be filled with the material of the data line layer
303 in the following procedure of fabricating the data line layer
303. Consequently, the data line layer 303 is connected with the
scan line layer 301. Due to the fact that the materials of the data
line layer 303 and the scan line layer are both conductors, the
connection of the data line layer 303 and the scan line layer 301
results in short-circuit in the crossover capacitor region 300.
[0023] Conventionally, the edges of the lower metal layer, the scan
line layer in this case, are etched to be taper-shaped to reduce
the occurrence of short-circuit between different metal layers.
[0024] FIG. 4 is the cross-sectional view, showing the conventional
method to modify the TFT in order to eliminate short-circuit. The
crossover capacitor region as in FIG. 4 includes a scan line layer
401, an interlayer 402 and a data line layer 403. The edges of the
scan line layer 401 are etched to be taper-shaped. Therefore, the
interlayer 401 formed thereafter could have better step coverage,
which consequently reduces the occurrence of the pin holes and
short-circuit. It is clear that this method include at least one
additional step to etch the lower metal layer, which conflicts the
principle of minimizing fabricating steps.
[0025] Another method for preventing pin holes is to improve the
pre-washing procedure before the deposition of the interlayer.
However, to improve the pre-washing procedure requires
high-stability of each step, which therefore increases the
complexity the process.
SUMMARY OF THE INVENTION
[0026] It is therefore an object of the invention to provide an
improved and simplified structure and process of TFT to solve the
above-mentioned problems. According to a preferred embodiment of
the invention, the lower metal line (the scan line layer) needs not
to be etched as taper-like. Also, a under strict control
pre-washing step is not needed. Furthermore, TFT device of a
preferred embodiment of the invention has higher yield and the
occurrence ratio of short-circuit thereof is greatly reduced.
[0027] It is another object of the invention to provide a TFT and a
method of forming the same. A planarization layer of polymer is
formed on the interlayer to reduce short-circuit. The planarization
layer further reduces the capacitance of the crossover capacitor
and the delay time of the LCD panel using the TFT is therefor
minimized. A gate thereof can be design under the data line to
increase aperture ratio.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Other objects, features, and advantages of the invention
will become apparent from the following detailed description of the
preferred but non-limiting embodiments. The description is made
with reference to the accompanying drawings in which:
[0029] FIG. 1 (Prior Art) illustrates the equivalent circuit of the
LCD panel.
[0030] FIG. 2 (Prior Art) is the cross-section view of the
crossover capacitor of a conventional TFT.
[0031] FIG. 3 (Prior Art) is the cross-sectional view of a
crossover capacitor region, having pin holes, of a conventional
TFT.
[0032] FIG. 4 (Prior Art) is the cross-sectional view, showing the
conventional method to modify the TFT in order to eliminate
short-circuit.
[0033] FIG. 5A to FIG. 5C are the cross-sectional views showing the
fabrication of the thin film transistor (TFT) device according to a
preferred embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0034] FIG. 5A to FIG. 5C are the cross-sectional views showing the
fabrication of the thin film transistor (TFT) device according to a
preferred embodiment of the invention.
[0035] As shown in FIG. 5A, the TFT is formed on a buffer layer 502
over a substrate 501. The material of the substrate 501 could be
silicon wafer, quartz, or alkali-free glass. An active layer 520 as
the channel region and source/drain (S/D) regions of the TFT is
first formed on the buffer layer 502. Next, a gate insulator 503 is
formed on the buffer layer 502, preferrably using Plasma Enhanced
Chemical Vapor Deposition (PECVD). The gate insulator 503 covers
both the S/D regions and the active layer 520. The material of the
gate insulator 503 can be any kind of insulating material such as
silicon oxide, silicon oxide (SiOx) or silicon nitride (SiNx).
[0036] Then, a gate G as the scan line of the LCD panel is formed
on the gate insulating layer 503 over the active layer 520. S/D
regions are formed by doping the active layer 520, preferrably
using ion implantation. TFT with a gate G over the S/D regions as
shown in FIG. 5A is so-called Top Gate TFT.
[0037] Then, as shown in FIG. 5B, an interlayer 504 is formed over
the gate insulating layer 503 and the gate G. The interlayer 504
can be formed by, for example, the following methods:
[0038] 1, depositing silicon oxide (SiOx) and performing hydrogen
plasma hydrogenation; or
[0039] 2. depositing silicon nitride (SiNx) by PECVD and high
temperature annealing.
[0040] Moreover, the interlayer 504 can be an oxide/polymer double
layer structure and a single polymer layer.
[0041] Then, a planarization layer 505 is formed on the interlayer
504. The planarization layer 505 is fabricated preferrably by
coating polymers smoothly over the interlayer 504, using spin-on
and the preferred thickness of the planarization layer 505 is about
1-5 .mu.m. The planarization layer 505 is one of the
characteristics of the invention. The formation of the
planarization layer 505 greatly reduces the occurrence of
short-circuit between different metal layers and consequently
increase the yield of the LCD panel.
[0042] Transparency and dielectric constant are two criteria for
choosing the polymer material for the planarization layer 505. The
capacitance of the crossover capacitor is a function of the value
of dielectric constant of the polymer. Also, the delay time of the
LCD panel is a function of the capacitance of the crossover
capacitor. Therefore, dielectric constant of the polymer determines
the delay time of the LCD panel. Ideal material for LCD is polymer
having dielectric constant of about 1.5-3.5 and high transparency.
Polymers such as BCB (Dow Chemical) and PC403 (JSR) are
preferred.
[0043] After the formation of the planarization layer 505, via
holes 506, 507 are formed, using methods such as photolithography
and etching. Via holes 506, 507 are formed down to the S/D regions.
In other words, S/D regions are exposed at this stage. Photo-resist
used for forming the via holes can be either positive photo-resist
or negative photo-resist.
[0044] Then, as shown in FIG. 5C, a metal layer is formed, for
example, by deposition over the substrate and to fill the via holes
506, 507. The metal layer is then patterned to form metal lines
508, 509, connecting to S/D regions.
[0045] A passivation layer 510 is next formed over the
planarization layer 505, covering the metal lines 508, 509.
[0046] Then, a conductive layer 511 coupled to the metal lines 508,
509 is to be formed. The process of forming the conductive layer
511 includes: defining an opening through the passivation layer 510
to expose the metal lines 508, 509, and filling conductive material
in the opening. The conductive layer 511 is used as the data line
of the LCD panel. Preferred material of the conductive layer 511
can be Indium Tin Oxide (ITO). Forming the planarization layer over
the interlayer is one of the characteristics of the structure and
the method of the TFT according to a preferred embodiment of the
invention. The problem of short-circuit can be overcome simply by
using the planarization layer instead of the conventional step of
etching the lower conductive layer, that is, the scan line layer,
to be taper-like.
[0047] Furthermore, the delay time of the LCD panel can be reduced
by using proper polymer material of the planarization layer.
[0048] The gate G can be designed under the data line layer to
increase the aperture ratio. The occurrence ratio of short-circuit
will not be effected by this design.
[0049] While the invention has been described by way of example and
in terms of the preferred embodiment, it is to be understood that
the invention is not limited to the disclosed embodiment. To the
contrary, it is intended to cover various modifications and similar
arrangements and procedures, and the scope of the appended claims
therefore should be accorded the broadest interpretation so as to
encompass all such modifications and similar arrangements and
procedures.
* * * * *