U.S. patent application number 10/058061 was filed with the patent office on 2002-08-01 for semiconductor integrated circuit and fabrication process therefor.
Invention is credited to Kanda, Makoto.
Application Number | 20020100975 10/058061 |
Document ID | / |
Family ID | 18885732 |
Filed Date | 2002-08-01 |
United States Patent
Application |
20020100975 |
Kind Code |
A1 |
Kanda, Makoto |
August 1, 2002 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION PROCESS
THEREFOR
Abstract
A semiconductor integrated circuit is provided which includes
bump electrodes having a uniform height. The semiconductor
integrated circuit includes: a semiconductor substrate (wafer)
having a plurality of bump electrode formation areas and a bump
electrode non-formation area respectively defined on a front
surface thereof; a first electrode pad formed in the bump electrode
non-formation area; a second electrode pad formed in each bump
electrode formation area; and a bump electrode formed on each
second electrode pad; wherein the first electrode pad is used for
supplying a plating electric current to the second electrode pads
through the semiconductor substrate in formation of the bump
electrodes by electrolytic plating.
Inventors: |
Kanda, Makoto;
(Fukuyama-shi, JP) |
Correspondence
Address: |
NIXON & VANDERHYE P.C.
8th Floor
1100 North Glebe Road
Arlington
VA
22201-4714
US
|
Family ID: |
18885732 |
Appl. No.: |
10/058061 |
Filed: |
January 29, 2002 |
Current U.S.
Class: |
257/737 ;
257/673; 257/E21.175; 257/E21.508; 257/E23.021 |
Current CPC
Class: |
H01L 2924/01082
20130101; H01L 2924/01005 20130101; H01L 24/11 20130101; H01L
2924/14 20130101; H01L 2924/01079 20130101; H01L 2224/1147
20130101; H01L 2924/01004 20130101; H01L 2224/03912 20130101; H01L
21/2885 20130101; H01L 2924/01033 20130101; H01L 24/02 20130101;
H01L 24/05 20130101; H01L 24/13 20130101; H01L 2924/01006 20130101;
H01L 2924/01078 20130101; H01L 2224/0401 20130101; H01L 24/03
20130101 |
Class at
Publication: |
257/737 ;
257/673 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 29, 2001 |
JP |
2001-019950 |
Claims
What is claimed is:
1. A semiconductor integrated circuit comprising: a semiconductor
substrate having a plurality of bump electrode formation areas and
a bump electrode non-formation area respectively defined on a front
surface thereof; a first electrode pad formed in the bump electrode
non-formation area; a second electrode pad formed in each bump
electrode formation area; and a bump electrode formed on each
second electrode pad; wherein the first electrode pad is used for
supplying a plating electric current to the second electrode pads
through the semiconductor substrate in formation of the bump
electrodes by electrolytic plating.
2. A semiconductor integrated circuit as set forth in claim 1,
wherein the bump electrode non-formation area includes a plurality
of bump electrode non-formation areas respectively formed with
first electrode pads.
3. A semiconductor integrated circuit as set forth in claim 1, the
first electrode pad is formed in the neighborhood of the second
electrode pads.
4. A semiconductor integrated circuit as set forth in claim 1,
semiconductor substrate includes a metal film on a back surface of
the semiconductor substrate.
5. A process for fabricating the semiconductor integrated circuit
of claim 1, the process comprising the steps of: defining a
plurality of bump electrode formation areas and a bump electrode
non-formation area on a front surface of a semiconductor substrate,
the bump electrode formation area being insulated from the
semiconductor substrate, the bump electrode non-formation area
being conductive to the semiconductor substrate,; forming a first
electrode pad in the bump electrode non-formation area; forming a
second electrode pad in each bump electrode formation area; forming
a conductive layer for connecting the first electrode pad and the
second electrode pads on the semiconductor substrate; covering the
front surface of the semiconductor substrate with a resist film
except the second electrode pads; supplying a plating electric
current from a back surface of the semiconductor substrate to the
second electrode pads through the semiconductor substrate, the
first electrode pad and the conductive layer; forming a bump
electrode on each second electrode pad by electrolytic plating; and
removing the resist film and the conductive layer from the
semiconductor substrate.
6. A process as set forth in claim 5, wherein the step of defining
the bump electrode non-formation area includes a step of defining a
plurality of bump electrode non-formation areas on the front
surface of the semiconductor substrate, and the step of forming the
first electrode pad includes a step of forming a first electrode
pad in each bump electrode non-formation area.
7. A process as set forth in claim 5, wherein the step of forming
the first electrode pad includes a step of forming the first
electrode pad in the neighborhood of the second electrode pads.
8. A process as set forth in claim 5, further comprising the step
of forming a metal film on the back surface of the semiconductor
substrate, Wherein the plating electric current is supplied through
the metal film.
9. A semiconductor integrated circuit comprising: a semiconductor
substrate having a bump electrode formation area and a bump
electrode non-formation area respectively defined on a surface
thereof; a first electrode pad formed in the bump electrode
non-formation area; a second electrode pad formed in the bump
electrode formation area; and a bump electrode formed on the second
electrode pad; wherein the first electrode pad is used for
supplying a plating electric current to the second electrode pad
through the semiconductor substrate in formation of the bump
electrode by electrolytic plating.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to Japanese application No.
2001-019950 filed on Jan. 29, 2001, whose priority is claimed under
35 USC .sctn. 119, the disclosure of which is incorporated by
reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor integrated
circuit and a fabrication process therefor. More particularly, the
invention relates to a semiconductor integrated circuit which has a
plurality of bump electrodes having a uniform height, and to a
fabrication process therefor.
[0004] 2. Description of the Related Art
[0005] In the fields of cellular phones and mobile information
terminals in the electronic information industry, attempts have
recently been made to increase the integration density of
semiconductor devices. For a higher integration density, it is
necessary to stably establish electrical and physical connections
between minute electrode pads on a semiconductor device and
interconnections on a substrate mounted with the semiconductor
device.
[0006] One exemplary method for the establishment of the
connections is to form gold bumps on electrode pads of the
semiconductor device. Plating methods are generally employed for
the formation of the gold bumps on the semiconductor device. The
plating methods are broadly classified into two categories: an
electroless plating method and an electrolytic plating method.
[0007] In the electroless plating method, a metal of a metal base
to be plated is chemically replaced with a metal contained in a
plating liquid. Therefore, the electroless plating method is
advantageous in that equipment such as a plating power source is
not required. However, possible combinations of the metal base and
the plating liquid are limited, and a plating rate is relatively
low. Therefore, the electroless plating method is not suitable for
formation of a metal film having a thickness of ten-odd micrometers
to several tens of micrometers as required for the formation of the
bumps on the semiconductor device.
[0008] In the electrolytic plating method, on the other hand, the
plating is electrochemically achieved by passing an electric
current through a metal base to be plated and a plating liquid.
Therefore, the electrolytic plating method can be applied to a
combination of the metal base and the plating liquid to which the
aforesaid electroless plating method cannot be applied. In the
electrolytic plating method, the plating electric current increases
the plating rate as compared with the electroless plating method,
and a metal film having a thickness of several tens of micrometers
can easily be formed. Therefore, the electrolytic plating method is
suitable for the formation of the bumps on the semiconductor
integrated circuit.
[0009] Next, a bump formation process employing the electrolytic
plating method will briefly be described.
[0010] A metal base film is first formed on an insulating film
provided on a semiconductor substrate (herein referred to as
"wafer"). Then, a photoresist film is formed on the metal base
film, and openings are formed in the photoresist film by a
photolithography technique to expose predetermined portions of the
metal base film, i.e., in bump electrode formation areas.
Thereafter, a plating electric current is supplied to the metal
base film, whereby a metal is deposited on the exposed portions of
the metal base film for formation of bump electrodes. There are
three conventionally known methods for the supply of the plating
electric current.
[0011] In a first conventional method, an opening for connection of
a plating electrode (herein referred to as "cathode electrode") is
formed in the photoresist film in a peripheral area of the wafer
when the photoresist film is formed on the metal base film, and
then the cathode electrode is connected to the metal base film
through the opening. Alternatively, the photoresist film is removed
by piercing the photoresist film with the cathode electrode for the
connection of the cathode electrode to the metal base film.
[0012] More specifically, electrode pads 23 are provided on an
insulating film 22 on a wafer 21, and the wafer is covered with a
protective film 24 which has openings on the electrode pads 23 in
bump electrode formation areas A as shown in FIG. 6. A metal base
film 25 is formed over the resulting wafer, and a photoresist film
26 is formed on the metal base film 25. Further, openings are
formed in the photoresist film 26 in the bump electrode formation
areas A.
[0013] The photoresist film 26 is pierced with a cathode electrode
28 for electrical connection of the cathode electrode 28 to the
metal base film 25 (though not shown, an opening may be formed in
the photoresist film 26 for connection of the cathode electrode to
the metal base film).
[0014] In turn, the resulting wafer 21 is set in a plating device
101 as shown in FIG. 7. The wafer 21 is supported by the cathode
electrode 28 with a bump electrode formation surface thereof facing
downward to be opposed to an anode electrode 10.
[0015] In the plating device 101, a plating liquid 9 is fountained
from an inner lower side of the device toward the bump formation
surface of the wafer 21, and discharged from the periphery of the
wafer 21 to the outside.
[0016] In this state, a voltage is applied between the anode
electrode 10 and the cathode electrode 28 connected to the metal
base film 25 on the wafer 21, whereby a plating electric current is
supplied to the metal base film 25 for formation of bump electrodes
27 (see FIG. 6).
[0017] In a second conventional method, a cathode electrode is
connected to a portion of the metal base film on a side surface of
the wafer (see, for example, Japanese Unexamined Patent Publication
No. 1-110751 (1989)) in view of the fact that the metal base film
is formed not only on the bump electrode formation surface but also
on the side surfaces of the wafer.
[0018] More specifically, a metal base film 35 is formed on a bump
electrode formation surface and side surfaces of a wafer 31, and a
cathode electrode 38 is electrically connected to a portion of the
metal base film on the side surface of the wafer as shown in Fig.
8. Thereafter, the resulting wafer is subjected to the plating
process in substantially the same manner as in the first method in
the aforesaid plating device 101 (See FIG. 7).
[0019] In a third conventional method, a metal film electrically
connected to the metal base film is formed on a back surface of the
wafer, and a cathode electrode is connected to the metal film on
the back surface of the wafer (see, for example, Japanese
Unexamined Patent Publication No. 3-54829 (1991)).
[0020] More specifically, a metal base film 45 is formed as
covering a bump electrode formation surface and side surfaces of a
wafer 41, and a metal film 46 is formed on a back surface of the
wafer 41 so as to be electrically connected to the metal base film
on the side surface of the wafer. A cathode electrode 48 is
electrically connected to the metal film 46. Thereafter, the
resulting wafer is subjected to the plating process in
substantially the same manner as in the first method in the
aforesaid plating device 101 (see FIG. 7).
[0021] In the first conventional method, the plating liquid
penetrates through the opening provided for the cathode electrode
connection during the plating process in the electrolytic plating
device, so that the plating electric current is unevenly supplied
to an area other than the bump electrode formation areas.
Therefore, a metallization layer is uselessly formed in the
unintended area by the plating, and the resulting bump electrodes
are nonuniform in height.
[0022] Where the photoresist film is pierced with the cathode
electrode to be removed, it is difficult to control the removal of
the photoresist film. If the removal of the photoresist film is
excessive, the aforesaid problem occurs. If the removal of the
photoresist film is insufficient, an electrical connection cannot
sufficiently be established between the cathode electrode and the
metal base film, resulting in uneven supply of the plating electric
current. Therefore, the resulting bump electrodes are nonuniform in
height.
[0023] In the second conventional method, the metal base film is
exposed on the side surfaces of the wafer, so that the plating
liquid is easily brought into contact with the side surfaces of the
wafer. Therefore, a metallization layer is uselessly formed on the
side surfaces of the wafer, and the resulting bump electrodes are
nonuniform in height.
[0024] In the third conventional method, the cathode electrode is
connected to the metal film formed on the back surface of the
wafer, so that the plating electric current is supplied to the bump
electrode formation areas via the periphery of the wafer. Since
distances between the periphery of the wafer and each bump
formation area in the semiconductor integrated circuit formed on
the wafer are different, plating potentials occurring in the bump
formation areas are different.
[0025] Further, the metal base film has variations in thickness due
to steps on the surface of the semiconductor integrated circuit on
the wafer, so that the metal base film has variations in resistance
depending on the position on the wafer. Due to these problems, the
amperage of the plating electric current supplied to the metal base
film varies depending on the position on the wafer, so that the
resulting bump electrodes are nonuniform in height.
[0026] In the first to third conventional methods, a common
approach is to supply the plating electric current via the
periphery of the wafer, so that the amperage of the supplied
plating electric current varies depending on the position on the
wafer. Therefore, the first to third methods fail to form bump
electrodes having a uniform height on the wafer.
[0027] Where bump electrodes having a height of about 20 .mu.m are
to be formed on 6-inch wafer, for example, a maximum height
variation of the bump electrodes is about 6 .mu.m in the first
conventional method, about 5 .mu.m in the second method, and about
4 .mu.m in the third method.
[0028] In view of the foregoing, the present invention is directed
to a semiconductor integrated circuit having bump electrodes of a
uniform height and a fabrication process in which a plating
electric current is evenly supplied over a wafer in an electrolytic
plating process for formation of the bump electrodes.
SUMMARY OF THE INVENTION
[0029] In accordance with the present invention, there is provided
a semiconductor integrated circuit which comprises a semiconductor
substrate (wafer) having a plurality of bump electrode formation
areas and a bump electrode non-formation area respectively defined
on a front surface thereof; a first electrode pad formed in the
bump electrode non-formation area; a second electrode pad formed in
each bump electrode formation area; and a bump electrode formed on
each second electrode pad; wherein the first electrode pad is used
for supplying a plating electric current to the second electrode
pads through the semiconductor substrate in formation of the bump
electrodes by electrolytic plating.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is a sectional view illustrating a semiconductor
integrated circuit according to Embodiment 1 of the present
invention;
[0031] FIGS. 2(a) to 2(e) and FIGS. 3(f) and 3(g) are process
diagrams for explaining a bump electrode formation process for the
semiconductor integrated circuit shown in FIG. 1;
[0032] FIG. 4 is a graph illustrating a comparison between height
variations of bump electrodes formed by a fabrication process
according to Embodiment 1 and height variations of bump electrodes
formed by a conventional fabrication process;
[0033] FIG. 5 is a sectional view of a semi-finished semiconductor
integrated circuit in a bump electrode formation process according
to Embodiment 2 of the invention;
[0034] FIG. 6 is a diagram for explaining a conventional bump
electrode formation process;
[0035] FIG. 7 is a diagram for explaining the conventional bump
electrode formation process with a wafer being set in a plating
device;
[0036] FIG. 8 is a diagram for explaining a conventional bump
electrode formation process; and
[0037] FIG. 9 is a diagram for explaining a conventional bump
electrode formation process.
DETAILED DESCRIPTION OF THE INVENTION
[0038] In accordance with one aspect of the present invention,
there is provided a semiconductor integrated circuit which
comprises a semiconductor substrate (wafer) having a plurality of
bump electrode formation areas and a bump electrode non-formation
area respectively defined on a front surface thereof; a first
electrode pad formed in the bump electrode non-formation area; a
second electrode pad formed in each bump electrode formation area;
and a bump electrode formed on each second electrode pad; wherein
the first electrode pad is used for supplying a plating electric
current to the second electrode pads through the semiconductor
substrate in formation of the bump electrodes by electrolytic
plating.
[0039] In the inventive semiconductor integrated circuit, the
semiconductor substrate forms an integrated circuit inside
thereof.
[0040] The bump electrode formed on each second electrode pad is
electrically connected to the integrated circuit through a wiring
pattern.
[0041] The bump electrodes are frequently provided at a peripheral
of the semiconductor substrate, since the bump electrodes serve for
electrically connecting the semiconductor integrated circuit to an
external wiring pattern of a mounting substrate, an external
terminal of a lead frame or the like.
[0042] According to the invention, the plating electric current may
be supplied from a back surface of the semiconductor substrate to
the second electrode pads through the semiconductor substrate and
the first electrode pad for supplying the plating electric
current.
[0043] On this occasion, the general amount of the plating electric
current is supplied from the back surface of the semiconductor
substrate to each second electrode pad through the semiconductor
substrate and the first electrode pad.
[0044] On the other hand, an electric resistance of a route running
from the back surface of the semiconductor substrate to each second
electrode pad through the semiconductor substrate, the integrated
circuit and the wiring pattern is so high that the amount of the
plating electric current supplied through the said route is
slight.
[0045] Therefore, it is required that the first electrode pad has
an enough size to reduce an electric resistance for the plating
electric current.
[0046] Consequently, it is preferred that the bump electrode
non-formation area is defined on a region having a sufficient size,
for example, a peripheral of the semiconductor substrate.
[0047] In the inventive semiconductor integrated circuit, the first
electrode pad may be formed in the neighborhood of the second
electrode pads.
[0048] In the inventive semiconductor integrated circuit, the bump
electrode non-formation area may include a plurality of bump
electrode non-formation areas respectively formed with first
electrode pads. In this case, the first electrode pads are
preferably equal to the second electrode pads in number so that
each first electrode pad is adjacent to each second electrode
pad.
[0049] With this arrangement, when the plating electric current is
supplied from a cathode electrode to each second electrode pad via
each first electrode pad provided adjacent to each bump electrode
formation area, the plating electric current is evenly supplied to
each second electrode pad, so that the resulting bump electrodes
are uniform in height.
[0050] In the inventive semiconductor integrated circuit,
semiconductor substrate may include a metal film on the back
surface of the semiconductor substrate.
[0051] With this arrangement, an electric resistance to the plating
electric current supplied from the cathode electrode can be
reduced.
[0052] In accordance with another aspect of the present invention,
there is provided a process for fabricating the semiconductor
integrated circuit of the present invention, the process comprising
the steps of: defining a plurality of bump electrode formation
areas and a bump electrode non-formation area on a front surface of
a semiconductor substrate (wafer), the bump electrode formation
areas being insulated from the semiconductor substrate, the bump
electrode non-formation area being conductive to the semiconductor
substrate,; forming a first electrode pad in the bump electrode
non-formation area; forming a second electrode pad in each bump
electrode formation area; forming a conductive layer for connecting
the first electrode pad and the second electrode pads on the
semiconductor substrate; covering the front surface of the
semiconductor substrate with a resist film except the second
electrode pads; supplying a plating electric current from a back
surface of the semiconductor substrate to the second electrode pads
through the semiconductor substrate, the first electrode pad and
the conductive layer; forming a bump electrode on each second
electrode pad by electrolytic plating; and removing the resist film
and the conductive layer from the semiconductor substrate.
[0053] In the inventive fabrication process, the step of defining
the bump electrode non-formation area may include a step of
defining a plurality of bump electrode non-formation areas on the
front surface of the semiconductor substrate, and the step of
forming the first electrode pad may include a step of forming a
first electrode pad in each bump electrode non-formation area.
[0054] In the inventive fabrication process, the step of forming
the first electrode pad may include a step of forming the first
electrode pad in the neighborhood of the second electrode pads.
[0055] The inventive fabrication process may further comprise the
step of forming a metal film on the back surface of the
semiconductor substrate. In this case, the plating electric current
may be supplied through the metal film.
[0056] Furthermore, in accordance with another aspect of the
present invention, there is provided a semiconductor integrated
circuit comprising a semiconductor substrate (wafer) having a bump
electrode formation area and a bump electrode non-formation area
respectively defined on a surface thereof; a first electrode pad
formed in the bump electrode non-formation area; a second electrode
pad formed in the bump electrode formation area; and a bump
electrode formed on the second electrode pad; wherein the first
electrode pad is used for supplying a plating electric current to
the second electrode pad through the semiconductor substrate in
formation of the bump electrode by electrolytic plating.
EMBODIMENTS
[0057] With reference to the attached drawings, the present
invention will hereinafter be described in detail by way of
embodiments thereof. It should be understood that the invention be
not limited to the embodiments.
Embodiment 1
[0058] A semiconductor integrated circuit and a fabrication process
therefor according to Embodiment 1 of the invention will be
described with reference to FIGS. 1 to 4. Fig. 1 is a sectional
view illustrating the semiconductor integrated circuit according to
Embodiment 1 of the invention, and FIGS. 2(a) to 2(e) and FIGS.
3(f) and 3(g) are process diagrams for explaining a fabrication
process for the semiconductor integrated circuit shown in FIG. 1.
FIG. 4 is a graph illustrating a comparison between height
variations of bump electrodes formed by a fabrication process
according to Embodiment 1 and height variations of bump electrodes
formed by a conventional fabrication process. In the following
embodiments, like components are denoted by like reference
characters.
[0059] As shown in FIG. 1, the semiconductor integrated circuit 13
according to Embodiment 1 of the invention includes a wafer
(semiconductor substrate) 1 having a plurality of bump electrode
formation areas A and a bump electrode non-formation area B
respectively defined on a front surface thereof, a first electrode
pad 12 formed in the bump electrode non-formation area B, a second
electrode pad 3 formed in each bump electrode formation area A, and
a bump electrode 7 formed on each second electrode pad 3. The first
electrode pad 12 is used for supplying a plating electric current
to the second electrode pads 3 through the wafer 1 from a back
surface of the wafer 1 in formation of the bump electrodes 7 by
electrolytic plating.
[0060] More specifically, an insulating film 2 is provided on the
wafer 1, and second electrode pads 3 are provided on the insulating
film 2. The second electrode pads 3 are partly protected by a
protective film 4, and a metal base film 5 is provided between the
bump electrodes 7 and the second electrode pads
[0061] The wafer 1 forms an integrated circuit (not shown) inside
thereof. A wiring pattern (not shown) extends from the second
electrode pads 3 to the integrated circuit and is electrically
connected to the integrated circuit via a contact hole (not shown)
opened at insulating film 2.
[0062] Eventually, each bump electrode 7 is electrically connected
to the integrated circuit through the wiring pattern.
[0063] Referring to FIGS. 2 and 3, an explanation will be given to
a process for forming the bump electrodes 7 of the semiconductor
integrated circuit 13 of Embodiment 1 shown in FIG. 1. Where the
bump electrode formation process employs the same process
conditions as in an ordinary semiconductor integrated circuit
fabrication process, a detailed explanation will not be given
thereto.
[0064] As shown in FIG. 2 (a) , an insulating film 2 having a
thickness of about 1 .mu.m is formed on the entire front surface of
a wafer 1 incorporating a integrated circuit by a CVD method, and
then an opening is formed in the insulating film 2 in the vicinity
of bump electrode formation areas A by a photolithography technique
for formation of a bump electrode non-formation area B.
[0065] The bump electrode non-formation area B has substantially
the same size and shape as bump electrodes 7 (see FIG. 1) to be
formed in this embodiment, for example, a 40 .mu.m.times.40 .mu.m
square shape, to allow for passage of a sufficient plating electric
current.
[0066] Then, a metal film is formed over the entire front surface
of the wafer 1 by a sputtering method, and patterned by a
photolithography technique and an etching technique for formation
of second electrode pads 3 and a first electrode pad 12 for
supplying the plating electric current as shown in FIG. 2 (b). The
first electrode pad 12 is formed directly on the wafer 1 for
electrical connection to the wafer 1.
[0067] As shown in FIG. 2 (c), a protective film 4 having a
thickness of about 1 .mu.m is formed over the resulting wafer, and
openings are formed in the protective film 4 to expose parts of the
second electrode pads 3 and the first electrode pad 12.
[0068] In turn, a metal base film 5 composed of a single metal or
plural types of metals is formed over the resulting wafer by a
sputtering method as shown in FIG. 2 (d).
[0069] As shown in FIG. 2 (e) , a photoresist film 6 is formed over
the metal base film 5, and openings are formed in the photoresist
film 6 in the bump electrode formation areas A.
[0070] Thereafter, the resulting wafer 1 is set in a plating device
101 as shown in FIG. 3 (f). The wafer 1 is set with a bump
electrode formation surface thereof facing downward to be opposed
to an anode electrode 10, and cathode electrodes 8 are connected to
the back surface of the wafer 1 opposite from the bump electrode
formation surface.
[0071] In the plating device 101, a plating liquid 9 is fountained
from an inner lower side of the device toward the bump formation
surface, and then discharged from the periphery of the wafer 1
outside the plating device 101.
[0072] In this state, a voltage is applied between the anode
electrode 10 and the cathode electrodes 8, whereby the plating
electric current is supplied to the metal base film 5 through the
first electrode pad 12 adjacent to the bump electrode formation
areas A as shown in FIG. 3 (g). Thus, the bump electrodes 7 are
formed.
[0073] Then, the photoresist film 6 is removed, and a portion of
the metal base film 5 is removed by using the bump electrodes 7 as
a mask. Thus, the semiconductor integrated circuit 13 shown in FIG.
1 is fabricated.
[0074] Referring to FIG. 4, an explanation will be given to height
variations of the bump electrodes 7 formed by the fabrication
process according to Embodiment 1 and height variations of the bump
electrodes formed by the first to third conventional methods (see
FIGS. 7 to 9).
[0075] Where a plurality of 20-.mu.m high bump electrodes were
formed on a 5-inch wafer and a 6-inch wafer each incorporating an
integrated circuit by the fabrication process according to
Embodiment 1, a maximum height variation of the bump electrodes
over the wafer was suppressed to 2 to 3 .mu.m as indicated by a
line (a) in FIG. 4.
[0076] Where a plurality of 20-.mu.m high bump electrodes were
formed on a 5-inch wafer and a 6-inch wafer each incorporating an
integrated circuit by the first to third conventional methods, on
the other hand, a maximum height variation of the bump electrodes
over the wafer was 4 to 6 .mu.m as indicated by a line (b) in FIG.
4.
[0077] In general, the height variations of the bump electrodes are
required to be suppressed to not greater than 4 .mu.m in a
semiconductor integrated circuit mounting process. The height
variations of the bump electrodes formed by the fabrication process
according to Embodiment 1 satisfy this requirement.
Embodiment 2
[0078] With reference to FIG. 5, an explanation will be given to a
semiconductor integrated circuit according to Embodiment 2 of the
present invention. FIG. 5 is a sectional view of a semi-finished
semiconductor integrated circuit (corresponding to FIG. 3 (g) in
Embodiment 1) in a bump electrode formation process according to
Embodiment 2 of the invention.
[0079] As shown in FIG. 5, the semiconductor integrated circuit 14
according to Embodiment 2 of the invention includes a metal film 11
provided on the entire back surface of a wafer 1. The metal film 11
serves for connection to a cathode electrode 8, and is electrically
connected to a metal base film 5. The other construction of the
semiconductor integrated circuit 14 is the same as that of
Embodiment 1 described above.
[0080] With the metal film 11 provided over the entire back surface
of the wafer 1, a resistance to the plating electric current
supplied from the cathode electrode 8 for formation of bump
electrodes 7 can be reduced.
[0081] In accordance with the present invention, the first
electrode pad is provided in the bump electrode non-formation area
for supplying the plating electric current to the second electrode
pads through the semiconductor substrate in the formation of the
bump electrodes by the electrolytic plating. Therefore, the plating
electric current can evenly be supplied over the semiconductor
substrate (wafer) , so that the bump electrodes of the
semiconductor integrated circuit are uniform in height.
* * * * *