U.S. patent application number 10/097472 was filed with the patent office on 2002-07-25 for method and apparatus for providing seamless hooking and intercepting of selected kernel and hal exported entry points.
Invention is credited to Bonola, Thomas J..
Application Number | 20020099874 10/097472 |
Document ID | / |
Family ID | 22543587 |
Filed Date | 2002-07-25 |
United States Patent
Application |
20020099874 |
Kind Code |
A1 |
Bonola, Thomas J. |
July 25, 2002 |
Method and apparatus for providing seamless hooking and
intercepting of selected kernel and HAL exported entry points
Abstract
In a computer system having at least one host processor, a
method and apparatus for providing seamless hooking and
interception of selected entrypoints includes finding the IDT for
each CPU which can include scanning the HAL image for the HAL PCR
list. Saving the interrupt handler currently mapped in the CPU's
interrupt descriptor table. Patching the original interrupt into
the new interrupt handler. Storing the new interrupt exception into
the CPU's interrupt descriptor table. Hooking a select entrypoint
by first determining if the entrypoint begins with a one byte
instruction code. If it does, saving the address of the original
entrypoint, saving the original first one byte instruction, and
patching the new interrupt intercept routine to jump to the
original entrypoint's next instruction
Inventors: |
Bonola, Thomas J.; (Tomball,
TX) |
Correspondence
Address: |
Michael G. Fletcher
Fletcher, Yoder & Van Someren
P.O. Box 692289
Houston
TX
77269-2289
US
|
Family ID: |
22543587 |
Appl. No.: |
10/097472 |
Filed: |
March 14, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10097472 |
Mar 14, 2002 |
|
|
|
09788899 |
Feb 20, 2001 |
|
|
|
09788899 |
Feb 20, 2001 |
|
|
|
09152597 |
Sep 14, 1998 |
|
|
|
6275893 |
|
|
|
|
Current U.S.
Class: |
710/1 |
Current CPC
Class: |
G06F 13/24 20130101 |
Class at
Publication: |
710/1 |
International
Class: |
G06F 003/00 |
Claims
What is claimed is:
1. A computer system comprising: at least one processor; an
operating system having at least one entrypoint; a module for
hooking said at least one entrypoint; and said module further for
selectively executing a routine subsequent to hooking said at least
one entrypoint.
2. The computer system as recited in claim 1, wherein said
operating system is a kernel based operating system.
3. The computer system as recited in claim 2, wherein said at least
one entrypoint is a kernel entrypoint
4. The computer system as recited in claim 1, wherein said
operating system includes a hardware abstraction layer, and further
wherein said at least one entrypoint is a hardware abstraction
layer entrypoint.
5. The computer system as recited in claim 1, wherein said module
for hooking said at least one entrypoint further for determining if
said at least one entrypoint begins with a one byte instruction,
such that if the determination is made that said at least one
entrypoint does not begin with a one byte instruction, said at
least one entrypoint is not hooked.
6. The computer system as recited in claim 5, wherein said module
for hooking said at least one entrypoint further for placing an
interrupt instruction into the first byte of the entrypoint if the
determination is made that said at least one entrypoint does begin
with a one byte instruction.
7. A computer system comprising: at least one host processor; an
operating system having a hardware abstraction layer associated
therewith, said hardware abstraction layer having at least one
entrypoint, a module for hooking said at least one entrypoint, and
said module further for selectively executing a routine subsequent
to hooking said at least one entrypoint.
8. The computer system as recited in claim 7, and further
comprising an interrupt descriptor table associated with said at
least one host processor, and further wherein said module for
hooking said at least one entrypoint further for storing a new
interrupt exception into the interrupt descriptor table for said at
least one host processor.
9. The computer system as recited in claim 8, wherein said module
for hooking said at least one entrypoint further for determining if
said at least one entrypoint begins with a one byte instruction,
such that if the determination is made that said at least one
entrypoint does not begin with a one byte instruction, said at
least one entrypoint is not hooked.
10. The computer system as recited in claim 9, wherein said first
module for hooking said at least one entrypoint further for placing
a new interrupt instruction associated with said new interrupt
exception into the first byte of the entrypoint if the
determination is made that said at least one entrypoint does begin
with a one byte instruction.
11. In a computer system having at least one host processor, a
method for selectively hooking a public entrypoint, said method
comprising the steps of: determining if the entrypoint begins with
a one byte instruction, such that if the determination is made that
the entrypoint begins with a one byte instruction; saving the
address of the original entrypoint, and placing an interrupt
instruction into the first byte of the entrypoint.
12. The method as recited in claim 11, and further comprising the
step of scanning the hardware abstraction layer image for the
hardware abstraction layer table of system processor control
registers for the at least one host processor.
13. The method as recited in claim 12, and further comprising the
step of saving a select interrupt handler currently mapped in the
interrupt descriptor table of the at least one host processor.
14. The method as recited in claim 13, and further comprising the
step of patching the select interrupt handler into a new interrupt
handler.
15. The method as recited in claim 14, and further comprising the
step of storing the new interrupt handler into the interrupt
descriptor table for the at least one host processor.
Description
FIELD OF INVENTION
[0001] The present invention relates to computer systems, and more
particularly, but not by way of limitation, to a method and
apparatus for providing seamless hooking and interception of
selected entrypoints of an operating system, such as entrypoints of
either the kernel or the hardware abstraction layer
BACKGROUND OF THE INVENTION
[0002] One of the key factors in the performance of a computer
system is the speed at which the central processing unit (CPU)
operates. Generally, the faster the CPU operates, the faster the
computer system can complete a designated task. Another method of
increasing the speed of a computer system is through the use of
multiple CPUs. This is commonly known as multiprocessing. With
multiple CPUs, algorithms required to complete a task can be
executed substantially in parallel as opposed to their sequential
execution, thereby decreasing the total time to complete the
task.
[0003] However, as CPUs are dependent upon peripherals for
providing data to the CPU and storing the processed data from the
CPU, when a CPU needs to read or write to a peripheral, the CPU is
diverted from a current algorithm to execute the read/write
transaction. As can be appreciated, the length of time that the CPU
is diverted is typically dependent upon the speed of the I/O
transaction.
[0004] One advancement developed to increase the efficiency of I/O
transactions is the intelligent input/output (I.sub.2O)
architecture. In the I.sub.2O approach to I/O, low-level interrupts
are off loaded from a CPU to I/O processors (IOPs). The IOPs are
additional processors that specifically handle I/O With support for
message-passing between multiple independent processors, the
I.sub.2O architecture relieves the host processor of
interrupt-intensive I/O tasks, greatly improving I/O performance
especially in high-bandwidth applications such as networked video,
groupware, and client/server processing.
[0005] Typical I.sub.2O architectures use a "split driver" model
which inserts a messaging layer between the portion of the device
driver specific to the operating system and the portion of the
device driver specific to the peripheral. The messaging layer
splits the single device driver of today into two separate modules,
an Operating System Service Module (OSM), and a Downloadable Driver
Module (DDM). The only interaction one module has with another
module is through this messaging layer.
[0006] The OSM comprises the portion of the device driver which is
specific to the operating system. The OSM interfaces with the
operating system of the computer system (which is commonly referred
to in the art as the "host operating system") and is executed by
the CPU. Typically, a single OSM may be used to service a specific
class of peripherals. For example, one OSM would be used to service
all block storage devices, such as hard disk drives, and CD-ROM
drives.
[0007] The DDM provides the peripheral-specific portion of the
device driver that understands how to interface to the particular
peripheral hardware To execute the DDM, an IOP is added to the
computer system. A single IOP may be associated with multiple
peripherals, each controlled by a particular DDM, and contains its
own operating system such as, for example, the I.sub.2O Real-Time
Operating System (iRTOS). The DDM directly controls the peripheral,
and is executed by the IOP under the management of the iRTOS.
[0008] In general operation, the communications model used in the
I.sub.2O architecture is a message passing system. When the CPU
seeks to read or write to a peripheral in an I.sub.2O system, the
host operating system makes what is known as a "request". The OSM
translates the request by the host operating system and, in turn,
generates a message. The OSM sends the message across the messaging
layer to the DDM associated with the peripheral which processes it
appropriately to achieve a result. Upon completion of the
processing, the DDM sends the result back to the OSM by sending a
message through the messaging layer. It can be appreciated that to
the host operating system, the OSM appears just like any other
device driver
[0009] By executing the DDM on the IOP, the time-consuming portion
of transferring information from and to the peripheral hardware is
off-loaded from the CPU to the IOP With this off-loading, the CPU
is no longer diverted for inordinate amounts of time during an I/O
transaction. Moreover, because the IOP is a hardware component
essentially dedicated to the processing of the I/O transactions,
the problem of I/O bottlenecking is mitigated. Accordingly, any
performance gains to be achieved by adding an additional or faster
CPU to the computer system may be unhindered by the I/O processing
bottleneck.
[0010] There are three common approaches to implement the I.sub.2O
architecture. The first is an IOP installed on the motherboard of
the computer system. In this approach, the IOP is installed
directly on the motherboard and is used for I.sub.2O processing. In
this particular configuration, the IOP is often used as a standard
PCI bridge, and can also be used to bring intelligence to the PCI
bus.
[0011] The second approach is to include an IOP on adapter cards,
such that with an IOP on an adapter card, IT managers can add
intelligent I/O to the computer system by adding an additional
adapter
[0012] The third approach is to install the IOP in the computer
system via an optional plug-in card This allows systems to be
populated with one IOP per host adapter plugged into a slot instead
of on the motherboard
[0013] Although the intent of I.sub.2O was the implementation of
portable, high-performance intelligent I/O systems there exists a
number of problems with I.sub.2O architecture. As is,often the
case, one problem is cost. The inclusion or the addition of
additional hardware and extra processors (the IOPs) to a computer
system will ultimately raise the price of the system.
[0014] Another problem arises as a result of the direction the
computer industry has taken in the adoption of an IOP "standard".
Currently, the computer industry is pushing to adopt the Intel i960
processor for the industry standard I.sub.2O IOP Some of the
problems with the i960 include computing and speed problems,
especially when the i960 is compared to other existing processors
on the market.
[0015] In a multiprocessor system environment one proposed solution
to the i960 IOP is to use software to solely dedicate at least one
of the host processors to controlling the I/O. As can be
appreciated, current system processors have very superior computing
power and speed as compared with the i960. Another advantage of a
host processor IOP is that no additional hardware needs to be
purchased or added This is especially true when upgrading an
existing computer system to be I.sub.2O compliant. However, in
making a computer system I.sub.2O compliant by dedicating a host
processor, many problems have been encountered One problem is
making the dedicated host processor appear to the rest of the
computer system to be an I.sub.2O IOP in a seamless manner. It is
desired that a computer system having a host processor IOP appear
to a user to be a typical I.sub.2O compliant computer system in all
aspects including software interaction and hardware
interaction.
[0016] Many existing computer systems utilize kernel based
operating systems In a kernel based operating system, such as
Windows NT, the operating system has a layered architecture. In
this type of operating system, the kernel is at the core of the
layered architecture and manages only basic operating system
functions. The kernel is responsible for thread dispatching,
multiprocessor synchronization, and hardware exception
handling.
[0017] Another piece of software often associated with the
operating system is the hardware abstraction layer (HAL). The HAL
is an isolation layer of software that hides, or abstracts hardware
differences from higher layers of the operating systems. Because of
the HAL, the different types of hardware all look alike to the
operating system, removing the need to specifically tailor the
operating system to the hardware with which it communicates.
Ideally, the HAL provides routines that allow a single device
driver to support the same device on all platforms
[0018] HAL routines can be called from both the base operating
system, including the kernel, and from device drivers The HAL
enables device drivers to support a wide variety of I/O
architectures without having to be extensively modified. The HAL is
also responsible for hiding the details of symmetric
multiprocessing hardware from the rest of the operating system.
[0019] In the early days of Windows NT, it was common practice for
the hardware OEMs to be responsible for providing the HAL software
for their particular hardware to the manufacturer of the operating
system. As multiprocessing systems became more commonplace, there
was a shift from the hardware OEMs supplying the HAL routines, to
the OS manufacturer supplying the HAL routines for all the hardware
OEMs.
[0020] Therefore, as can be further appreciated, when making of a
computer system I.sub.2O compliant by dedicating at least one of
the host processors for an IOP, it is not practical to modify an
existing operating system or HAL Rather it would be more
advantageous to provide "routines" that are seamlessly hooked into
the operating system
SUMMARY OF THE INVENTION
[0021] The present invention overcomes the above identified
problems as well as other shortcomings and deficiencies of existing
technologies by providing a method and apparatus for seamless
hooking and interception of selected entrypoints of an operating
system, such as entrypoints of either the kernel or the hardware
abstraction layer.
[0022] The present invention further provides, in a computer system
having at least one host processor, a method and apparatus for
providing seamless hooking and interception of selected entrypoints
by first scanning the HAL image for the HAL PCR list, whereupon the
interrupt handler currently mapped in the CPU's interrupt
descriptor table is then saved. The original interrupt is then
patched into a new interrupt handler Then the new interrupt
exception is stored into the CPU's interrupt descriptor table
Subsequent thereto, a select entrypoint is hooked by first
determining if the entrypoint begins with a one byte instruction
code If it does, the address of the original entrypoint is saved
The new interrupt intercept routine is then patched to jump to the
original entrypoint's next instruction for selected conditions
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] A more complete understanding of the present invention may
be had by reference to the following Detailed Description and
appended claims when taking in conjunction with the accompanying
Drawings wherein:
[0024] FIG. 1 is a schematic block diagram of a computer system
utilizing the present invention,
[0025] FIG. 2 is a schematic diagram of an exemplary embodiment of
an operating system in accordance with the principles of the
present invention;
[0026] FIG. 3 is a block flow diagram illustrating an exemplary
embodiment of a routine or method for seamlessly hooking and
intercepting selected exported entrypoints without the need to
provide a modified kernel or HAL,
[0027] FIG. 4 is a block flow diagram illustrating an exemplary
embodiment of a hook routine in accordance with the principles of
the present invention, and
[0028] FIG. 5 is a block flow diagram illustrating an exemplary
embodiment of how a hooked entrypoint is handled in accordance with
the principles of the present invention when a select interrupt
exception occurs
DETAILED DESCRIPTION
[0029] With reference to FIGS. 1, 2, 3, 4 and 5 there are shown
block diagrams illustrating an exemplary embodiment of the present
invention. The purpose of these block diagrams is to illustrate,
among other things, the features of the present invention and the
basic principles of operation thereof. These block diagrams are not
necessarily intended to schematically represent particular modules
of circuitry or control paths.
[0030] Referring now to FIG. 1, there is illustrated a schematic
block diagram of a computer system 100. As illustrated, computer
system 100 is a multiprocessor system and contains the following:
multiple host processors 110, 112, 114 and 116; module 118 which
contains the operating system; module 120 which contains I.sub.2O
software; and associated hardware 122. As depicted, the associated
hardware 122 includes items such as a LAN controller 124, SCSI
controller 126, audio controller 128, and graphics controller
130.
[0031] As computer system 100 is a multiprocessing computer, it is
able to execute multiple threads simultaneously, one for each of
the processors therein Further it is contemplated that the
processors in computer system 100 can operate either
asymmetrically, symmetrically, or in a combination thereof
[0032] Although the present invention is illustrated in a computer
system having four host processors, it is contemplated that the
present invention could also be utilized in a computer system with
virtually any number of host processors, including, but not limited
to a single host processor.
[0033] In this particular embodiment of computer system 100, the
I.sub.2O software of module 120 is utilized to dedicate one or more
of the processors (such as processor 116) for use as a input/output
processor (IOP) such that computer system 100 is an I.sub.2O
compliant computer system.
[0034] Referring now to FIG. 2, there is illustrated a more
detailed block diagram of an exemplary architecture for operating
system 118 As depicted the architecture of operating system 118 is
a kernel based operating system. Operating system 118 includes
subsystems 210 (which operate in user mode), and system or
executive services 212 (which operate in kernel mode). Executive
services 212 are made up of multiple components, such as the I/O
manager 214, the object manager, the security reference monitor
218, the process manager 220, the local procedure call facility
222, the virtual memory manager, 224, the kernel 226, and the
hardware abstraction layer (HAL) 228 The components that make up
the executive services provide basic operating system services to
subsystems 210 and to each other. The components are generally
completely independent of one another and communicate through
controlled interfaces.
[0035] Still referring to FIG. 2, the I/O manager 214 manages all
input and output for the operating system including the managing of
the communications between drivers of computer system 100; Object
manger 216 is for creating, managing, and deleting executive
objects. Security reference monitor 218 is utilized to ensure
proper authorization before allowing access to system resources
such as memory, I/O devices, files and directories. Process manager
220 manages the creation and deletion of processes by providing a
standard set of services for creating and using threads and
processes in the context of a particular subsystem environment
Local procedure call facility 222 is a message-passing mechanism
for controlling communication between the client and server when
they are on the same machine. Virtual memory manager 224 maps
virtual addresses in the process' address space to physical pages
in the computer's memory
[0036] Still referring to FIG. 2, kernel 226 is the core of the
architecture of operating system 1 18 and manages the most basic of
the operating system functions. It is responsible for thread
dispatching, multiprocessor synchronization, and hardware exception
handling.
[0037] Still referring to FIG. 2, in this particular embodiment
applications utilized in computer system 100 are kept separate from
the operating system 118 itself. Operating system 118 runs in a
privileged processor mode known as kernel-mode and has access to
system data and hardware. Applications run in a nonprivileged
processor mode known as user mode and have limited access to system
data and hardware through a set of tightly controlled application
programming interfaces (APIs) or entrypoints.
[0038] In this exemplary embodiment, good results have also been
achieved in the present invention by using a microkernel-based
operating system for operating system 118 In a microkernel-based
operating system, only the functions that can not be reasonably
performed elsewhere remain in the kernel The functionalities that
are removed from the standard kernel are put in subsystems 210
Subsystems 210 provide the traditional operating system support to
applications through a set of APIs.
[0039] Hardware abstraction layer (HAL) 228 is an isolation layer
of software that hides, or abstracts hardware differences from
higher layers of the operating system. Through the utilization of
HAL 228, the different types of hardware all "look" alike to the
operating system. The HAL 228 removes the need to specifically
tailor the operating system to the hardware with which it
communicates. Routines of HAL 228 can be called from both the base
operating system (including the kernel) and from the device
drivers.
[0040] In this exemplary computer system, the processors 110-116
provide two mechanisms for interrupting program execution
interrupts and exceptions. An interrupt is an asynchronous event
that is typically triggered by an I/O device. An exception is a
synchronous event that is generated when the processor detects one
or more predefined conditions while executing an instruction.
[0041] Interrupts are forced transfers of execution from the
currently running program or task of a processor to a special
procedure to task called an interrupt handler. Interrupts typically
occur at random times during the execution of a program, in
response to signals from hardware They are used to handle events
external to the processor, such as requests to service peripheral
devices. Software can also generate interrupts by executing the INT
n instruction.
[0042] Generally a processor's interrupt handling mechanism allows
interrupts to be handled transparently to application programs and
the operating system or executive. When an interrupt is signaled,
the processor halts execution of the current program or task and
switches to an interrupt handler procedure that is written
specifically to handle the interrupt condition. The processor
accesses the interrupt handler procedure through an entry in the
interrupt descriptor table (IDT).
[0043] When execution of the interrupt handler is complete, the
processor resumes execution of the interrupted procedure or task.
The resumption of the interrupted procedure or task happens without
loss of program continuity, unless the interrupt caused the
currently running program to be terminated.
[0044] As described hereinabove, a processor can receive interrupts
from two sources. The first is from external (hardware generated)
interrupts. External interrupts are generally received through pins
on the processor or through the local APIC serial bus
[0045] The second source of interrupts is from software-generated
interrupts A very common software-generated interrupt is the INT n
instruction. The INT n instruction generates a call to the
interrupt or exception handler specified with the destination
operand The destination operand specifies an interupt vector number
The interrupt vector number specifies an interrupt descriptor in
the interrupt descriptor table (IDT), i.e., it provides index into
the IDT. The selected interrupt descriptor in turn contains a
pointer to an interrupt or exception handler procedure.
[0046] A particular call to interrupt procedure is the Int03 The
Int03 instruction generates a special one byte opcode (CC) that is
intended for calling the debug exception handler. This one byte
form for Int03 is valuable because it can be used to replace the
first byte of any instruction with a breakpoint, including other
one-byte instructions, without over-writing other code.
[0047] Referring now to FIG. 3, there is illustrated a block flow
diagram 300 illustrating a routine or method for seamlessly hooking
and unhooking selected exported entrypoints without the need to
provide a special kernel or HAL This is performed so that an
alternative routine can be selectively substituted for the selected
entrypoint routines Although illustrated as part of the I.sub.2O
software, it is contemplated that the present invention is not
limited to this type of software, rather could be utilized in
virtually any type of software or hardware
[0048] As depicted by block 310, the IDT for each CPU is found This
step could include scanning the HAL image for each of the
processors in the computer system for the table of system processor
control registers (PCRs) There is generally one PCR per processor
in the computer system 100. Subsequent thereto, as indicated by
block 312, the original Int03 handler mapped in each CPU's IDT
entry 3 is saved, this includes saving the contents of the original
Int03 vector information. Then, as indicated by block 314, the
original Int03 handler code is patched into the new Int03 handler
code. This is performed so that a direct jump can be made to the
original Int03 handler code if the exception is not for
interception.
[0049] Then, as indicated by block 316, the new Int03 vector
information is loaded into the IDT of each of the processors. This
code is responsible for intercepting Int03 exceptions and
dispatching the new Int03 exceptions to a corresponding new
routine. Any Int03's not created by the new routine will be
forwarded to the original dispatch handler provided by the
operating system.
[0050] Then, as indicated by block 318, the selected entrypoints,
from either the HAL or kernel are hooked Generally, blocks 310-318
are performed during the initialization sequence of the computer
system An exemplary hooking routine is given in detail hereinbelow
with reference to FIG. 4
[0051] Still referring to FIG. 3, as indicated by block 320,
entrypoints no longer requiring interception are then unhooked An
example of when this occurs is at a select time after the
initialization sequence, certain entrypoints may no longer be
needed whereby these entrypoints should operate in a "normal"
routine, thus the unneeded entrypoints are unhooked.
[0052] Referring now to FIG. 4, there is illustrated a block
diagram 400 illustrating an exemplary embodiment of a hooking
routine in accordance with the principles of the present
invention.
[0053] As depicted in block 410, a determination is first made
whether a selected entrypoint begins with a one byte instruction.
If it does not begin with a one byte instruction, the "no" branch
is followed to block 418 where the routine ends without hooking the
selected entrypoint.
[0054] If the determination is made that the entrypoint begins with
a one byte instruction, the "yes" branch is followed to block 412
The address of the original entrypoint are saved in the data
structure of the new or substitute routine As indicated by block
413, the original 1 byte instruction is then saved into the new
Int03 intercept routine Then, as indicated by block 414, the new
Int03 intercept routine is patched to jump to the original
entrypoint's next instruction. This is done for instances when the
encountered Int03 is not the new Int03
[0055] Then, as indicated by block 416, the first byte of the
original entrypoint is replaced by an Int03 instruction. This is
performed, such that all callers of this particular entrypoint will
cause an Int03 exception to occur and vector to the new driver's
INT03 handler.
[0056] Referring now to FIG. 5, there is illustrated a block flow
diagram 500 of an exemplary embodiment of how the hooked entrypoint
is handled in accordance with the principles of the present
invention when an INT03 exception occurs. Because the first byte
location of the hooked entrypoint is the INT03, the INT03 exception
is executed by all callers of the entrypoint. As depicted by block
510 whenever an INT03 is encountered, a determination is made as to
the caller or origin of the interrupt. If the determination is made
that the caller of the interrupt is not a caller of interest for
the particular new routine, then the "no" branch is followed to
block 512, where the routine jumps back to the original routine for
the caller of the interrupt. If the determination is made that the
caller of the interrupt is a caller of interest for the particular
new routine the "yes" branch is followed to block 514, where a jump
is made to the new routine
[0057] Therefore, as can be appreciated by one of ordinary skill in
the art, the present invention provides, in a computer system
having at least one host processor, a method and apparatus for
providing seamless hooking and interception of selected
entrypoints. The HAL image for the HAL PCR list is scanned,
whereupon the interrupt handler currently mapped in the CPU's
interrupt descriptor table is saved. The original interrupt is then
patched to the new interrupt handler. Then the new interrupt
exception is stored into the CPU's interrupt descriptor table. A
select entrypoint is hooked by first determining if the entrypoint
begins with a one byte instruction code. If it does, the address of
the original entrypoint is saved. The new interrupt intercept
routine is patched to jump to the original entrypoint's next
instruction for selected conditions.
[0058] Although a preferred embodiment of the present invention has
been illustrated in the accompanying Drawings and described in the
foregoing Detailed Description, it will be understood that he
invention is not limited to the embodiment disclosed, but is
capable of numerous rearrangements, modifications and substitutions
without departing from the spirit of the invention as set forth and
defined by the following claims
* * * * *