U.S. patent application number 09/752250 was filed with the patent office on 2002-07-04 for duty cycle control loop.
Invention is credited to Mooney, Stephen, Nair, Rajendran, Narendra, Siva G., Wright, Chantal.
Application Number | 20020084817 09/752250 |
Document ID | / |
Family ID | 25025523 |
Filed Date | 2002-07-04 |
United States Patent
Application |
20020084817 |
Kind Code |
A1 |
Nair, Rajendran ; et
al. |
July 4, 2002 |
DUTY CYCLE CONTROL LOOP
Abstract
An output circuit generates an output signal. The output signal
has a duty cycle from an input signal. A level extractor couple to
the output circuit to extract a direct current (DC) level from the
output signal. The DC level is a representative of the duty cycle.
An integrator couple to the level extractor to integrate the DC
level. The integrator generates a current control signal to adjust
the duty cycle.
Inventors: |
Nair, Rajendran; (Hillsboro,
OR) ; Wright, Chantal; (Portland, OR) ;
Mooney, Stephen; (Beaverton, OR) ; Narendra, Siva
G.; (Beaverton, OR) |
Correspondence
Address: |
CAROLINE T. DO
BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN, LLP
7th Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025
US
|
Family ID: |
25025523 |
Appl. No.: |
09/752250 |
Filed: |
December 28, 2000 |
Current U.S.
Class: |
327/175 |
Current CPC
Class: |
H03K 5/1565
20130101 |
Class at
Publication: |
327/175 |
International
Class: |
H03K 003/017; H03K
005/04; H03K 007/08 |
Claims
What is claimed is:
1. An apparatus comprising: an output circuit to generate an output
signal having a duty cycle from an input signal; a level extractor
coupled to the output circuit to extract a direct current (DC)
level from the output signal, the DC level being representative of
the duty cycle; and an integrator coupled to the level extractor to
integrate the DC level, the integrator generating a current control
signal to adjust the duty cycle.
2. The apparatus of claim 1 wherein the output circuit comprises:
an output device to provide the output signal according to the
input signal; and a bias current source coupled to the output
device and the integrator to provide bias current to the output
device using the current control signal, the bias current adjusting
the duty cycle of the output signal.
3. The apparatus of claim 2 wherein the output device comprises: an
output p-device; and an output n-device coupled to the output
p-device to form an inverter, the inverter inverting the input
signal.
4. The apparatus of claim 3 wherein the bias current source
comprises: a bias p-device coupled to the output p-device to adjust
a p-current according to the current control signal; and a bias
n-device coupled to the output n-device to adjust an n-current
according to the current control signal, the p-current and the
n-current forming the bias current.
5. The apparatus of claim 3 wherein the integrator comprises: a
p-integrator coupled to the low-pass filter to generate a p-control
signal; and an n-integrator coupled to the low-pass filter to
generate an n-control signal, the p-control and the n-control
signals forming the current control signal
6. The apparatus of claim 5 wherein the bias current source
comprises: a bias p-device coupled to the output p-device to adjust
a p-current according to the p-control signal; and a bias n-device
coupled to the output n-device to adjust an n-current according to
the n-control signal, the p-current and the n-current forming the
bias current.
7. The apparatus of claim 4 wherein the current control signal
controls the bias p-device and the bias n-device in a complementary
mode.
8. The apparatus of claim 6 wherein the p-control signal and the
n-control signal controls the bias p-device and the bias n-device,
respectively, in a complementary mode.
9. The apparatus of claim 4 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
10. The apparatus of claim 6 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
11. A method comprising: generating an output signal having a duty
cycle from an input signal by an output circuit; extracting a
direct current (DC) level from the output signal, the DC level
being representative of the duty cycle; and integrating the DC
level to generate a current control signal, the current control
signal adjusting the duty cycle.
12. The method of claim 11 wherein generating comprises: providing
the output signal according to the input signal by an output
device; and providing bias current to the output device using the
current control signal by a bias current source, the bias current
adjusting the duty cycle of the output signal.
13. The method of claim 12 wherein providing the output signal
comprises: inverting the input signal by an output p-device and an
output n-device.
14. The method of claim 13 wherein providing bias current
comprises: adjusting a p-current according to the current control
signal by a bias p-device; and adjusting an n-current according to
the current control signal by a bias n-device, the p-current and
the n-current forming the bias current.
15. The method of claim 13 wherein integrating comprises:
generating a p-control signal by a p-integrator; and generating an
n-control signal by an n-integrator, the p-control and the
n-control signals forming the current control signal.
16. The method of claim 15 wherein providing bias current
comprises: adjusting a p-current according to the p-control signal
by a bias p-device; and adjusting an n-current according to the
n-control signal by a bias n-device, the p-current and the
n-current forming the bias current.
17. The method of claim 14 wherein integrating comprises
controlling the bias p-device and the bias n-device in a
complementary mode.
18. The method of claim 16 wherein the p-control signal and the
n-control signal control the bias p-device and the bias n-device,
respectively, in a complementary mode.
19. The method of claim 14 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
20. The method of claim 16 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
21. A system comprising: a clock signal generator to generate a
clock signal; an output circuit coupled to the clock signal
generator to generate an output signal having a duty cycle from the
clock signal; and a duty cycle control circuit coupled to the
output circuit to control the duty cycle of the output signal
comprising: a level extractor coupled to the output circuit to
extract a direct current (DC) level from the output signal, the DC
level being representative of the duty cycle, and an integrator
coupled to the level extractor to integrate the DC level, the
integrator generating a current control signal to adjust the duty
cycle.
22. The system of claim 21 wherein the output circuit comprises: an
output device to provide the output signal according to the input
signal; and a bias current source coupled to the output device and
the integrator to provide bias current to the output device using
the current control signal, the bias current adjusting the duty
cycle of the output signal.
23. The system of claim 22 wherein the output device comprises: an
output p-device; and an output n-device coupled to the output
p-device to form an inverter, the inverter inverting the input
signal.
24. The system of claim 23 wherein the bias current source
comprises: a bias p-device coupled to the output p-device to adjust
a p-current according to the current control signal; and a bias
n-device coupled to the output n-device to adjust an n-current
according to the current control signal, the p-current and the
n-current forming the bias current.
25. The system of claim 23 wherein the integrator comprises: a
p-integrator coupled to the low-pass filter to generate a p-control
signal; and an n-integrator coupled to the low-pass filter to
generate an n-control signal, the p-control and the n-control
signals forming the current control signal
26. The system of claim 25 wherein the bias current source
comprises: a bias p-device coupled to the output p-device to adjust
a p-current according to the p-control signal; and a bias n-device
coupled to the output n-device to adjust an n-current according to
the n-control signal, the p-current and the n-current forming the
bias current.
27. The system of claim 24 wherein the current control signal
controls the bias p-device and the bias n-device in a complementary
mode.
28. The system of claim 26 wherein the p-control signal and the
n-control signal controls the bias p-device and the bias n-device,
respectively, in a complementary mode.
29. The system of claim 24 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
30. The system of claim 26 wherein a change in the p-current
corresponds to an opposite change in the n-current such that the
duty cycle of the output signal remains substantially constant.
Description
BACKGROUND
[0001] 1. Field of the Invention
[0002] This invention relates to clock generation. In particular,
the invention relates to the control of duty cycle of the clock
signal.
[0003] 2. Description of Related Art
[0004] Clock signals are basic elements in digital circuits. A
clock signal may be used to trigger flip-flops, serve as a timing
reference, provide data and address strobing, and perform many
other timing and control functions. Since a clock signal may be
connected to a number of circuit elements, it is usually buffered
to increase the driving capability.
[0005] A clock signal may be generated by a number of methods
including use of a phase-lock loop (PLL). It is desirable that the
duty cycle of the clock signal to be approximately 50%. To
distribute the clock signal to various circuit elements, a clock
distribution circuit is used. The clock distribution circuit
usually uses inverters or buffers. Variations in the P and N
devices of the distribution inverters or clock skew due to buffers
tend to distort the duty cycle.
[0006] Existing techniques to maintain a balanced duty cycle of 50%
include using manual control of current sources. These techniques
have a number of drawbacks. First, as processes scale down and
supply voltage decreases, the headroom used by the series current
sources significantly decreases the range of control. Second, there
is non-linearity at the ends of the control range.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The features and advantages of the present invention will
become apparent from the following detailed description of the
present invention in which:
[0008] FIG. 1 is a diagram illustrating a system in which one
embodiment of the invention can be practiced.
[0009] FIG. 2A is a diagram illustrating a controlled duty cycle
circuit shown in FIG. 1 using a common duty cycle controller
according to one embodiment of the invention.
[0010] FIG. 2B is a diagram illustrating a controlled duty cycle
circuit shown in FIG. 1 using separate duty cycle controllers
according to one embodiment of the invention.
[0011] FIG. 3 is a timing diagram illustrating control of duty
cycle using rise and fall currents according to one embodiment of
the invention.
[0012] FIG. 4 is a diagram illustrating relationship between duty
cycle and bias voltage according to one embodiment of the
invention.
DESCRIPTION
[0013] In the following description, for purposes of explanation,
numerous details are set forth in order to provide a thorough
understanding of the present invention. However, it will be
apparent to one skilled in the art that these specific details are
not required in order to practice the present invention. In other
instances, well-known electrical structures and circuits are shown
in block diagram form in order not to obscure the present
invention.
[0014] FIG. 1 is a diagram illustrating a system 100 in which one
embodiment of the invention can be practiced. The system 100
includes a clock signal generator 110 and a controlled duty cycle
circuit 120.
[0015] The clock signal generator 110 may be any circuit that
generates a signal having a duty cycle that is controlled by the
circuit 120. Examples of the clock signal generator 110 include
phase locked loop circuit, delayed locked loop circuit, etc. The
clock signal generator 110 generates a clock signal 101 which may
be a clock signal having high and low periods. The clock signal 101
has a frequency and a duty cycle. The duty cycle is defined as the
ratio between the high period over the entire period of the signal.
The duty cycle of the clock signal 101 may range from 10% to 90%
although 40% to 60% is typical. It is desired to have an
approximately 50% (e.g., 45% to 55%) duty cycle so that operations
using the clock signal 101 can be reliably performed.
[0016] The controlled duty cycle circuit 120 distributes the clock
signal 101 to other circuits. The circuit 120 receives the clock
signal 101 and generates an output signal 102. The circuit 120
helps increase the driving capability of the clock signal 101 and
also maintains an approximately 50% duty cycle. By selecting proper
components, the circuit 120 may maintain any desired duty cycle and
is not limited to 50%. The circuit 120 regulates the duty cycle of
the output signal 102 using a feedback mechanism.
[0017] The controlled duty cycle circuit 120 includes a output
circuit 130 and a duty cycle control circuit 140. The output
circuit 130 receives the clock signal 101 and generate the output
signal 102 according to a current control signal 103 from the duty
cycle control circuit 140. The duty cycle control circuit 140
receives the output signal 102 in a feedback path and generates the
current control signal 103 based on the output signal 102.
[0018] FIG. 2A is a diagram illustrating the controlled duty cycle
circuit 120 shown in FIG. 1 using a common duty cycle controller
according to one embodiment of the invention. The circuit 120
includes the output circuit 130 and the duty cycle control circuit
140 as shown in FIG. 1.
[0019] The output circuit 130 includes an output device or inverter
210 and a bias current source 220. The output device 210 operates
as an inverter which inverts the clock signal 101 to generate the
output signal 102. The inverter 210 may be a buffer. The inverter
210 includes an output p-device 212 and an output n-device 216
operating as an inverter as is known by one skilled in the art. The
bias current source 220 provides a bias current to the inverter 210
using the current control signal 103 from the duty cycle control
circuit 140. The bias current source 220 adjusts the duty cycle of
the output signal 102. The bias current source 220 includes a bias
p-device 222 and a bias n-device 226. The bias p-device 222 is
coupled to the output p-device 212 to adjust a p-current according
to the current control signal 103. The bias n-device 226 is coupled
to the output n-device 216 to adjust an n-current according to the
current control signal 103. The p-current and the n-current form
the bias current. In the embodiment shown in FIG. 2A, the current
control signal 103 from the duty cycle control circuit 140 is
connected to the gates of the bias p-device 222 and the bias
n-device 226 such that the current control signal 103 controls the
bias p-device 222 and the bias n-device 226, respectively, in a
complementary mode.
[0020] The duty cycle control circuit 140 includes a direct current
(DC) level extractor 230 and an error integrator 240. The DC level
extractor 230 filters the output signal 102 to eliminate high
frequency components and to retain the DC component. In one
embodiment, the DC level extractor 230 operates as a low pass
filter. The DC level extractor 230 essentially extracts a DC level
representative of the duty cycle of the output signal 102. The DC
level extractor 230 includes a resistor 232 and a capacitor 236. As
is known by one skilled in the art, any other configuration of the
DC level extractor 230 may be used. The error integrator 240
integrates the extracted signal to provide the current control
signal 103. The error integrator 240 includes an amplifier
operating as an integrator.
[0021] The control of the duty cycle is performed automatically
without manual adjustment. When the duty cycle of the output signal
102 deviates from the desired duty cycle, the duty cycle control
circuit 140 automatically senses the deviation and generates an
appropriate amount of current control signal 103 to counter act the
increase or decrease of the generated duty cycle. For example, if
the high period of the clock signal 101 is longer than the low
period, then the duty cycle control circuit 140 generates the
current control signal 103 such that the bias currents adjust the
inverter 210 to reduce the high period and increase the low period.
Since the duty cycle control circuit 140 senses the output signal
102 directly in a feedback path, any deviation from the desired
duty cycle will be automatically adjusted and corrected
appropriately.
[0022] FIG. 2B is a diagram illustrating a controlled duty cycle
circuit 120 shown in FIG. 1 using separate duty cycle controllers
according to one embodiment of the invention. The embodiment shown
in FIG. 2B is essentially the same as the embodiment shown in FIG.
2A except that two separate duty control circuits are used to
control the bias devices separately.
[0023] The circuit 120 includes duty cycle control circuits 140A
and 140B. The duty cycle control circuits 140A and 140B control the
bias p-device 222 and 226, respectively, in the output circuit 130.
By selecting the components of the duty cycle control circuits 140A
and 140B appropriately, the bias currents may be generated to
maintain a desired duty cycle of the output signal 102.
[0024] FIG. 3 is a timing diagram illustrating control of duty
cycle using rise and fall currents according to one embodiment of
the invention. The timing diagram illustrates the adjustment of the
output signal 102 to achieve a desired duty cycle.
[0025] The timing diagram shows four episodes: a high duty cycle
episode, a balanced episode, a low duty cycle episode, and a
balanced mode episode. In the high duty cycle episode, the output
signal 102 has longer high interval then low interval. The feedback
mechanism provided by the duty cycle control circuit 140 (FIGS. 2A
and 2B) generates the current control signal 103 such that the bias
p-current is reduced while the bias n-current is increased. The
effect of this complementary operation reduces the high interval
while increasing the low interval with approximately equal amount
to achieve an approximately 50% duty cycle, or when separate duty
cycle control circuits are used, the high and low intervals will be
adjusted accordingly to achieve the desired duty cycle. Eventually,
when the desired duty cycle is achieved, the current control signal
103 is at a stable level without further change and the output
signal 102 is in the balanced episode. Similarly, in the low duty
cycle episode, the output signal 102 has shorter high interval then
low interval. The feedback mechanism provided by the duty cycle
control circuit 140 (FIGS. 2A and 2B) generates the current control
signal 103 such that the bias p-current is increased while the bias
n-current is reduced. The effect of this complementary operation
increases the high interval while decreasing the low interval with
approximately equal amount to achieve an approximately 50% duty
cycle, or when separate duty cycle control circuits are used, the
high and low intervals will be adjusted accordingly to achieve the
desired duty cycle. Eventually, when the desired duty cycle is
achieved, the current control signal 103 is at a stable level
without further change and the output signal 102 is in the balanced
episode.
[0026] FIG. 4 is a diagram illustrating the relationship between
duty cycle and bias voltage according to one embodiment of the
invention.
[0027] The diagram shows the variation of the duty cycle of the
output signal 102 as a function of the bias voltage relative to the
supply voltage. The relative bias voltage is representative of the
bias current as discussed above. As the relative bias voltage
changes from -0.6V to +0.6V, the duty cycle is reduced from 51.75%
to 49.5%. When the relative bias voltage is near zero volt, the
duty cycle reaches approximately 50.5%.
[0028] While this invention has been described with reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications of the
illustrative embodiments, as well as other embodiments of the
invention, which are apparent to persons skilled in the art to
which the invention pertains are deemed to lie within the spirit
and scope of the invention.
* * * * *