U.S. patent application number 09/736803 was filed with the patent office on 2002-06-20 for apparatus for detecting the width of a v-groove formed in a semiconductor wafer.
This patent application is currently assigned to Xerox Corporation. Invention is credited to Browne, Paul W., Hosier, Paul A., TeWinkle, Scott L..
Application Number | 20020074545 09/736803 |
Document ID | / |
Family ID | 24961357 |
Filed Date | 2002-06-20 |
United States Patent
Application |
20020074545 |
Kind Code |
A1 |
Hosier, Paul A. ; et
al. |
June 20, 2002 |
APPARATUS FOR DETECTING THE WIDTH OF A V-GROOVE FORMED IN A
SEMICONDUCTOR WAFER
Abstract
The present invention generally relates to electrical detection
of V-groove width during the fabrication of photosensitive chips,
which create electrical signals from an original image, as would be
found, for example, in a digital scanner or facsimile machine.
Inventors: |
Hosier, Paul A.; (Rochester,
NY) ; Browne, Paul W.; (Canandaigua, NY) ;
TeWinkle, Scott L.; (Ontario, NY) |
Correspondence
Address: |
John E.Beck
Xerox Corporation
Xerox Square 20A
Rochester
NY
14644
US
|
Assignee: |
Xerox Corporation
|
Family ID: |
24961357 |
Appl. No.: |
09/736803 |
Filed: |
December 14, 2000 |
Current U.S.
Class: |
257/48 ; 257/379;
257/380; 257/536; 257/537; 257/538; 257/E21.53 |
Current CPC
Class: |
H01L 22/12 20130101;
H01L 22/34 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/48 ; 257/379;
257/380; 257/536; 257/537; 257/538 |
International
Class: |
H01L 023/58; H01L
029/76; H01L 029/94; H01L 031/062; H01L 031/113; H01L 031/119 |
Claims
1. A V-groove width monitor resistor comprising a diffusion layer
etched on a silicon wafer and overlapping at least one chip area
and area upon which the V-groove is to etched.
2. The V-groove width monitor resistor as in claim 1, wherein the
diffusion layer overlaps two chip areas and the area upon which the
V-groove is to etched.
3. The V-groove width monitor resistor as in claim 1, wherein the
diffusion layer overlaps two chip areas and is continuously etched
in the area upon which the V-groove is to etched.
4. The V-groove width monitor resistor as in claim 1, wherein the
diffusion layer is one of n-type or p-type.
5. An apparatus for detecting width of a V-groove on a
semiconductor wafer, comprising: a V-groove width monitor resistor
overlapping a chip area and an area upon which the V-groove is to
be etched; a pad etched on the silicon wafer and coupled to the
V-groove width monitor resistor; and a tester supplying voltage to
the pad after the V-groove has been etched into the silicon wafer;
and means, coupled to the pad, for determining the width of the
etched V-groove.
6. The apparatus as in claim 5, wherein the pad is an input/output
pad.
7. The apparatus as in claim 5, wherein the pad is a separate test
pad for testing V-groove width only.
8. The apparatus as in claim 5, further comprising a pull up
resistance connected to the V-groove width monitor resistor and the
pad.
9. A method for determining the width of a V-groove on a silicon
wafer before dicing, comprising: defining a V-groove region on the
silicon wafer; applying a diffusion layer within a test area on the
silicon wafer to form a V-groove width monitor resistor; connecting
the diffusion layer to a pad through metal layers and nodes;
etching a V-groove in the silicon wafer in the V-groove region;
applying one of a test voltage or test current to the diffusion
layer; calculating the resistance of the diffusion layer after
etching the V-groove in the silicon wafer; and calculating the
width of the diffusion layer and the width of the etched V-groove
based on the calculated resistance.
Description
FIELD OF THE INVENTION
[0001] The present invention generally relates to electrical
detection of V-groove width during the fabrication of
photosensitive chips, which create electrical signals from an
original image, as would be found, for example, in a digital
scanner or facsimile machine.
BACKGROUND OF THE INVENTION
[0002] In the context of document processing, a raster input
scanner, or simply "scanner," is a device by which an image on a
hardcopy original, such as a sheet of paper, is converted to
digital data. A common design for a scanner includes a linear array
of photosites with corresponding circuitry to form a linear array
of photosensors. Each photosensor in the array is adapted to output
a signal, typically in the form of an electrical charge or voltage,
of a magnitude proportional to or otherwise related to the
intensity of light incident on the photosensor. By providing a
linear array of these photosensors and causing the array to scan
relative to the hard-copy original, each photosensor will output a
sequence of charge signals resulting from the various gradations of
dark and light in the image as the individual photosensors move
through a path relative to an image.
[0003] In most low cost scanners, such as presently found in
inexpensive facsimile machines, the most typical technology for
creating such a scanner is the charge-coupled device, or CCD. For
higher-quality applications, CMOS technology in one or more
photosensor chips are used.
[0004] The number of photosites (and therefore photosensors) that
can be packed onto a single chip or wafer is limited, and this, in
turn, limits the image resolution that can be achieved with a
single photosensitive array. Joining several of the smaller
photosensor arrays together to form a longer array, and
particularly, to form a full page width array with increased
resolution along with the attendant simplification of the scanning
system that this allows is desirable.
[0005] Arrays of photosites are typically formed from a plurality
of generally rectangular substrates and these substrates are
separated by dicing or other suitable means from one or more
circular silicon wafers to form photosensitive chips. (The shape of
substrates do not have to be rectangular. Other geometric shapes
are also possible). The photosensitive chips are preferably
assembled end to end in a collinear fashion to improve image
quality and to form a full width array.
[0006] One method presently employed to produce photosensitive
chips is the formation of aligned V-grooves in the semiconductor
wafer. The V-grooves are preferably etched along the 111 plane of
the silicon, which is the easy slip plane for stress relief or
cracks. V-grooves are needed for proper dicing of the chips in
regions very close to active circuits. If the proper V-groove width
is not there for each chip during dicing, chipping damage may occur
and this will cause yield problems or a reliability degradation
problem in the final photosensor array. Only 100% visual inspection
of all wafers catches all of these defects, or a 100% visual
inspection of a sample of wafers might indicate that there is a
problem. Visual inspection of every chip on every wafer is labor
intensive and prone to human error. Therefore, there is a need for
a new method and apparatus to inspect and evaluate V-groove widths
on the semiconductor wafer.
SUMMARY OF THE INVENTION
[0007] The present invention provides a V-groove width monitor
resistor including a diffusion layer etched on a silicon wafer and
overlapping at least one chip area and area upon which the V-groove
is to etched. The diffusion layer may overlap one or two chip areas
and the area upon which the V-groove is to etched.
[0008] Alternatively, the diffusion layer overlaps two chip areas
and is continuously etched in the area upon which the V-groove is
to etched. The diffusion layer may be one of n-type or p-type.
[0009] The present invention provides an apparatus for detecting
width of a V-groove on a semiconductor wafer including a V-groove
width monitor resistor overlapping a chip area and an area upon
which the V-groove is to be etched; an pad etched on the silicon
wafer and coupled to the V-groove width monitor resistor; and a
tester supplying voltage to the pad after the V-groove has been
etched into the silicon wafer; and apparatus to determine the width
of the etched V-groove. The pad can be an input/output pad. The pad
can be a separate test pad for testing V-groove width only. A pull
up resistance may be connected to the pad and V-groove width
monitor resistor.
[0010] The present invention provides a method for determining the
width of a V-groove on a silicon wafer before dicing, comprising:
defining a V-groove region on the silicon wafer; applying a
diffusion layer within a test area on the silicon wafer to form a
V-groove width monitor resistor; connecting the diffusion layer to
a pad through metal layers and nodes; etching a V-groove in the
silicon wafer in the V-groove region; applying one of a test
voltage or test current to the diffusion layer; calculating the
resistance of the diffusion layer after etching the V-groove in the
silicon wafer; and calculating the width of the diffusion layer and
the width of the etched V-groove based on the calculated
resistance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a simplified perspective view showing a base
substrate having a plurality of semiconductor chips assembled and
mounted end to end on the base substrate;
[0012] FIG. 2 is a detailed partial plan view of two representative
semiconductor chips on a semiconductor wafer relevant to the
present invention before dicing;
[0013] FIG. 3 is a simplified perspective view of a semiconductor
wafer;
[0014] FIG. 4 is a plan view of a prior art V-groove structure on a
silicon wafer;
[0015] FIG. 5 is a plan view of a V-groove structure on a silicon
wafer in accordance with a first embodiment of the present
invention;
[0016] FIG. 6 is a plan view of a V-groove structure on a silicon
wafer in accordance with a second embodiment of the present
invention;
[0017] FIG. 7 is a plan view of a V-groove structure on a silicon
wafer in accordance with a third embodiment of the present
invention;
[0018] FIG. 8 is an electrical schematic in accordance with the
first through third embodiments of the present invention;
[0019] FIG. 9 is an electrical schematic in accordance with the
first through third embodiments of the present invention;
[0020] FIG. 10 is an electrical schematic in accordance with the
first through third embodiments of the present invention;
[0021] FIG. 11 is a plan view of a V-groove structure on a silicon
wafer in accordance with a fourth embodiment of the present
invention;
[0022] FIG. 12 is a plan view of a V-groove structure on a silicon
wafer in accordance with a fifth embodiment of the present
invention;
[0023] FIG. 13 is an electrical schematic in accordance with the
fourth and fifth embodiments of the present invention; and
[0024] FIG. 14 is an electrical schematic in accordance with the
fourth and fifth embodiments of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] While the present invention will hereinafter be described in
connection with a preferred embodiment thereof, it will be
understood that it is not intended to limit the invention to that
embodiment. On the contrary, it is intended to encompass all
alternatives, modifications and equivalents as may be included
within the spirit and scope of the invention as defined in the
appended claims.
[0026] FIG. 1 shows a full width array image sensor 21 including a
plurality of photosensitive chips 10 mounted end-to-end on a
substrate 20 to form an effective collinear array of photosites,
which extends across a page image being scanned for a scanner,
copier, facsimile machine or other document reading device.
Generally, each individual photosite is adapted to output a charge
or voltage signal indicative of the intensity of light of a certain
type impinging thereon. Various structures, such as transfer
circuits, or charged coupled devices, are known in the art for
processing signal output by the various photosites.
[0027] FIG. 2 is a plan view showing part of two of these
photosensitive chips relevant to the claimed invention. The
photosensitive chip 10 is generally made of a semiconductor
substrate, as is known in the art, in which circuitry and other
elements are formed, such as by photolithographic etching. A few of
the most relevant structures are one or more linear arrays of
photosites 12, each of which forms the photosensitive surface of
circuitry within the photosensitive chip 10, and a set of bonding
pads 14. The photosites 12 are typically arranged in a linear array
along one main dimension of the photosensitive chip 10, with each
photosite 12 along the array corresponding to one pixel in an image
signal. The photosites 12 are preferably for sensing the three
primary colors, blue, green and red. However, the photosites 12
sensing blue, green and red could be replaced with photosites
sensing yellow, magenta and cyan, for example. Any other suitable
combination of color sensitive photosites may also be used. Each
photosite is associated with a corresponding photosensor.
Preferably, there are three parallel linear arrays 16a, 16b, and
16c for the three primary colors. However, any number of multiple
parallel linear arrays may be provided on each photosensitive chip
10.
[0028] The bonding pads 14 are distinct surfaces on the main
surface of the photosensitive chip 10, and are intended to accept
wire bonds attached thereto. The bonding pads 14 thus serve as the
electronic interface between the photosensitive chip 10 and any
external circuitry. The active circuitry for obtaining signals
related to light directed to the photosites 12, and for unloading
image data from the photosensitive chip 10 is generally indicated
as 15. The active circuitry 15 is generally deposited between a
linear array of photosites 12 and a linear array of bonding pads
14.
[0029] Photosensitive chips 10 are typically formed in batches on
semiconductor wafers 11, which are subsequently cleaved, or
"diced," to create individual photosensitive chips. Typically, the
semiconductor wafers are made of silicon. Photolithographically
etched V-grooves 17 define precisely the intended boundaries of a
particular photosensitive chip 10 for dicing as shown in the
partial perspective view of two adjacent photosensitive chips 10 in
FIG. 2. (Alternatively, U-grooves or trenches may be used to define
the intended boundaries in the same location as V-grooves 17.)
Thus, all of the photosites 12, bonding pads 14 and circuitry 15
for relatively large number of photosensitive chips 10 are etched
onto a single semiconductor wafer. The region between the V-grooves
17 is called the tab region, or vertical scribe line (industry term
is scribe line). A region in which a V-groove is to be etched is
called a V-groove region. A guardring 18 parallel to the V-grooves
17 is formed on each chip as taught for example in U.S. Pat. No.
6,066,883. Reference numeral 40 denotes the area on the
semiconductor wafer 11, where the circuit for the electrical
detection of V-groove width is formed.
[0030] FIG. 3 shows a typical semiconductor wafer 11, in isolation,
wherein a relatively large number of photosensitive chips 10 are
created in the wafer 11 prior to dicing thereof. Each
photosensitive chip 10 has a distinct photosensitive chip area
within the main surface of the wafer 11. The phrase "chip area"
refers to a defined area within the main surface of the wafer 11
which is intended to comprise a discrete photosensitive chip 10
after the dicing step, when individual photosensitive chips 10 are
separated from the rest of the wafer 11.
[0031] As discussed above, the width of the V-groove must be known
and controlled, such that it is wide enough for optimum dicing and
also narrow enough that it does not interfere with circuitry near
the edge of the chips 10. This invention allows the nondestructive
measurement of the width of every V-groove 17 on every chip. (It is
preferable but not necessary to measure every V-groove 17 on every
chip on the silicon wafer 11). Generally, an implanted or diffused
region overlaps V-groove 17, with electrical connections on both
ends of the diffusion. Depending on its width, the V-groove 17 will
cut away some, or all, of the diffused region changing the
resistance of the electrical path between nodes. One end of the
electrical path can be tied to an existing bonding pad 14 on the
chip 10 and the other end to ground, if the decreased input
resistance can be tolerated. Alternatively, a new test pad can be
added just for the purpose of ascertaining the width of the
V-groove. Further, a more complex circuit can be used to generate a
pass/fail condition that can be used to alter an existing DC test
measurement. Alternately, other complex DC test schemes can be used
on existing bonding pads 14. Thus, using existing, or slightly
modified circuit elements, DC tests can be used to check the
V-groove widths 17, with or without the addition of any test
pads.
[0032] FIG. 4 shows a partial plan view of a prior art V-groove
structure on a silicon wafer in area 40. The center of the V-groove
(V-groove center) is denoted by reference numeral 50. The width of
the V-groove (V-groove width) is denoted by reference numeral 55.
The guardrings, which are preferably n-doped silicon, are denoted
by reference numeral 18. The silicon substrate is denoted by
reference numeral 60. In the prior art, there is no circuit to
detect the V-groove width 55 in area 40 as shown in FIG. 4.
[0033] FIGS. 5-7 show the first three embodiments of circuits used
to electrically detect the width of the V-groove 17. These
embodiments are preferably located in area 40 in FIG. 2. (Please
note that area 40 is not drawn to scale.) The nodes in the circuits
are electrically connected through metal connectors 61. In all of
the embodiments, the width of the V-grooves 17 etched on the
silicon wafer 11 must be determined to ensure that the V-groove
width 55 is within a specific range of V-groove widths. If the
V-groove width 55 is too large, then the V-groove 17 will break the
guardring 18, which effects end photosite performance. If the
V-groove width 55 is even larger, the large width will encroach
upon circuitry and cause a functional failure of the chip 10.
However, if the V-groove width 55 is too small, then the saw for
dicing the silicon wafer 11 may dice outside the V-groove 17
because the V-groove 17 does not fall within the saw tolerances.
This causes cracks in the silicon causing failure of the chips
10.
[0034] In the first embodiment shown in FIG. 5, a V-groove width
monitor resistor 58 is placed in parallel with and overlapping the
area upon which V-groove 17 is to be etched on the silicon wafer
11. The resistor 58 preferably comprises a diffusion layer on the
silicon 60, which overlaps both the minimum and maximum edges of
the V-groove 17 to be etched on the silicon wafer 11. The width of
the diffusion layer (resistor 58) prior to etching the V-groove 17
is equal to the sum of the overlap width 56 and the resistor width
59 after the V-groove 17 is etched into the semiconductor wafer 11
(resistor width 59). The overlap of the resistor 58 in the width
direction (overlap width 56) are such, that for any expected
variation in the V-groove width 55, the resistor width 59 is
determined by the edge of the etched V-groove 17. Further, the
length of the resistor 58 is determined by the distance between
node 1 and node 2 as denoted by reference numeral 57 in FIG. 5. The
resistance of the resistor 58 is (L/W)(.rho..sub.0), where
.rho..sub.0 is resistor sheet rho in ohms/square, and L and W are
the dimensions (length and width) of the resistor 58. Since W of
the resistor is directly proportional to the negative of V-groove
width 55, the resistance will be a linear indicator of the V-groove
width 55.
[0035] Also, in the first embodiment, the guardring 18 may extend
into area 40 as shown or may be eliminated from area 40. A metal
layer 61 connected to resistor 58 through node 1 and node 2
provides an electrical connection between the contacts of resistor
58 and a test pad, ground, or other circuitry as shown in FIGS.
8-10. By measuring the resistance after the V-groove 17 has been
etched, the resistor width 59 is ascertained using the above
formula as will be discussed further with reference to FIGS. 8-10.
Subsequently, the resistor width 59 is compared to the range of
resistor widths acceptable for dicing. If the resistor width 59 is
within the range (tolerance), then the chips 10 adjacent to the
V-groove 17 should not fail or have reduced performance after
dicing.
[0036] The second embodiment of the present invention as shown in
FIG. 6 not only detects whether a resistor width 59 is within a
certain tolerance for dicing (dicing tolerance) but the second
embodiment detects also an alignment variation between the resistor
mask (in this case N+, or active area) and the V-groove mask. This
alignment variation will cause the resistor width to vary with a
component that is independent of the V-groove width 55. The second
embodiment of the present invention eliminates this undesirable
random variation. This embodiment has a two resistors 58 which can
be tied together in parallel, with a resulting resistance of
U(W1+W2)(.rho..sub.0), to form one V-groove width monitor resistor.
Reference numeral 62 denotes width W2 and reference numeral 64
denotes a width overlapping the V-groove 17. (Please note that the
two resistors 58 may have different widths and different
resistances. However, they result in one resistance for the
purposes of the present invention.) No matter what the alignment of
the V-groove to resistor mask, the resultant sum of W1+W2 (denoted
by reference numerals 59 and 62) will be a linear indicator of the
V-groove width, which is compared to the range of resistor widths
acceptable for dicing.
[0037] There is still a small independent component of variation of
W1+W2 due to the image variation of the resistor mask. However, in
practice, this variation is much smaller than the V-groove
variation and therefore is tolerable. In addition, the V-groove
width monitor resistor can be used in a circuit with a similar
resistor to null out most of this effect, as shown in FIG. 9. If
resistor 130 in FIG. 9 is similar to resistors 58, the voltage
division between resistor 130 and resistor 58 will be largely
independent of image variation. Specifically, resistor 130 should
be made with the same N+resistor mask, the same L and a W=W1+W2,
for W1 and W2 corresponding to a nominal size V-groove. If W1+W2 is
made to nominally be four times the expected V-groove variation,
the small image error will be reduced by a factor of four
times.
[0038] FIG. 7 shows the third embodiment of the present invention.
Electrically, this configuration is exactly the same as the second
embodiment when a V-groove 17 is present. However, if a V-groove 17
is malformed or missing, the resistance in FIG. 7 will register a
very low resistance since the width will now be
W1+W2+W.sub.V-groove. This lower resistance can be used to flag a
missing V-groove 17. In addition, another advantage of the FIG. 7
configuration is a continuous resistor active region across the
V-groove 17, which assists ensuring uniform V-groove
processing.
[0039] FIGS. 8-10 show electrical schematics for testing resistance
after the V-groove 17 has been etched onto the silicon wafer 11 for
the first three embodiments of the present invention. In FIG. 8,
Node 1 connects the test circuit to the added V-groove width
monitor resistor 58, which is connected to a reference voltage or
ground by node 2 as denoted by reference numeral 100. By adding a
test pad 90 (input/output pad) to the silicon wafer 11, the current
through the resistor can be measured by applying a known test
voltage (tester 110), and using an ammeter in series with the test
voltage source. Alternatively, a current source could be applied to
the resistor and the voltage across it could be measured by a
voltmeter. Since the current and voltage are known, the resistance
can be calculated. Based on the resistance value and length of the
resistor, the width of the resistor can be ascertained. Therefore,
the V-groove width can be determined.
[0040] In FIG. 9, Node 1 connects the test circuit to the added
V-groove width monitor resistor 58, which is connected to a
reference voltage or ground by node 2 as denoted by reference
numeral 100. By adding a test pad 90 (input/output pad) and pull up
resistor 130 to the silicon wafer 11, the voltage (measured by
voltmeter 140) across the resistor 58 can be measured by applying a
known voltage VDD (e.g. 5 volts) and measuring the voltage across
the resistor 58 using a voltmeter 140 or other voltage measuring
device. The resistor 58 can just be tied to the chip power supply
or a test pad. Since the VDD voltage, pull up resistance and the
divider voltage, V.sub.M are known, the resistance value of
resistor 58 can be calculated. Since voltage division results in
V.sub.M=R58/(R58+R130), then
R58=V.sub.M.times.R130/(1-V.sub.M/VDD). R58 is the resistance of
resistor 58, and R130 is the resistance of resistor 130. V.sub.M is
the voltage measured by the voltmeter 140. Based on the resistance
value and length of the resistor, the width of the resistor can be
ascertained. Therefore, the V-groove width can be determined.
[0041] In FIG. 10, Node 1 connects the test circuit to the added
V-groove width monitor resistor 58, which is connected to a
reference voltage or ground by node 2 as denoted by reference
numeral 100. The advantage of this embodiment is that an additional
test pad (input/output pad) does not need to be added to the chip
10 on the silicon wafer 11. Instead, one of the existing bonding
pads 14 may be used. Since the test voltage, VT applied by tester
110 which also measures input current I.sub.IN (with ammeter) and
the resistance of resistor 150 are known, the resistance value of
resistor 58 can be calculated. Based on the resistance value and
length of the resistor, the width of the resistor can be
ascertained. Therefore, the V-groove width can be determined.
Please note that input circuit 170 acts as a buffer between the
active circuitry 15 on chip 10 and test circuit 155, tester 110,
and added V-groove width monitor resistor circuit 100.
[0042] FIGS. 11 and 12 show the fourth and fifth embodiments. In
one alternative embodiment, the gaurdring 18 may be eliminated. In
both the fourth and fifth embodiments, the resistance layout on the
left may be duplicated or mirrored on the right to eliminate the
alignment effects as discussed with reference to the third and
fourth embodiments. The principle of detection is the same. The
resistor width of each of the resistor sections will be determined
by the width of the V-groove 17. The major difference with these
embodiments is that the resistors could be used in a "digital"
manner. Depending on the width of the V-groove 17, a certain number
of the resistor legs will be cut off, or open circuited. For
example, in FIG. 11, resistor 200 is not affected. Resistor 210
looses some width because part of the resistance is etched away by
the V-groove 17. However, this circuit does remain connected (not
open circuited). Resistor 220 is completely cut off by the etched
V-groove 17, and this creates an open circuit. Based upon the
measured resistance value, the width of the V-groove 17 can be
ascertained. A similar result is shown in FIG. 12 with respect to
resistor 270. Therefore, if each of these resistors (fourth or
fifth embodiments) is connected to the appropriate circuitry as
shown in FIGS. 13-14 for example, the number of open circuits can
be determined and this number will be proportional to the width of
the V-groove 17.
[0043] FIGS. 13-14 show electrical schematics for testing
resistance after the V-groove 17 has been etched onto the silicon
wafer 11 for the fourth and fifth embodiments of the present
invention. In FIG. 13, Node A.sub.N connects the test circuit to
the added V-groove width monitor resistor(s) 58, which are
connected to a reference voltage or ground by node B.sub.N as
denoted by reference numeral 300. By adding a test pad 90
(input/output pad) and pull up resistor 130 to the silicon wafer
11, the voltage 140 across a resistor 350 can be measured by
applying a known voltage VDD and measuring the voltage across the
resistor 350 using a voltmeter 140 or other voltage measuring
device. Applying the test circuit in FIG. 13 to the fourth
embodiment, the resistor 350 denotes the resistance provided by
resistors 200, 210, and 220 after etching the semiconductor wafer
11 in accordance with the fourth embodiment. Applying the test
circuit in FIG. 13 to the fifth embodiment, the resistor 350
denotes the resistance of resistor 270 after etching the
semiconductor wafer 11 in accordance with the fifth embodiment.
Since the VDD voltage, pull up resistance and V.sub.M are known in
either the fourth or fifth embodiment, the resistance value of
resistor 350 can be calculated. Since voltage division results in
V.sub.M=R350/(R350+R130), then
R58=V.sub.M.times.R130/(1-V.sub.M/VDD). Based on the resistance
value and length of the resistor, the width of the resistor can be
ascertained. Therefore, the V-groove width can be determined.
[0044] If R130 of FIGS. 13 and 14 is picked such that
R130>>R350, the resistor divider circuits will provide a
digital output, which indicates whether the resistor portion is
completely etch away by V-groove or partially there. If R58 is
open, or etch away, V.sub.M="1", or be at the VDD level. If any of
R58 is still present, V.sub.M="0" or be close to ground and
certainly below the logic threshold of VDD/2. This provides us with
a digital result.
[0045] In FIG. 14, Nodes A.sub.1, A.sub.2, . . . A.sub.N connects
the test circuits 300.sub.1, 300.sub.2 . . . 300.sub.N to the added
V-groove width monitor resistors 350.sub.1, 350.sub.2 . . .
350.sub.N, which is connected to a reference voltage or ground by
node B.sub.1, B.sub.2, . . . B.sub.N as denoted by reference
numeral 300. The advantage of this embodiment is that an additional
test pad (input/output pad) does not need to be added to the chip
10 on the silicon wafer 11. Instead, one of the existing bonding
pads 14 may be used.
[0046] The digital outputs, "0" or "1", on nodes A.sub.1-A.sub.N
are processed to produce a digital output or an analog output
representing the width of the V-groove 17. For example if nodes
Al-AN are added by digital adder or processor 305, the sum will be
proportional to the width of the V-groove. This digital sum could
be converted back to an analog level through a digital to analog
converter 310, and multiplexed out to a new or existing pad using a
transfer switch 315 for example. Input circuit 170 acts as a buffer
between the active circuitry 15 and the test circuitry. Those
skilled in the art of digital circuit design know how to add and
process digital outputs.
[0047] While the invention has been described in detail with
reference to specific and preferred embodiments involving the
V-groove, it will be appreciated that various modifications and
variations will be apparent to the artisan including the use of
this width detection technique with trench, U-groove, or
microelectromechanical systems (MEMS). All such modifications and
embodiments as may occur to one skilled in the art are intended to
be within the scope of the appended claims.
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