U.S. patent application number 09/729751 was filed with the patent office on 2002-06-06 for image sensor utilizing a low fpn high gain capacitive transimpedance amplifier.
Invention is credited to Fowler, Boyd.
Application Number | 20020066848 09/729751 |
Document ID | / |
Family ID | 24932454 |
Filed Date | 2002-06-06 |
United States Patent
Application |
20020066848 |
Kind Code |
A1 |
Fowler, Boyd |
June 6, 2002 |
Image sensor utilizing a low FPN high gain capacitive
transimpedance amplifier
Abstract
An imaging element and an imaging array constructed from such
elements. The preferred imaging element is constructed from a
photodiode having a parasitic capacitance C.sub.pd; and an
amplifier for measuring the charge stored on the parasitic
capacitor. The amplifier includes an opamp having a signal input,
reference input and output; the first terminal of the parasitic
capacitor is connected to the signal input. The imaging element
includes a reset switch for shorting the signal input and the
output of the opamp, and capacitive network. The capacitive network
connects the signal input and the output of the opamp, and provides
a capacitance of C.sub.T between the signal input and the output of
the opamp wherein C.sub.T<C.sub.Pd. The capacitive network is
constructed from a plurality of component capacitors. Preferably
each component capacitor has a capacitance greater than or equal to
C.sub.pd. An imaging array according to the invention includes a
plurality of imaging elements, a signal bus, a reset bus, and a
reset circuit. Each imaging element also includes a coupling switch
for connecting the output of the opamp to the signal bus and a
reset coupling switch for connecting the photodiode to the reset
bus via a low-pass filter. The reset circuit includes a second
opamp having a signal input, a reference input connected to a
second reference potential, and an output connected to the reset
bus; and a reset coupling switch for connecting the signal input of
the second opamp to the signal bus.
Inventors: |
Fowler, Boyd; (Sunnyvale,
CA) |
Correspondence
Address: |
The Law Offices of Calvin B. Ward
18 Crow Canyon Court, Suite 305
San Ramon
CA
94583
US
|
Family ID: |
24932454 |
Appl. No.: |
09/729751 |
Filed: |
December 4, 2000 |
Current U.S.
Class: |
250/208.1 ;
348/E3.021; 348/E5.079 |
Current CPC
Class: |
H04N 5/3658 20130101;
H04N 5/37452 20130101; H04N 5/361 20130101 |
Class at
Publication: |
250/208.1 |
International
Class: |
H01L 027/14 |
Claims
What is claimed is:
1. An imaging element comprising: a photodiode having a parasitic
capacitance C.sub.pd; and an amplifier for measuring the charge
stored on said parasitic capacitor, said amplifier comprising: an
opamp having a signal input, reference input and output, said first
terminal of said source capacitor being connected to said signal
input; a reset switch for shorting said signal input and said
output of said opamp; and a capacitive network connecting said
signal input and said output of said opamp, said capacitive network
providing a capacitance of C.sub.T between said signal input and
said output of said opamp wherein C.sub.T<C.sub.pd and wherein
said capacitive network is constructed from a plurality of
component capacitors.
2. The imaging element of claim 1 wherein each component capacitor
has a capacitance greater than or equal to C.sub.pd.
3. The imaging element of claim 1, wherein said capacitive network
comprises first, second, and third component capacitors, each
capacitor having first and second terminals, said first terminal of
said first capacitor being connected to said output of said opamp,
said second terminal of said first capacitor, said first terminal
of said second capacitor, and said first terminal of said third
capacitor being connected together at a first common node, said
second terminal of said third capacitor being connected to said
signal input of said opamp, and said second terminal of said second
capacitor being connected to said second terminal of said parasitic
capacitor, said capacitive network further comprising a first
network switch for connecting said first common node to said output
of said opamp.
4. The imaging element of claim 3 wherein said first capacitor
comprises a network constructed from fourth, fifth, and sixth
component capacitors, said fourth, fifth, and sixth component
capacitors being connected such that said fourth, fifth, and sixth
capacitors are connected together at a common node, said network
further comprising a second network switch for connecting said
common node to said output of said opamp.
5. An imaging array comprising first and second imaging elements, a
signal bus, a reset bus, and a reset circuit, each of said first
and second imaging elements comprising: a photodiode having a
parasitic capacitance C.sub.pd; and an amplifier for measuring the
charge stored on said parasitic capacitor, said amplifier
comprising: a first opamp having a signal input, a reference input
connected to a first reference potential, and an output, said first
terminal of said source capacitor being connected to said signal
input; a reset switch for shorting said signal input and said
output of said first opamp; a capacitive feedback path connecting
said signal input and said output of said first opamp; a first
coupling switch for connecting said signal output of said first
opamp to said signal bus; and a second coupling switch for
connecting said reset bus to said photodiode via a low-pass filter
connected between said photodiode and said second coupling switch;
said reset circuit comprising: a second opamp having a signal
input, a reference input connected to a second reference potential,
and an output connected to said reset bus; and a reset coupling
switch for connecting said signal input of said second opamp to
said signal bus.
6. The imaging array of claim 5 wherein said low-pass filters
comprise a network of capacitors.
7. The imaging array of claim 5, wherein said capacitive feedback
path comprises first, second, and third component capacitors, each
capacitor having first and second terminals, said first terminal of
said first capacitor being connected to said output of said first
opamp, said second terminal of said first capacitor, said first
terminal of said second capacitor, and said first terminal of said
third capacitor being connected together at a first common node,
said second terminal of said third capacitor being connected to
said signal input of said first opamp, and said second terminal of
said second capacitor being connected to said second terminal of
said parasitic capacitor, said capacitive feedback path further
comprising a first network switch for connecting said first common
node to said output of said first opamp.
Description
[0001] The present invention relates to CMOS imaging elements, and
more particularly, to image sensors utilizing capacitive
transimpedance.
BACKGROUND OF THE INVENTION
[0002] While imaging arrays based on CCDs have become common, these
arrays have two drawbacks. First, the technology used to fabricate
such arrays has a significantly lower yield than that used to
fabricate CMOS circuitry. CCD arrays have large areas of gate
oxide. These areas are prone to shorts. These electrical shorts, in
turn, reduce the yield of useful chips, and hence, increase the
cost of the devices.
[0003] The second problem with CCD arrays lies in the lower bound
for the noise in the sensor arrays. Many imaging problems of
interest require the imaging array to sense very low levels of
light. The minimum level that an array can sense depends on the
minimum noise in the sensors.
[0004] In principle, both of these drawbacks can be overcome by
utilizing CMOS image sensors. The CMOS yields are significantly
better than those of the CCD fabrication process. In addition, the
minimum noise levels achievable with CMOS-based sensors are
substantially lower than those that can be obtained with CCDs.
[0005] CMOS image sensing arrays have been limited, however, by so
called "fixed pattern noise" (FPN). Each image sensor in a CMOS
array typically includes an amplifier for converting the small
amount of charge stored on the parasitic capacitance of the imaging
element to a voltage or current. Consider an array of such imaging
elements. To provide a high quality image, each element must have
the same response characteristics. Consider an imaging array in
which the amplifier generates a voltage that is linearly related to
the amount of light that fell on the imaging element. Each imaging
element can be characterized by an offset and gain. That is, the
voltage, V.sub.i, generated by the i.sup.th amplifier is related to
the offset, O.sub.i, for that element and the gain, G.sub.i, by
V.sub.iO.sub.i+G.sub.iI, (1)
[0006] where I is the light incident on the i.sup.th element since
the last time the imaging element was reset. To provide a high
quality image all of the O.sub.i must be the same, i.e., O.sub.i=O,
and all of the gains, G.sub.i must be the same, i.e., G.sub.i=G.
The extent to which O.sub.i is different from O is referred to as
the offset FPN of the array, and the extent to which G.sub.i is
different from G is referred to as the gain FPN of the array. It
should be noted that these noise values are constant for any given
array. For any given pixel, G.sub.i-G does not change in time.
[0007] In addition to the offset and gain FPN, there is a third
type of noise, referred to as the temporal noise which reflects the
variation of V.sub.i from measurement to measurement. This noise is
related to the various shot, thermal, and 1/f noise sources in the
image sensor.
[0008] As CMOS sensors are pushed to ever-lower light levels, the
relative magnitude of the gain and offset FPN increases leading to
degraded images. To provide the high gain levels needed at low
light levels without introducing additional temporal noise,
capacitive transimpedance amplifiers are used. The gain of such
amplifiers depends on the ratio of the capacitance of the sensor to
that of the capacitance of the feedback loop in the amplifier.
Hence, to obtain high gain, the feedback capacitor must be much
smaller than the sensor capacitor. The variations in these
capacitors determines the gain FPN of the array. Hence, the
dimensions of the capacitors must be held to very tight tolerances
to prevent the introduction of gain FPN.
[0009] A capacitor is constructed by overlapping two metal
electrodes that are separated by a dielectric layer. For any given
fabrication process, there is a point at which the ability to
control the degree of overlap and size of the electrodes becomes a
problem. In general, one would like to have the capacitance of the
photodiode be as small as possible so that the charge sensitivity
will be as high as possible. Hence, the photodiode capacitance is
set to be just big enough to assure that the capacitance does not
vary substantially from image to image. However, if this is the
case, the feedback capacitor, which must have a small fraction of
the capacitance of the photodiode, will be too small to be reliably
constructed.
[0010] Offset FPN arises from variations in the amplifier threshold
levels. To remove offset FPN, each diode-amplifier pair must be
reset such that the output voltage of the amplifier is the same for
each such pair. In addition, the reset must be accomplished in a
manner that does not increase the temporal noise and does not
increase the size of the sensing element. Alternatively, some prior
art devices utilize schemes in which the offset FPN is recorded for
each device and the image is then corrected for that measured
offset FPN. While such schemes can remove the offset FPN, they
require complex circuitry and/or memory arrays that increase the
cost of the imaging devices.
[0011] Broadly, it is the object of the present invention to
provide an improved image sensor.
[0012] It is a further object of the present invention to provide
an image sensor that has reduced gain FPN relative to prior art
devices.
[0013] It is a still further object of the present invention to
provide an image sensor that has reduced offset FPN without
requiring a separate storage array for storing the offset
values.
[0014] It is a still further object of the present invention to
provide an image sensor that has reduced temporal reset noise.
[0015] These and other objects of the present invention will become
apparent to those skilled in the art from the following detailed
description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
[0016] The present invention is an imaging element and an imaging
array constructed from such elements. The preferred imaging element
is constructed from a photodiode having a parasitic capacitance
C.sub.pd; and an amplifier for measuring the charge stored on the
parasitic capacitor. The amplifier includes an opamp having a
signal input, reference input, and output; the first terminal of
the parasitic capacitor is connected to the signal input. The
imaging element includes a reset switch for shorting the signal
input and the output of the opamp (operational amplifier), and
capacitive network. The capacitive network connects the signal
input and the output of the opamp, and provides a capacitance of
C.sub.T between the signal input and the output of the opamp
wherein C.sub.T<C.sub.pd. The capacitive network is constructed
from a plurality of component capacitors. Preferably each component
capacitor has a capacitance greater than or equal to C.sub.pd. In
one embodiment of the invention, the capacitive network includes
first, second, and third component capacitors, each capacitor
having first and second terminals. The first terminal of the first
capacitor is connected to the output of the opamp; the second
terminal of the first capacitor, the first terminal of the second
capacitor, and the first terminal of the third capacitor are
connected together at a first common node, the second terminal of
the third capacitor is connected to the signal input of the opamp,
and the second terminal of the second capacitor is connected to the
second terminal of the parasitic capacitor. The capacitive network
also includes a first network switch for connecting the first
common node to the output of the opamp.
[0017] An imaging array according to the present invention includes
a plurality of imaging elements, a signal bus, a reset bus, and a
reset circuit. Each imaging element also includes a coupling switch
for connecting the output of the opamp to the signal bus and a
reset coupling switch for connecting the photodiode to the reset
bus via a low-pass filter. The reset circuit includes a second
opamp having a signal input, a reference input connected to a
second reference potential, and an output connected to the reset
bus; and a reset coupling switch for connecting the signal input of
the second opamp to the signal bus. In the preferred embodiment of
the present invention, low-pass filters are constructed from a
network of capacitors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic drawing of a portion of prior art
image sensor array 10 representing one column of a two-dimensional
array.
[0019] FIG. 2 is a schematic drawing of an imaging element 40
according to the present invention.
[0020] FIG. 3 is a schematic drawing of another embodiment of a
transimpedance amplifier according to the present invention.
[0021] FIG. 4 is a schematic drawing of one column of an imaging
array 100 made up of imaging elements according to the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0022] The manner in which the present invention obtains its
advantages can be more easily understood with reference to FIG. 1
which is a schematic drawing of a portion of prior art image sensor
array 10. The portion of the array shown in FIG. 1 represents one
column of a two-dimensional array. Exemplary imaging elements are
shown at 20 and 30. Each imaging element in the column includes a
photodiode and a capacitive transimpedance amplifier. The
photodiode for imaging element 20 is shown at 21. The photodiode
has a parasitic capacitance shown at 22. The capacitance of this
capacitor will be denoted by C.sub.pd in the following discussion.
The transimpedance amplifiers are constructed from an opamp and a
capacitive feedback loop. The opamp for imaging element 20 is shown
at 23, and the feedback capacitor is shown at 24. The capacitance
of the feedback capacitor will be denoted by C.sub.T in the
following discussion. Each imaging element also has a reset switch
for shorting the input and output of the opamp prior to
accumulating charge. The reset switch is typically a transistor
such as transistor 25.
[0023] The gain of the transimpedance amplifier is proportional to
C.sub.pd/C.sub.T. Hence, to provide high gain,
C.sub.pd>>C.sub.T. In addition, to minimize gain FPN,
C.sub.pd/C.sub.T needs to be constant over the array. C.sub.pd is
normally set to be as small as possible because Cpd is proportional
to pixel size and pixel size is proportional to sensor cost. Since
C.sub.pd>>C.sub.T and C.sub.pd is typically very small
C.sub.T is too small to be reproducible over the array, and the
resulting arrays have suffered from gain FPN.
[0024] The present invention overcomes this problem by replacing
the feedback capacitor 24 with a network of capacitors constructed
from capacitors that are large enough to be reproducibly
fabricated. The capacitors are chosen such that the network has a
capacitance that is small compared to C.sub.pd. Refer now to FIG.
2, which is a schematic drawing of an imaging element 40 according
to the present invention. Imaging element 40 is similar to imaging
element 20 shown in FIG. 1 in that it includes a photodiode 41
having a parasitic capacitor 42 having a capacitance denoted by
C.sub.pd. Imaging element 40 also includes a capacitive
transimpedance amplifier constructed from an opamp 43 and a
capacitive network consisting of capacitors 46-48 whose
capacitances will be denoted by C.sub.1-C.sub.3, respectively, in
the following discussion. Reset switches 45 and 49 short the
capacitors prior to accumulating charge. The capacitance of the
network is C.sub.3C.sub.1/(C.sub.1+C.sub.2- +C.sub.3). Hence, if
C.sub.3 and C.sub.1 are about the same size as C.sub.pd, i.e.,
C.sub.1=C.sub.3=C.sub.pd and C.sub.2=G*C.sub.pd, where G>>1,
the resulting network will have a capacitance that is approximately
C.sub.pd/G, and all of the capacitors will be of a size that can be
reproducibly fabricated. The reset switches are preferably operated
such that switch 49 closes prior to switch 45. This order of
operation minimizes the effects of the noise generated by the
electrons leaving the transistors when the state of the switches
changes.
[0025] While the embodiment shown in FIG. 2 utilizes a three
capacitor network and two shorting switches, it will be obvious to
those skilled in the art from the preceding discussion that more
complex networks may be utilized. Refer now to FIG. 3, which is a
schematic drawing of another embodiment of a transimpedance
amplifier according to the present invention. Transimpedance
amplifier 50 is constructed from an opamp 59 and a capacitive
feedback loop constructed from a 5 capacitor network whose
capacitances are denoted by C.sub.1-C.sub.5. This network utilizes
three shorting switches shown at 51-53. Transimpedance amplifier 50
provides higher gain for the same size capacitors. For example, if
C.sub.1=C.sub.3=C.sub.5=C.sub.pd, and C.sub.2=C.sub.4=G*C.sub.pd,
then the effective capacitance of the network is approximately
C.sub.pd/G.sup.2, and the gain of the transimpedance amplifier will
be G.sup.2.
[0026] The arrangement shown in FIG. 3 has the further advantage of
providing a transimpedance amplifier with switchable gain. If
during the operation of the amplifier shorting switch 53 remains
closed, the effective capacitance of the network will increase, and
the gain will decrease accordingly.
[0027] It will be apparent from the preceding discussion, that
other capacitive networks may be utilized. For example, the
networks shown in FIGS. 2 and 3 can be extended further by
incorporating additional capacitive dividers and shorting switches.
In addition, any other capacitive network connected so as to
provide a net capacitance that is much less than C.sub.pd may also
be used. It should be noted that a purely capacitive network is
preferred, because resistors introduce thermal noise into the
system. In this regard, it should be noted that inductors always
have finite resistances, and hence, inductive networks are not
preferred.
[0028] While the capacitive feedback networks described above
substantially decrease gain FPN, these networks do little to
eliminate offset FPN. Refer now to FIG. 4, which is a schematic
drawing of one column of an imaging array 100 made up of imaging
elements according to the present invention. Exemplary imaging
elements are shown at 110 and 120. Imaging element 110 includes a
capacitive transimpedance amplifier constructed from opamp 111 and
a capacitive feedback network, preferably of the type discussed
above. To simplify the drawings, the capacitive feedback network is
shown as a single capacitor 112; however, it is to be understood
that capacitor 112 can be a single capacitor or any form of
capacitive network such as those discussed above. The form of
capacitive feedback loop does not alter the manner in which the
present invention reduces offset FPN. Imaging element 110 also
includes a photodiode 114 having a parasitic capacitance shown at
115. Each imaging element in array 100 can be connected to a
readout bus 131 by turning on a bus isolation transistor. The bus
isolation transistor for imaging element 110 is shown at 119. Each
imaging element can also be connected to a reset bus 132 by turning
on a reset isolation transistor. The reset isolation transistor for
imaging element 110 is shown at 118.
[0029] Offset FPN is the result of charge being injected into node
141 when reset switch 113 is opened prior to accumulating charge
from photodiode 114. The amount of charge injected into this node
will, in general, be different for each imaging element due to
variations in the reset switches from imaging element to imaging
element. These variations result from variations in the fabrication
process for these transistors. It should be noted that space is at
a premium in an imaging array, and hence, these transistors are
constrained to be as small as possible. As noted above, small
structures have greater variability, especially when the size of
the transistor is of the same order as the minimum feature size
that is available in the fabrication process.
[0030] The present invention overcomes this variability by
providing an offset feedback loop that forces all of the outputs of
the opamps to be the same after the reset process is completed. The
offset feedback loop utilizes an opamp 133, which is shared by all
of the imaging elements in a column. Since only one opamp 133 is
needed per column, the space constraints that apply to opamp 111
and reset switch 113 do not apply to opamp 133. Accordingly, opamp
133 is preferably much larger than opamp 111 and switch 113. In
addition, opamp 133 can also incorporate internal offset correction
to further reduce column based offset FPN. This assures that opamp
133 is reproducible from column to column and contributes an
insignificant amount of offset FPN.
[0031] During the reset operation, opamp 133 is connected to
readout bus 131 by switch 134. Each imaging element in the column
is reset in sequence by connecting that imaging element to buses
131 and 132. Opamp 133 then forces the output of the imaging
element to be V.sub.REF, by transferring charge to the input of the
opamp in that imaging element. This charge transfer needs to be
accomplished in a manner that does not introduce additional offset
FPN or temporal noise.
[0032] The manner in which the reset loops operate will be
discussed with reference to imaging element 110. First, switch 113
is closed to short capacitor 112. Switch 113 is then opened. If
capacitor 112 is constructed from a network that includes switches
that short the internal nodes of the network as described above,
the internal nodes are first shorted by closing and opening the
internal switches in the capacitive network. Switch 118 is then
closed to allow opamp 133 to pump charge to node 141. The opening
and closing of switch 118 can generate offset noise as well as
temporal noise, i.e., thermal and shot noise. To reduce the effects
of this noise source, a low pass filter consisting of capacitors
116 and 117 is utilized. Since the magnitude of the thermal noise
depends on the bandwidth of the signal, the low pass filter limits
the thermal noise. It should be noted that a capacitive low-pass
filter is utilized because capacitors do not introduce additional
temporal noise for the reasons previously discussed.
[0033] Various modifications to the present invention will become
apparent to those skilled in the art from the foregoing description
and accompanying drawings. Accordingly, the present invention is to
be limited solely by the scope of the following claims.
* * * * *