U.S. patent application number 09/238887 was filed with the patent office on 2002-05-30 for device for evaluating characteristic of insulated gate transistor.
Invention is credited to AMISHIRO, HIROYUKI, MARUYAMA, YUKO, YAMAGUCHI, KENJI.
Application Number | 20020063572 09/238887 |
Document ID | / |
Family ID | 16632167 |
Filed Date | 2002-05-30 |
United States Patent
Application |
20020063572 |
Kind Code |
A1 |
YAMAGUCHI, KENJI ; et
al. |
May 30, 2002 |
DEVICE FOR EVALUATING CHARACTERISTIC OF INSULATED GATE
TRANSISTOR
Abstract
A transistor having a longer channel length and serving as a
reference, and a transistor having a shorter channel length and to
be subjected to effective channel length extraction are prepared
(step ST1.1). A hypothetical point at which a change in a total
drain-to-source resistance is estimated to be approximately zero
when a gate overdrive is slightly changed is extracted in a mask
channel length versus total drain-to-source resistance plane. The
values of a function (F) are calculated which are defined by the
difference between the rate of change in the total drain-to-source
resistance and the product of a channel resistance per unit length
and the rate of change in a mask channel length at the hypothetical
points (step ST1.6). A true threshold voltage of the transistor
having the shorter channel length is determined by a shift amount
(.delta.) which minimizes the standard deviation of the function
(F) determined in the step ST1.7 (step ST1.10). A resistance-based
method thus extracts an effective channel length and a series
resistance with increased accuracy.
Inventors: |
YAMAGUCHI, KENJI; (TOKYO,
JP) ; AMISHIRO, HIROYUKI; (TOKYO, JP) ;
MARUYAMA, YUKO; (TOKYO, JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Family ID: |
16632167 |
Appl. No.: |
09/238887 |
Filed: |
January 28, 1999 |
Current U.S.
Class: |
324/762.09 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/00 20130101; H01L 2924/0002 20130101; G01R 31/2621
20130101 |
Class at
Publication: |
324/769 |
International
Class: |
H01L 023/58; G01R
031/26 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 28, 1998 |
JP |
P10-213019 |
Claims
We claim:
1. An insulated gate transistor characteristic evaluation device
using at least two insulated gate transistors differing from each
other only in mask channel length and including a first insulated
gate transistor having a longer channel length and a second
insulated gate transistor having a shorter channel length, said
insulated gate transistor characteristic evaluation device for
evaluating a characteristic of said second insulated gate
transistor using a characteristic of said first insulated gate
transistor as a reference, said insulated gate transistor
characteristic evaluation device comprising: threshold voltage
estimation means for extracting a threshold voltage for said first
insulated gate transistor to estimate a threshold voltage for said
second insulated gate transistor to define the estimated value as a
first estimated value; extraction means for extracting a
hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when first and
second gate overdrives are slightly changed, based on a
characteristic curve drawn in an X-Y plane with said mask channel
length measured on an X-axis and said total drain-to-source
resistance measured on a Y-axis, said characteristic curve
indicating the relationship between said mask channel length of
said first and second insulated gate transistors and said total
drain-to-source resistance, the value of said mask channel length
and the value of said total drain-to-source resistance at said
hypothetical point being defined as second and third estimated
values, respectively, said extraction means also extracting the
slope of said characteristic curve at said hypothetical points to
define the value of the slope as a fourth estimated value, said
first gate overdrive being defined as the difference between the
gate voltage of said first insulated gate transistor and the
extracted threshold voltage of said first insulated gate
transistor, said second gate overdrive being defined as the
difference between the gate voltage of said first and second
insulated gate transistors and said first estimated value;
threshold voltage determination means for determining optimum
second to fourth estimated values that are respective ones of said
second to fourth estimated values which satisfy that the amount of
change in said third estimated value equals the product of the
amount of change in said second estimated value and said fourth
estimated value when said first and second gate overdrives are
slightly changed, to determine an optimum first estimated value
associated with said optimum second to fourth estimated values,
thereby to determine a true threshold voltage of said second
insulated gate transistor based on said optimum first estimated
value; and channel length reduction determination means for
determining the difference between said mask channel length and an
effective channel length, and a series resistance, based on said
true threshold voltage.
2. The insulated gate transistor characteristic evaluation device
according to claim 1, wherein said extraction means approximates
said characteristic curve using a first line drawn in said X-Y
plane and passing through first and second points, said first point
being given for said first insulated gate transistor when said
first gate overdrive has a first value, said second point being
given for said second insulated gate transistor when said second
gate overdrive has said first value.
3. The insulated gate transistor characteristic evaluation device
according to claim 2, wherein said threshold voltage determination
means determines said optimum second to fourth estimated values
which satisfy that the amount of change in said third estimated
value equals the product of the amount of change in said second
estimated value and said fourth estimated value when said first and
second gate overdrives are slightly changed, using the relationship
expressed by 31 F ( , V gtLo ) = dL * ( , V gtLo ) + f ( , V gtLo )
f ' ( , V gtLo ) dL * ' ( , V gtLo ) - DL * ( , V gtLo ) where d is
the difference between the first estimated value of the threshold
voltage of said second insulated gate transistor and the threshold
voltage of said first insulated gate transistor, V.sub.gtLo is said
first gate overdrive, dL* is an X-intercept provided by
extrapolation from said characteristic curve, f is said slope of
said characteristic curve at said hypothetical point, DL* is the X
coordinate of said hypothetical point, and the prime denotes a
first derivative with respect to V.sub.gtLo.
4. The insulated gate transistor characteristic evaluation device
according to claim 2, wherein said threshold voltage determination
means determines said optimum second to fourth estimated values
which satisfy that the amount of change in said third estimated
value equals the product of the amount of change in said second
estimated value and said fourth estimated value when said first and
second gate overdrives are slightly changed, using the relationship
expressed by 32 F ( , V gtLo ) = f 2 ( , V gtLo ) f ' ( , V gtLo )
d L * ' ( , V gtLo ) - R sd * ( , V gtLo ) where .delta. is the
difference between the first estimated value of the threshold
voltage of said second insulated gate transistor and the threshold
voltage of said first insulated gate transistor, V.sub.gtLo , is
said first gate overdrive, dL* is an X-intercept provided by
extrapolation from said characteristic curve, f is said slope of
said characteristic curve at said hypothetical point, R.sub.sd* is
the Y coordinate of said hypothetical point, and the prime denotes
a first derivative with respect to V.sub.gtLo.
5. The insulated gate transistor characteristic evaluation device
according to claim 2, wherein said threshold voltage determination
means determines said optimum second to fourth estimated values
which satisfy that the amount of change in said third estimated
value equals the product of the amount of change in said second
estimated value and said fourth estimated value when said first and
second gate overdrives are slightly changed, using the relationship
expressed by 33 F ( , V gtLo ) = R * ( , V gtLo ) - f ( , V gtLo )
f ' ( , V gtLo ) R * ' ( , V gtLo ) - R sd * ( , V gtLo ) where
.delta. is the difference between the first estimated value of the
threshold voltage of said second insulated gate transistor and the
threshold voltage of said first insulated gate transistor,
V.sub.gtLo is said first gate overdrive, R* is a Y-intercept
provided by extrapolation from said characteristic curve, f is said
slope of said characteristic curve at said hypothetical point,
R.sub.sd* is the Y coordinate of said hypothetical point, and the
prime denotes a first derivative with respect to V.sub.gtLo.
6. The insulated gate transistor characteristic evaluation device
according to claim 2, wherein said threshold voltage determination
means determines said optimum second to fourth estimated values
which satisfy that the amount of change in said third estimated
value equals the product of the amount of change in said second
estimated value and said fourth estimated value when said first and
second gate overdrives are slightly changed, using the relationship
expressed by 34 F ( , V gtLo ) = R * ' ( , V gtLo ) f ' ( , V gtLo
) + DL * ( , V gtLo ) where .delta. is the difference between the
first estimated value of the threshold voltage of said second
insulated gate transistor and the threshold voltage of said first
insulated gate transistor, V.sub.gtLo is said first gate overdrive,
R* is a Y-intercept provided by extrapolation from said
characteristic curve, f is said slope of said characteristic curve
at said hypothetical point, DL* is the X coordinate of said
hypothetical point, and the prime denotes a first derivative with
respect to V.sub.gtLo.
7. An insulated gate transistor characteristic evaluation device
using at least two insulated gate transistors differing from each
other only in mask channel length and including a first insulated
gate transistor having a longer channel length and a second
insulated gate transistor having a shorter channel length, said
insulated gate transistor characteristic evaluation device for
evaluating a characteristic of said second insulated gate
transistor using a characteristic of said first insulated gate
transistor as a reference, said insulated gate transistor
characteristic evaluation device comprising: threshold voltage
estimation means for extracting a threshold voltage for said first
insulated gate transistor to estimate a threshold voltage for said
second insulated gate transistor to define the estimated value as a
first estimated value; extraction means for extracting a
hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when a first gate
overdrive and a second gate overdrive are slightly changed, based
on a characteristic curve drawn in an X-Y plane with said mask
channel length measured on an X-axis and said total drain-to-source
resistance measured on a Y-axis, said characteristic curve
indicating the relationship between said mask channel length of
said first and second insulated gate transistors and said total
drain-to-source resistance, the values of said mask channel length
at said hypothetical point being defined as a second estimated
value, said first gate overdrive being defined as the difference
between the gate voltage of said first insulated gate transistor
and the extracted threshold voltage of said first insulated gate
transistor, said second gate overdrive being defined as the
difference between the gate voltage of said second insulated gate
transistor and said first estimated value; threshold voltage
determination means for determining a first estimated value by said
second estimated value, said first estimated value satisfying that
a characteristic curve indicating the relationship between said
second gate overdrive measured on an X-axis and said second
estimated values measured on a Y-axis has a predetermined
configuration in a predetermined range of said second gate
overdrive, to determine the determined first estimated value as a
true threshold voltage of said second insulated gate transistor;
and channel length reduction determination means for determining
the difference between said mask channel length and an effective
channel length, and a series resistance, based on said true
threshold voltage.
8. The insulated gate transistor characteristic evaluation device
according to claim 7, wherein said threshold voltage determination
means determines a standard deviation of said second estimated
value in said predetermined range to detect the characteristic
curve having said predetermined configuration.
9. An insulated gate transistor characteristic evaluation device
comprising: calculation means for extracting an effective channel
length from each of at least two drain current versus gate voltage
characteristics differing from each other in source-drain voltage,
by using a resistance-based method; and output means for
determining an effective channel length by extrapolation from the
effective channel lengths extracted for different source-drain
voltages.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a device for evaluating a
characteristic of an insulated gate transistor which extracts the
effective channel length and also the series resistance of the
insulated gate transistor.
[0003] 2. Description of the Background Art The resistance-based
method is intended for extracting a series resistance R.sub.sd and
an effective channel length L.sub.eff. However, the
resistance-based method determines a channel length reduction DL
(=L.sub.m-L.sub.eff in place of the effective channel length
L.sub.eff where L.sub.m is a mask channel length (designed channel
length). The resistance-based method carries out the extraction on
the assumption that a total drain-to-source resistance R.sub.tot is
the sum of the series resistance R.sub.sd and a channel resistance
R.sub.ch. A relationship which holds between the effective channel
length L.sub.eff and the channel resistance R.sub.ch is such that
the channel resistance R.sub.ch is the product of the effective
channel length L.sub.eff and a channel resistance f per unit
length. FIG. 24 conceptually shows the relationship between the
channel resistance R.sub.ch, the series resistance R.sub.sd, the
effective channel length L.sub.eff, the mask channel length
L.sub.m, and the channel length reduction DL. The relationship
shown in FIG. 25 approximately holds between the total
drain-to-source resistance R.sub.tot and the mask channel length
L.sub.m. Specifically, with a gate voltage V.sub.gs or the gate
voltage V.sub.gs minus a threshold voltage V.sub.th held constant,
the total drain-to-source resistance R.sub.tot changes in constant
proportion to the mask channel length L.sub.m. The gate voltage
V.sub.gs minus the threshold voltage V.sub.th is referred to
hereinafter as a gate overdrive V.sub.gt. It is assumed that
R.sub.tot-L.sub.m lines for various values of the gate overdrive
V.sub.gt intersect at one point. The mask channel length L.sub.m
coordinate of the point of intersection is represented by DL*, and
the total drain-to-source resistance R.sub.tot coordinate thereof
is represented by R.sub.sd*. The symbol * which follows the
reference character representing a value indicates that the value
is determined based on such a relationship which holds between the
total drain-to-source resistance R.sub.tot and the mask channel
length L.sub.m, in other words, based on characteristic curves
plotted in the X-Y plane defined by an X-axis which denotes the
mask channel length and a Y-axis which denotes the total
drain-to-source resistance.
[0004] Many types of resistance-based method have been hithertofore
proposed, among which the Terada-Muta-Chem method (referred to
hereinafter as the TMC method) and the Shift and Ratio method
(referred to hereinafter as the S&R method) are generally
used.
[0005] First, the TMC method is described with reference to FIGS.
26 and 27. Expression (1) providing the relationship between the
total drain-to-source resistance R.sub.tot, the effective channel
length L.sub.eff, the resistance f per channel unit length and the
series resistance R.sub.sd is transformed into Expression (4) by
using Expression (2) providing the relationship between the
effective channel length L.sub.eff, the mask channel length L.sub.m
and the channel length reduction DL and Expression (3) providing a
variable A.
R.sub.tot=L.sub.eff.multidot.f+R.sub.sd (1)
L.sub.eff=L.sub.m-DL (2)
A.ident.-DL.multidot.f+R.sub.sd (3)
R.sub.tot=L.sub.m.multidot.f+A (4)
[0006] It is found from Expression (4) that the resistance f per
unit length and the variable A are determined from the relationship
between the total drain-to-source resistance R.sub.tot and the mask
channel length L.sub.m. The total drain-to-source resistance
R.sub.tot, the mask channel length L.sub.m and the resistance f per
unit length which serve as a function of the gate overdrive
V.sub.gt must be determined, with the gate overdrive V.sub.gt held
constant. As shown in FIG. 26, for example, a plurality of lines
may be plotted for different gate overdrives V.sub.gt1, V.sub.gt2,
. . . by measuring the total drain-to-source resistance R.sub.tot
of MOS transistors having the mask channel length L.sub.m which
takes values L.sub.m1 to L.sub.m4. Then, values f.sub.1, f.sub.2, .
. . of the resistance f per unit length and values A.sub.1,
A.sub.2, . . . of the variable A defined in Expression (3) are
found from the slopes and R.sub.tot-intercepts of the respective
plotted lines.
[0007] With attention focused on Expression (3), the TMC method
extracts the channel length reduction DL and the series resistance
R.sub.sd based on the slope and R.sub.tot-intercept of the line of
the graph of FIG. 27 since the values f.sub.1, f.sub.2, . . . of
the resistance f and the values A.sub.1, A.sub.2, . . . of the
variable A which are found in the above described manner are in the
relationship shown in the graph of FIG. 27. The threshold voltage
V.sub.th of the MOS transistor which serves as a reference for the
calculation of the gate overdrive V.sub.gt is determined by
extrapolation from a source-drain current versus gate voltage
characteristic as shown in FIG. 28.
[0008] The TMC method is of low extraction accuracy because of the
uncertainty of the threshold voltage V.sub.th obtained by the
extrapolation, and thus is not adaptable for an application to
transistors which are not greater than 0.35 .mu.m in channel
length. FIG. 29 shows the influence of the uncertainty of the gate
overdrive V.sub.gt in the case where the mask channel length
L.sub.m, coordinate value DL* of the point of intersection is
determined using two transistors. There is no problem if the gate
overdrives V.sub.gt of the two transistors differ by the same
amount from the true V.sub.gt. On the other hand, a 0.01 V
difference in gate overdrive V.sub.gt between the two transistors,
for example, causes an error on the order of slightly less than
0.01 .mu.m. The extraction error of the threshold voltage V.sub.th
of one of the transistors which has a shorter gate length due to
the series resistance R.sub.sd is about -0.02 V when the
extrapolation is used for the extraction of the threshold voltage
V.sub.th. Thus, the extraction error of the channel length
reduction DL resulting from the uncertainty of the threshold
voltage V.sub.th is estimated to be about -0.01 to about -0.02
.mu.m. Additionally, when data obtained by measuring the gate
voltage V.sub.gs at intervals of 0.1 V are used, there is a
likelihood that a quantization error causes the extraction error of
the threshold voltage V.sub.th on the order of .+-.0.0V, thereby
causing the extraction error of the channel length reduction
DL.
[0009] Next, the S&R method is described below with reference
to FIGS. 30 and 31. The S&R method provides the channel length
reduction DL using Expression (5) using two MOS transistors Sh and
Lo which are equal in mask channel width W.sub.m but differ in mask
channel length L.sub.m. The MOS transistor Lo is a transistor
having a channel length long enough to ignore the influence of the
channel length reduction DL, and the MOS transistor Sh is a
transistor having a shorter channel length. 1 DL = L mSh - L mLo ri
where ri = R totLo ' ( V gs ) R totSh ' ( V gs + 0 ) ( 5 )
[0010] where the marks "<>" denote an average value in a
given region of the gate overdrive V.sub.gt, the prime denotes a
first derivative with respect to the gate overdrive V.sub.gt, and
.delta..sub.0 is the difference (V.sub.thSh-V.sub.thLo) between the
threshold voltages V.sub.thSh and V.sub.thLo of the two MOS
transistors Sh and Lo.
[0011] In other words, the S&R method results in the problem of
determining <ri> for the correct gate overdrive V.sub.gt. An
algorithm for determining <ri> is as follows:
[0012] Step 1: extracting the threshold voltage V.sub.thLo of the
transistor Lo
[0013] Step 2: shifting R.sub.totsh' to R.sub.totsh'+.delta. to
calculate the average value <ri> and a standard deviation
.sigma. (ri) in a given region of the gate overdrive V.sub.gtLo
(=V.sub.gs-V.sub.thLo) (See FIG. 30)
[0014] Step 3: repeating Step 2, with the shift amount .delta.
changed
[0015] Step 4: providing <ri> as
<ri>.delta.=.delta..sub.0 where 67 .sub.0 is the shift amount
.delta. when .sigma.(ri).sup.2 is a minimum, based on the result of
Step 3.
[0016] It should be noted that the changes in the shift amount
.delta. are equivalent to changes in the threshold voltage
V.sub.thSh of the short transistor Sh.
[0017] The S&R method reduces the error resulting from the
uncertainty of the threshold voltage V.sub.th which is the problem
with the TMC method, but presents another problem in that the
region of the gate overdrive V.sub.gt to be calculated must be
adequately determined so that the appropriate channel length
reduction DL is obtained. The S&R method determines <ri>
on the assumption that, when the gate overdrive V.sub.gt is small,
ri is a constant value, in spite of the dependence of ri upon the
gate overdrive V.sub.gt. As a result, the channel length reduction
DL extracted by the S&R method is dependent upon the region of
the gate overdrive V.sub.gt (See FIG. 32).
[0018] The S&R method requires the mask channel length
L.sub.mLo of the long transistor Lo to be sufficiently greater than
the mask channel length L.sub.mSh of the short transistor Sh. As
the mask channel length L.sub.mLo of the long transistor Lo
approaches the mask channel length L.sub.mSh of the short
transistor Sh, <ri> approaches "1," and the value of the
channel length reduction DL accordingly approaches "0" as will be
found from Expression (5) (See FIG. 33). This problem results from
the formulation in defiance of the dependence of the channel length
reduction DL and the series resistance R.sub.sd upon the gate
overdrive V.sub.gt.
[0019] As above described, the conventional resistance-based method
is disadvantageous in the low extraction accuracy of the effective
channel length and the series resistance, and in the dependence of
the extraction accuracy thereof upon the setting of parameters. For
example, the TMC method extracts the effective channel length and
the series resistance with low accuracy because of the error
resulting from the uncertainty of the threshold voltage determined
by the extrapolation. The S&R method reduces the extraction
error of the effective channel length resulting from the
uncertainty of the threshold voltage, but has the drawback that the
value of the effective channel length to be extracted changes
greatly depending on the range of the gate overdrive V.sub.gt to be
specified for calculation.
SUMMARY OF THE INVENTION
[0020] A first aspect of the present invention is intended for a
method of evaluating a characteristic of an insulated gate
transistor. According to the present invention, the method
comprises the steps of: (a) preparing at least two insulated gate
transistors differing from each other only in mask channel length
and including a first insulated gate transistor having a longer
channel length and a second insulated gate transistor having a
shorter channel length; (b) extracting a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
of the threshold voltage as a first estimated value; (c) extracting
a hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when a first gate
overdrive and a second gate overdrive are slightly changed, based
on a characteristic curve plotted in an X-Y plane with the mask
channel length measured on an X-axis and the total drain-to-source
resistance measured on a Y axis, the characteristic curve
indicating the relationship between the mask channel length of the
first and second insulated gate transistors and the total
drain-to-source resistance on the condition that the first and
second gate overdrives are equal, the value of the mask channel
length and the value of the total drain-to-source resistance at the
hypothetical point being defined as second and third estimated
values, respectively, and also extracting the slope of the
characteristic curve at the hypothetical point to define the
extracted value of the slope as a fourth estimated value, the first
gate overdrive being defined as the difference between the gate
voltage of the first insulated gate transistor and the extracted
threshold voltage of the first insulated gate transistor, the
second gate overdrive being defined as the difference between the
gate voltage of the second insulated gate transistor and the first
estimated value; (d) repeating the step (c) with the first
estimated value changed; (e) determining optimum second to fourth
estimated values that are respective ones of the second to fourth
estimated values which satisfy that the amount of change in the
third estimated value equals the product of the amount of change in
the second estimated value and the fourth estimated value when the
first and second gate overdrives are slightly changed, to determine
an optimum first estimated value associated with the optimum second
to fourth estimated values, thereby to determine a true threshold
voltage of the second insulated gate transistor based on the
optimum first estimated value; and (f) determining the difference
between the mask channel length and an effective channel length,
and a series resistance, based on the true threshold voltage.
[0021] Preferably, according to a second aspect of the present
invention, in the method of the first aspect, the characteristic
curve is approximated in the step (e) using a first line drawn in
the X-Y plane and passing through first and second points, the
first point being given for the first insulated gate transistor
when the first gate overdrive has a first value, the second point
being given for the second insulated gate transistor when the
second gate overdrive has the first value.
[0022] Preferably, according to a third aspect of the present
invention, in the method of the second aspect, the optimum second
to fourth estimated values which satisfy that the amount of change
in the third estimated value equals the product of the amount of
change in the second estimated value and the fourth estimated value
when the first and second gate overdrives are slightly changed are
determined in the step (e) using the relationship expressed by 2 F
( , V gtLo ) = d L * ( , V gtLo ) + f ( , V gtLo ) f ' ( , V gtLo )
d L * ' ( , V gtLo ) - DL * ( , V gtLo )
[0023] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, dL* is an
X-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, DL* is the X coordinate of the hypothetical
point, and the prime denotes a first derivative with respect to
V.sub.gtLo.
[0024] Preferably, according to a fourth aspect of the present
invention, in the method of the second aspect, the optimum second
to fourth estimated values which satisfy that the amount of change
in the third estimated value equals the product of the amount of
change in the second estimated value and the fourth estimated value
when the first and second gate overdrives are slightly changed are
determined in the step (e) using the relationship expressed by 3 F
( , V gtLo ) = f 2 ( , V gtLo ) f ' ( , V gtLo ) d L * ' ( , V gtLo
) - R sd * ( , V gtLo )
[0025] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, dL* is an
X-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, R.sub.sd* is the Y coordinate of the
hypothetical point, and the prime denotes a first derivative with
respect to V.sub.gtLo.
[0026] Preferably, according to a fifth aspect of the present
invention, in the method of the second aspect, the optimum second
to fourth estimated values which satisfy that the amount of change
in the third estimated value equals the product of the amount of
change in the second estimated value and the fourth estimated value
when the first and second gate overdrives are slightly changed are
determined in the step (e) using the relationship expressed by 4 F
( , V gtLo ) = R * ( , V gtLo ) - f ( , V gtLo ) f ' ( , V gtLo ) R
* ' ( , V gtLo ) - R sd * ( , V gtLo )
[0027] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, R* is a
Y-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, R.sub.sd* is the Y coordinate of the
hypothetical point, and the prime denotes a first derivative with
respect to V.sub.gtLo.
[0028] Preferably, according to a sixth aspect of the present
invention, in the method of the second aspect, the optimum second
to fourth estimated values which satisfy that the amount of change
in the third estimated value equals the product of the amount of
change in the second estimated value and the fourth estimated value
when the first and second gate overdrives are slightly changed are
determined in the step (e) using the relationship expressed by 5 F
( , V gtLo ) = R * ' ( , V gtLo ) f ' ( , V gtLo ) + D L * ( , V
gtLo )
[0029] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, R* is a
Y-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, DL* is the X coordinate of the hypothetical
point, and the prime denotes a first derivative with respect to
V.sub.gtLo.
[0030] A seventh aspect of the present invention is intended for a
method of evaluating a characteristic of an insulated gate
transistor. According to the present invention, the method
comprises the steps of: (a) preparing at least two insulated gate
transistors differing from each other only in mask channel length
and including a first insulated gate transistor having a longer
channel length and a second insulated gate transistor having a
shorter channel length; (b) extracting a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
of the threshold voltage as a first estimated value; (c) extracting
a hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when a first gate
overdrive and a second gate overdrive are slightly changed, based
on a characteristic curve plotted in an X-Y plane with the mask
channel length measured on an X-axis and the total drain-to-source
resistance measured on a Y-axis, the characteristic curve
indicating the relationship between the mask channel length of the
first and second insulated gate transistors and the total
drain-to-source resistance on the condition that the first and
second gate overdrives are equal, the value of the mask channel
length at the hypothetical point being defined as a second
estimated value, the first gate overdrive being defined as the
difference between the gate voltage of the first insulated gate
transistor and the extracted threshold voltage of the first
insulated gate transistor, the second gate overdrive being defined
as the difference between the gate voltage of the second insulated
gate transistor and the first estimated value; (d) repeating the
step (c) with the first estimated value changed; (e) determining an
optimum first estimated value among the first and second estimated
values associated with the steps (b), (c) and (d), the optimum
first estimated value satisfying that a characteristic curve
indicating the relationship between the second gate overdrive
measured on an X-axis and the second estimated value measured on a
Y-axis has a predetermined configuration in a predetermined range
of the second gate overdrive, to determine a true threshold voltage
of the second insulated gate transistor based on the optimum first
estimated value; and (f) determining the difference between the
mask channel length and an effective channel length, and a series
resistance, based on the true threshold voltage.
[0031] Preferably, according to an eighth aspect of the present
invention, in the method of the seventh aspect, the characteristic
curve includes a plurality of characteristic curves, and the step
(e) comprises the step of determining among the plurality of
characteristic curves an optimum characteristic curve exhibiting
the second estimated value which converge best on a constant value
within the predetermined range to detect the characteristic curve
having the predetermined configuration.
[0032] According to a ninth aspect of the present invention, a
method of evaluating a characteristic of an insulated gate
transistor comprises the steps of: (a) extracting an effective
channel length from each of at least two drain current versus gate
voltage characteristics differing from each other in source-drain
voltage, by using a resistance-based method; and (b) determining an
effective channel length by extrapolation from the effective
channel lengths extracted for different source-drain voltages.
[0033] According to a tenth aspect of the present invention, a
method of fabricating an insulated gate transistor comprises the
steps of: producing at least two insulated gate transistors
differing from each other only in mask channel length; measuring a
drain current characteristic of the two insulated gate transistors,
with a gate voltage and a source-drain voltage changed; determining
a threshold voltage and an effective channel length of the
insulated gate transistors by using a method of evaluating a
characteristic of an insulated gate transistor as recited in one of
the first to ninth aspects; and judging specification fitness of
the drain current characteristic, the threshold voltage and the
effective channel length.
[0034] Am eleventh aspect of the present invention is intended for
an insulated gate transistor characteristic evaluation device using
at least two insulated gate transistors differing from each other
only in mask channel length and including a first insulated gate
transistor having a longer channel length and a second insulated
gate transistor having a shorter channel length, the insulated gate
transistor characteristic evaluation device for evaluating a
characteristic of the second insulated gate transistor using a
characteristic of the first insulated gate transistor as a
reference. According to the present invention, the insulated gate
transistor characteristic evaluation device comprises: threshold
voltage estimation means for extracting a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
as a first estimated value; extraction means for extracting a
hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when first and
second gate overdrives are slightly changed, based on a
characteristic curve drawn in an X-Y plane with the mask channel
length measured on an X-axis and the total drain-to-source
resistance measured on a Y-axis, the characteristic curve
indicating the relationship between the mask channel length of the
first and second insulated gate transistors and the total
drain-to-source resistance, the value of the mask channel length
and the value of the total drain-to-source resistance at the
hypothetical point being defined as second and third estimated
values, respectively, the extraction means also extracting the
slope of the characteristic curve at the hypothetical point to
define the value of the slope as a fourth estimated value, the
first gate overdrive being defined as the difference between the
gate voltage of the first insulated gate transistor and the
extracted threshold voltage of the first insulated gate transistor,
the second gate overdrive being defined as the difference between
the gate voltage of the first and second insulated gate transistors
and the first estimated value; threshold voltage determination
means for determining optimum second to fourth estimated values
that are respective ones of the second to fourth estimated values
which satisfy that the amount of change in the third estimated
value equals the product of the amount of change in the second
estimated value and the fourth estimated value when the first and
second gate overdrives are slightly changed, to determine an
optimum first estimated value associated with the optimum second to
fourth estimated values, thereby to determine a true threshold
voltage of the second insulated gate transistor based on the
optimum first estimated value; and channel length reduction
determination means for determining the difference between the mask
channel length and an effective channel length, and a series
resistance, based on the true threshold voltage.
[0035] Preferably, according to a twelfth aspect of the present
invention, in the insulated gate transistor characteristic
evaluation device of the eleventh aspect, the extraction means
approximates the characteristic curve using a first line drawn in
the X-Y plane and passing through first and second points, the
first point being given for the first insulated gate transistor
when the first gate overdrive has a first value, the second point
being given for the second insulated gate transistor when the
second gate overdrive has the first value.
[0036] Preferably, according to a thirteenth aspect of the present
invention, in the insulated gate transistor characteristic
evaluation device of the twelfth aspect, the threshold voltage
determination means determines the optimum second to fourth
estimated values which satisfy that the amount of change in the
third estimated value equals the product of the amount of change in
the second estimated value and the fourth estimated value when the
first and second gate overdrives are slightly changed, using the
relationship expressed by 6 F ( , V gtLo ) = d L * ( , V gtLo ) + f
( , V gtLo ) f ' ( , V gtLo ) d L * ' ( , V gtLo ) - DL * ( , V
gtLo )
[0037] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, dL* is an
X-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, DL* is the X coordinate of the hypothetical
point, and the prime denotes a first derivative with respect to
V.sub.gtLo.
[0038] Preferably, according to a fourteenth aspect of the present
invention, in the insulated gate transistor characteristic
evaluation device of the twelfth aspect, the threshold voltage
determination means determines the optimum second to fourth
estimated values which satisfy that the amount of change in the
third estimated value equals the product of the amount of change in
the second estimated value and the fourth estimated value when the
first and second gate overdrives are slightly changed, using the
relationship expressed by 7 F ( , V gtLo ) = f 2 ( , V gtLo ) f ' (
, V gtLo ) d L * ' ( , V gtLo ) - R sd * ( , V gtLo )
[0039] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, dL* is an
X-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, R.sub.sd* is the Y coordinate of the
hypothetical point, and the prime denotes a first derivative with
respect to V.sub.gtLo. Preferably, according to a fifteenth aspect
of the present invention, in the insulated gate transistor
characteristic evaluation device of the twelfth aspect, the
threshold voltage determination means determines the optimum second
to fourth estimated values which satisfy that the amount of change
in the third estimated value equals the product of the amount of
change in the second estimated value and the fourth estimated value
when the first and second gate overdrives are slightly changed,
using the relationship expressed by 8 F ( , V gtLo ) = R * ( , V
gtLo ) - f ( , V gtLo ) f ' ( , V gtLo ) R * ' ( , V gtLo ) - R sd
* ( , V gtLo )
[0040] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, R* is a
Y-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, R.sub.sd* is the Y coordinate of the
hypothetical point, and the prime denotes a first derivative with
respect to V.sub.gtLo.
[0041] Preferably, according to a sixteenth aspect of the present
invention, in the insulated gate transistor characteristic
evaluation device of the twelfth aspect, the threshold voltage
determination means determines the optimum second to fourth
estimated values which satisfy that the amount of change in the
third estimated value equals the product of the amount of change in
the second estimated value and the fourth estimated value when the
first and second gate overdrives are slightly changed, using the
relationship expressed by 9 F ( , V gtLo ) = R * ' ( , V gtLo ) f '
( , V gtLo ) + D L * ( , V gtLo )
[0042] where .delta. is the difference between the first estimated
value of the threshold voltage of the second insulated gate
transistor and the threshold voltage of the first insulated gate
transistor, V.sub.gtLo is the first gate overdrive, R* is a
Y-intercept provided by extrapolation from the characteristic
curve, f is the slope of the characteristic curve at the
hypothetical point, DL* is the X coordinate of the hypothetical
point, and the prime denotes a first derivative with respect to
V.sub.gtLo.
[0043] A seventeenth aspect of the present invention is intended
for an insulated gate transistor characteristic evaluation device
using at least two insulated gate transistors differing from each
other only in mask channel length and including a first insulated
gate transistor having a longer channel length and a second
insulated gate transistor having a shorter channel length, the
insulated gate transistor characteristic evaluation device for
evaluating a characteristic of the second insulated gate transistor
using a characteristic of the first insulated gate transistor as a
reference. According to the present invention, the insulated gate
transistor characteristic evaluation device comprises: threshold
voltage estimation means for extracting a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
as a first estimated value; extraction means for extracting a
hypothetical point at which a change in a total drain-to-source
resistance is estimated to be approximately zero when a first gate
overdrive and a second gate overdrive are slightly changed, based
on a characteristic curve drawn in an X-Y plane with the mask
channel length measured on an X-axis and the total drain-to-source
resistance measured on a Y-axis, the characteristic curve
indicating the relationship between the mask channel length of the
first and second insulated gate transistors and the total
drain-to-source resistance, the values of the mask channel length
at the hypothetical point being defined as a second estimated
value, the first gate overdrive being defined as the difference
between the gate voltage of the first insulated gate transistor and
the extracted threshold voltage of the first insulated gate
transistor, the second gate overdrive being defined as the
difference between the gate voltage of the second insulated gate
transistor and the first estimated value; threshold voltage
determination means for determining a first estimated value by the
second estimated value, the first estimated value satisfying that a
characteristic curve indicating the relationship between the second
gate overdrive measured on an X-axis and the second estimated
values measured on a Y-axis has a predetermined configuration in a
predetermined range of the second gate overdrive, to determine the
determined first estimated value as a true threshold voltage of the
second insulated gate transistor; and channel length reduction
determination means for determining the difference between the mask
channel length and an effective channel length, and a series
resistance, based on the true threshold voltage.
[0044] Preferably, according to an eighteenth aspect of the present
invention, in the insulated gate transistor characteristic
evaluation device of the seventeenth aspect, the threshold voltage
determination means determines a standard deviation of the second
estimated value in the predetermined range to detect the
characteristic curve having the predetermined configuration.
[0045] According to a nineteenth aspect of the present invention,
an insulated gate transistor characteristic evaluation device
comprises: calculation means for extracting an effective channel
length from each of at least two drain current versus gate voltage
characteristics differing from each other in source-drain voltage,
by using a resistance-based method; and output means for
determining an effective channel length by extrapolation from the
effective channel lengths extracted for different source-drain
voltages.
[0046] A twentieth aspect of the present invention is intended or a
computer readable recording medium storing therein a characteristic
evaluation program and using at least two insulated gate
transistors differing from each other only in mask channel length
and including a first insulated gate transistor having a longer
channel length and a second insulated gate transistor having a
shorter channel length, the computer readable recording medium for
causing a computer to evaluate a characteristic of the second
insulated gate transistor using a characteristic of the first
insulated gate transistor as a reference. According to the present
invention, the computer readable recording medium comprises: means
for causing the computer to extract a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
as a first estimated value; means for causing the computer to
extract a hypothetical point at which a change in a total
drain-to-source resistance is estimated to be approximately zero
when a first gate overdrive and a second gate overdrive are
slightly changed, based on a characteristic curve drawn in an X-Y
plane with the mask channel length measured on an X-axis and the
total drain-to-source resistance measured on a Y-axis, the
characteristic curve indicating the relationship between the mask
channel length of the first and second insulated gate transistors
and the total drain-to-source resistance on the condition that the
first and second gate overdrives are equal, the value of the mask
channel length and the value of the total drain-to-source
resistance at the hypothetical point being defined as second and
third estimated values, respectively, the means also causing the
computer to extract the slope of the characteristic curve at the
hypothetical point to define the value of the slope as a fourth
estimated value, the first gate overdrive being defined as the
difference between the gate voltage of the first insulated gate
transistor and the extracted threshold voltage of the first
insulated gate transistor, the second gate overdrive being defined
as the difference between the gate voltage of the second insulated
gate transistor and the first estimated value; means for causing
the computer to determine optimum second to fourth estimated values
that are respective ones of the second to fourth estimated values
which satisfy that the amount of change in the third estimated
value equals the product of the amount of change in the second
estimated value and the fourth estimated value when the first and
second gate overdrives are slightly changed, to determine an
optimum first estimated value associated with the optimum second to
fourth estimated values, thereby to determine a true threshold
voltage of the second insulated gate transistor based on the
optimum first estimated value; and means for causing the computer
to determine the difference between the mask channel length and an
effective channel length, and a series resistance, based on the
true threshold voltage.
[0047] An twenty-first aspect of the present invention is intended
for a computer readable recording medium storing therein a
characteristic evaluation program and using at least two insulated
gate transistors differing from each other only in mask channel
length and including a first insulated gate transistor having a
longer channel length and a second insulated gate transistor having
a shorter channel length, the computer readable recording medium
for causing a computer to evaluate a characteristic of the second
insulated gate transistor using a characteristic of the first
insulated gate transistor as a reference. According to the present
invention, the computer readable recording medium comprises: means
for causing the computer to extract a threshold voltage for the
first insulated gate transistor to estimate a threshold voltage for
the second insulated gate transistor to define the estimated value
as a first estimated value; means for causing the computer to
extract a hypothetical point at which a change in a total
drain-to-source resistance is estimated to be approximately zero
when a first gate overdrive and a second gate overdrive are
slightly changed, based on a characteristic curve drawn in an X-Y
plane with the mask channel length measured on an X-axis and the
total drain-to-source resistance measured on a Y-axis, the
characteristic curve indicating the relationship between the mask
channel length of the first and second insulated gate transistors
and the total drain-to-source resistance on the condition that the
first and second gate overdrives are equal, the value of the mask
channel length at the hypothetical point being defined as a second
estimated value, the first gate overdrive being defined as the
difference between the gate voltage of the first insulated gate
transistor and the extracted threshold voltage of the first
insulated gate transistor, the second gate overdrive being defined
as the difference between the gate voltage of the second insulated
gate transistor and the first estimated value; means for causing
the computer to determine a first estimated value by the second
estimated value, the first estimated value satisfying that a
characteristic curve indicating the relationship between the second
gate overdrive measured on an X-axis and the second estimated value
measured on a Y-axis has a predetermined configuration in a
predetermined range of the second gate overdrive, to determine the
determined first estimated value as a true threshold voltage of the
second insulated gate transistor; and means for causing the
computer to determine the difference between the mask channel
length and an effective channel length, and a series resistance,
based on the true threshold voltage.
[0048] As above described, the method of evaluating the
characteristic of the insulated gate transistor according to the
first and seventh aspects of the present invention, the insulated
gate transistor characteristic evaluation device according to the
eleventh and seventeenth aspects of the present invention and the
computer readable recording medium storing therein the
characteristic evaluation program according to the twentieth and
twenty-first aspects of the present invention may accurately
extract the threshold voltage of the second insulated gate
transistor independently of the range of the second gate overdrive
to increase the extraction accuracy of the effective channel length
and the series resistance.
[0049] The method of evaluating the characteristic of the insulated
gate transistor according to the second aspect of the present
invention and the insulated gate transistor characteristic
evaluation device according to the twelfth aspect of the present
invention approximate the characteristic curve using the line.
Then, the hypothetical point may be determined as a point of
intersection of lines, and the slope at the point of intersection
may be determined as the slope of the lines. This is effective in
facilitating the extraction of the hypothetical point and the slope
at the hypothetical point.
[0050] The method of evaluating the characteristic of the insulated
gate transistor according to the third to sixth aspects of the
present invention and the insulated gate transistor characteristic
evaluation device according to the thirteenth to sixteenth aspects
of the present invention need not determine a derivative of the
coordinates of the hypothetical point with respect to the gate
overdrive. This might reduce errors since the coordinate of the
point of intersection determined from the characteristic curve are
more significantly influenced by noises than are the Y- and
X-intercepts of the characteristic curve. Thus, the derivative of
the coordinates of the hypothetical point with respect to the gate
overdrive has a greater error than does the derivative of the
intercepts.
[0051] The method of evaluating the characteristic of the insulated
gate transistor according to the eighth aspect of the present
invention and the insulated gate transistor characteristic
evaluation device according to the eighteenth aspect of the present
invention facilitate the detection of the characteristic curve
having the predetermined configuration to readily increase the
speed of the characteristic evaluation.
[0052] The method of evaluating the characteristic of the insulated
gate transistor according to the ninth aspect of the present
invention and the insulated gate transistor characteristic
evaluation device according to the nineteenth aspect of the present
invention may eliminate errors resulting from drift velocity
saturation to increase the extraction accuracy.
[0053] The method of fabricating the insulated gate transistor
according to the tenth aspect of the present invention may extract
the threshold voltage and the effective channel length with high
accuracy and in a non-destructive manner using the method of
evaluating the characteristic of the insulated gate transistor,
thereby to reduce the time required for the fabrication.
[0054] It is therefore an object of the present invention to
provide a resistance-based method which extracts an effective
channel length and a series resistance with increased accuracy.
[0055] These and other objects, features, aspects and advantages of
the present invention will become more apparent from the following
detailed description of the present invention when taken in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0056] FIG. 1 is a flowchart for illustrating the outline of the
present invention;
[0057] FIG. 2 conceptually illustrates one step of FIG. 1;
[0058] FIG. 3 is a flowchart showing a procedure of a method of
evaluating a characteristic of an insulated gate transistor
according to a first preferred embodiment of the present
invention;
[0059] FIG. 4 is a graph for illustrating the determination of a
true shift amount;
[0060] FIG. 5 is a graph for illustrating an effect of the first
preferred embodiment;
[0061] FIG. 6 is a graph for illustrating another effect of the
first preferred embodiment;
[0062] FIG. 7 is a graph for illustrating still another effect of
the first preferred embodiment;
[0063] FIG. 8 illustrates a high-order approximation;
[0064] FIG. 9 is a block diagram showing an arrangement of a device
for evaluating a characteristic of an insulated gate transistor
according to the first preferred embodiment;
[0065] FIG. 10 conceptually shows a calculation portion shown in
FIG. 9 as implemented using a computer;
[0066] FIG. 11 is a flowchart showing the steps of fabrication of
an insulated gate transistor using the method of evaluating the
characteristic of the insulated gate transistor according to the
first preferred embodiment;
[0067] FIG. 12 is a graph showing the relationship between a mask
channel length and an effective channel length in the fabrication
of the insulated gate transistor;
[0068] FIG. 13 is a graph showing the relationship between the
effective channel length and a threshold voltage in the fabrication
of the insulated gate transistor;
[0069] FIG. 14 is a graph for illustrating the outline of a second
preferred embodiment of the present invention;
[0070] FIG. 15 is a flowchart showing a procedure of the method of
evaluating the characteristic of the insulated gate transistor
according to the second preferred embodiment;
[0071] FIG. 16 is a graph for illustrating the determination of a
channel length reduction according to the second preferred
embodiment;
[0072] FIG. 17 is a block diagram showing an arrangement of the
device for evaluating the characteristic of the insulated gate
transistor according to the second preferred embodiment;
[0073] FIG. 18 is a graph showing a relationship between a
gate-drain voltage and the effective channel length;
[0074] FIG. 19 is a graph showing another relationship between the
gate-drain voltage and the effective channel length;
[0075] FIG. 20 is a graph showing the correction of a gate finished
length by KY and S&I methods;
[0076] FIG. 21 is a graph for comparison between measured values
and a first simulation result of a drain current versus gate
voltage characteristic;
[0077] FIG. 22 is a graph for comparison between the measured
values and a second simulation result of the drain current versus
gate voltage characteristic;
[0078] FIG. 23 is a graph for comparison between the measured
values and a third simulation result of the drain current versus
gate voltage characteristic;
[0079] FIG. 24 conceptually shows the relationship between a
channel resistance, a series resistance, the effective channel
length, the mask channel length, and the channel length
reduction;
[0080] FIG. 25 is a graph showing the relationship which
approximately holds between a total drain-to-source resistance and
the mask channel length;
[0081] FIGS. 26 and 27 are graphs for illustrating the extraction
of the effective channel length in the TMC method;
[0082] FIG. 28 is a graph for illustrating the extraction of the
threshold voltage;
[0083] FIG. 29 is a graph for illustrating an error caused by the
TMC method due to the uncertainty of the threshold voltage;
[0084] FIG. 30 is a graph for illustrating the calculation of a
standard deviation in the S&R method;
[0085] FIG. 31 is a graph for illustrating the determination of the
true shift amount in the S&R method;
[0086] FIG. 32 is a graph showing an example of the dependence of
the channel length reduction upon an upper limit of a gate
overdrive region in the S&R method;
[0087] FIG. 33 is a graph showing an example of the dependence of
the channel length reduction upon the channel length in the S&R
method; and
[0088] FIG. 34 illustrates the definition of Rsd* and Rsd* *
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0089] The outline of a method of evaluating a characteristic of an
insulated gate transistor according to the present invention will
now be described with reference to FIGS. 1 and 2. FIG. 1 is a
flowchart showing the outline of the procedure of the method of
evaluating the characteristic of the insulated gate transistor
according to the present invention. The insulated gate transistor
used herein shall be a MOS transistor. Two ore more MOS transistors
are prepared which are equal in mask channel width W.sub.m but
differ in mask channel length L.sub.m. An effective channel length
L.sub.eff for these MOS transistors is extracted from two or more
drain-source current versus gate voltage characteristics
(I.sub.ds-V.sub.gs characteristics) having different drain-source
voltages V.sub.ds (step ST1). This extraction is performed using a
linear region of the Ids-V.sub.gs characteristics. For example,
with the drain-source voltage V.sub.ds set to 0.05 V, 0.1 V and
0.15 V, the respective effective channel lengths L.sub.eff are
extracted.
[0090] The value of the effective channel length L.sub.eff is
provided by extrapolation from the relationship between the
effective channel length L.sub.eff(0) and the source-drain voltage
V.sub.ds. For instance, the value of an intercept, that is,
L.sub.eff(0) in the graph shown in FIG. 2 depicting the
relationship between the effective channel length L.sub.eff and the
source-drain voltage V.sub.ds is defined as the effective channel
length L.sub.eff (step ST2). A series resistance R.sub.sd is given
by extraction from the Ids-V.sub.gs characteristics when the
source-drain voltage V.sub.ds has a minimum value. The value of the
series resistance R.sub.sd may be determined by the extrapolation
using the relationship between the effective channel length
L.sub.eff and the source-drain voltage V.sub.ds in a manner similar
to the determination of the effective channel length L.sub.eff.
[0091] First Preferred Embodiment
[0092] The method of evaluating the characteristic of the insulated
gate transistor according to a first preferred embodiment of the
present invention will be described hereinafter. In the method of
evaluating the characteristic of the insulated gate transistor
according to the first preferred embodiment, a channel length
reduction DL and the series resistance R.sub.sd are extracted using
the drain current in a linear region of two transistors which are
equal in mask channel width W.sub.m but differ in mask channel
length L.sub.m.
[0093] The step ST1 shown in FIG. 1 in the method of evaluating the
characteristic of the insulated gate transistor according to the
first preferred embodiment will be briefly described below. In the
method of the first preferred embodiment, two MOS transistors which
are equal in mask channel width W.sub.m but differ in mask channel
length L.sub.m are prepared. One of the two MOS transistors which
has a longer mask channel length L.sub.m is referred to hereinafter
as a long transistor Lo or a first insulated gate transistor, and
the other MOS transistor having a shorter mask channel length
L.sub.m is referred to hereinafter as a short transistor Sh or a
second insulated gate transistor. The threshold voltages V.sub.thLo
and V.sub.thSh of the MOS transistors Lo and Sh are extrapolated,
for example, from the I.sub.ds-V.sub.gs characteristics in the
conventional manner described with reference to FIG. 28. The
threshold voltage V.sub.thSh of the second insulated gate
transistor obtained at this time by the extrapolation is a first
estimated value.
[0094] With the threshold voltage V.sub.thLo of the long transistor
Lo fixed, the threshold voltage V.sub.thSh (the first estimated
value) of the short transistor Sh is changed. Then, coordinates
(DL*, R.sub.sd*) of hypothetical points at which changes in the
value of a total drain-to-source resistance R.sub.tot is estimated
to be approximately zero if a gate overdrive V.sub.gt is slightly
changed for the changed values of the threshold voltage V.sub.thSh
are extracted using the coordinates of points of intersection, for
example. At this time, the gate overdrive V.sub.gt of the long
transistor Lo is a first gate overdrive, and the gate overdrive
V.sub.gt of the short transistor Sh is a second gate overdrive. The
values of the coordinate DL* of the hypothetical points are second
estimated values, the values of the coordinate R.sub.sd* thereof
are third estimated values, and the values of the slope f at the
hypothetical points are fourth estimated values.
[0095] Using the threshold voltages V.sub.thLo and V.sub.thSh, the
coordinates (DL*, R.sub.sd*) of the hypothetical point are
extracted from the relationship between the total drain-to-source
resistance R.sub.tot and the mask channel length L.sub.m. An
example of the method of extracting the hypothetical point from the
relationship between the total drain-to-source resistance R.sub.tot
and the mask channel length L.sub.m includes, for example, a
conventional method of extracting the point of intersection of two
R.sub.tot-L.sub.m characteristic curves (lines) drawn in the graph
shown in FIG. 25, that is, the graph showing the mask channel
length L.sub.m on the X-axis versus the total drain-to-source
resistance R.sub.tot on the Y-axis. For instance, in FIG. 25, the
line indicative of the gate overdrive V.sub.gt is a first line, a
point which satisfies the mask channel length L.sub.m=L.sub.mLo on
the first line is a first point, and a point which satisfies the
mask channel length L.sub.m=L.sub.mSh on the first line is a second
point. However, the estimation of the coordinate of the
hypothetical point is not limited to the above described method.
For example, a curve determined by three or more points, rather
than the line passing through two points, may be used for the
estimation, and a point adjacent to the point of intersection may
be used in place of the point of intersection. Among the extracted
coordinates (DL*, R.sub.sd*) of the hypothetical points are
determined those of a hypothetical point estimated to satisfy that
the product of the channel resistance f per unit length and the X
coordinate component of the hypothetical point, that is, the amount
of change in the mask channel length L.sub.m coordinate value DL*
is equal to the Y coordinate component of the hypothetical point,
that is, the amount of change in the total drain-to-source
resistance R.sub.tot coordinate value R.sub.sd* of the hypothetical
point.
[0096] Next, the step ST1 of FIG. 1, that is, the step of
extracting the effective channel length L.sub.eff and the series
resistance R.sub.sd of the MOS transistor for the respective values
of the drain-source voltages V.sub.ds is described in detail with
reference to FIG. 3. First, the I.sub.ds-V.sub.gs characteristics
of the two transistors Lo and Sh which are equal in mask channel
width W.sub.m but differ in mask channel length L.sub.m are
measured (step ST1.1).
[0097] The threshold voltages V.sub.thLo and V.sub.thSh of the long
and short transistors Lo and Sh are extracted by the extrapolation
and the like from the measured I.sub.ds-V.sub.gs characteristics
(step ST1.2). The difference (V.sub.thSh-V.sub.thLo) between the
threshold voltages V.sub.thLo and V.sub.thSh is calculated. The
difference (V.sub.thSh-V.sub.thLo) between the threshold voltages
V.sub.thLo and V.sub.thSh calculated in this manner is designated
hereinafter by .delta. guess.
[0098] The lower and upper limits of a range in which a value
.delta. defined as the threshold voltage difference falls are
determined as .delta..sub.inf=.delta..sub.guess-K and
.delta..sub.sup=.delta..sub.guess- +K, respectively, (step ST1.3)
where K equals 0.2 V, for example. The initial value
.delta.=.delta..sub.inf is set.
[0099] Whether or not the value .delta. to be calculated is between
.delta..sub.inf and .delta..sub.sup is judged (step ST1.4). That
is, whether or not
.delta..sub.inf.ltoreq..delta..ltoreq..delta..sub.sup is
judged.
[0100] The threshold voltage V.sub.thLo of the long transistor Lo
is fixed at the value extracted in the step ST1.2. The threshold
voltage V.sub.thSh of the short transistor Sh is assumed to be the
sum of the value .delta. and the threshold voltage V.sub.thLo of
the long transistor Lo (step ST1.5).
[0101] The gate overdrive V.sub.gt is measured on the basis of the
threshold voltages V.sub.thLo and V.sub.thLo+.delta. provided in
the step ST1.5. The rates of change DL*'(.delta., V.sub.gtn) in the
L.sub.m coordinate value of about 20 hypothetical points, the rates
of change R.sub.sd*(.delta., V.sub.gtn) in the R.sub.tot coordinate
values thereof, and the channel resistances f( 8R, V.sub.gtn) per
unit length thereof are determined in a given region .OMEGA., for
example, a range of the gate overdrive V.sub.gt satisfying 0.3
V.ltoreq.V.sub.gt.ltoreq.1.3 V. From the determined values are
calculated the values of a function F(.delta., V.sub.gtn) expressed
by
F(.delta., V.sub.gtn)=R.sub.sd*'-f.multidot.DL*' (6)
[0102] where n=1, 2, . . . , 20
[0103] Next, a standard deviation a .sigma.[F(.delta.)] of the
function F is calculated in the region .OMEGA. (step ST1.7). The
value of the shift amount .delta. is changed by substituting
.delta.+.OMEGA. for .delta., and the flow returns to the step ST1.4
(step ST1.8).
[0104] The steps ST1.5 to ST1.8 are repeated if it is judged in the
step ST1.4 that
.delta..sub.inf.ltoreq..delta..ltoreq..delta..sub.sup. If it is not
judged in the step ST1.4 that .delta..sub.inf.ltoreq..delta..ltore-
q..delta..sub.sup, the flow proceeds to the step ST1.9. In the step
ST1.9, .delta.=.delta.0 which minimizes the standard deviation a
.sigma.[F(.delta.)] is determined. At that time, the true threshold
voltage V.sub.thSh of the short transistor Sh is the sum of the
threshold voltage V.sub.thLo of the long transistor Lo and .delta.0
determined in the step ST1.9.
[0105] Using the true threshold voltage V.sub.thLo+.delta.0 of the
short transistor Sh which is determined in the step ST1.9, the gate
overdrive V.sub.gt of the short transistor Sh is measured to
determine the values of the L.sub.m coordinate DL*(V.sub.gt) of the
hypothetical points (step ST1.10). It should be noted that the
threshold voltage V.sub.thLo of the long transistor Lo at this time
is based on the value determined in the step ST1.2 as in the step
ST1.5.
[0106] The L.sub.m coordinate value DL* of a hypothetical point at
a stationary point closest to the point at which the gate overdrive
V.sub.gt=0 is determined as the true channel length reduction DL
(step ST1.11). The true channel length reduction DL is an optimum
second estimated value. At the same time, the effective channel
length L.sub.eff is determined by the difference between the mask
channel length L.sub.m and the true channel length reduction DL,
and the series resistance R.sub.sd which is an optimum third
estimated value is determined by
R.sub.sd(V.sub.gt)=R.sub.totLo(V.sub.gt)-(L.sub.mLo-DL).multidot.f(.delta.-
0, V.sub.gt) (7)
[0107] where R.sub.totLo is the total drain-to-source resistance of
the long transistor Lo, and L.sub.mLo is the mask channel length of
the long transistor Lo. An optimum fourth estimated value is the
channel resistance f per unit length obtained using the gate
overdrive V.sub.gt which gives the true channel length reduction
DL.
[0108] The specific procedure of the determination of the true
channel length reduction DL and the like from the standard
deviation of the function F given in Expression (6) is described
below. The method of evaluating the characteristic of the insulated
gate transistor according to the first preferred embodiment employs
a variational method particularly to reduce an error resulting from
the uncertainty of the extrapolation of the threshold voltage,
particularly the uncertainty of the extrapolation of the threshold
voltage of a transistor having a short channel length, with
attention focused on the relationship given in Expression (8) which
holds between the values of the L.sub.m coordinate DL* of the
hypothetical point and dL*, for example. 10 dl * + f f ' d L * ' -
DL * = 0 ( 8 )
[0109] where dL* is the value of an X-intercept provided by the
extrapolation from an R.sub.tot-L.sub.m characteristic curve (line)
drawn in a graph showing the relationship between the total
drain-to-source resistance R.sub.tot on the Y-axis and the mask
channel length L.sub.m on the X-axis. The value dL* is referred to
hereinafter as an L.sub.m-intercept value.
[0110] It is assumed that the threshold voltage difference between
the short transistor Sh and the long transistor Lo is the shift
amount .delta.. The L.sub.m coordinate value DL* of the
hypothetical point the L.sub.m-intercept value dL*, the rate of
change dL*' thereof, the channel resistance f per unit length, and
the rate of change f thereof are determined from
R.sub.totSh(V.sub.gtLo+.delta.-V.sub.thSh+V.sub.thLo) and
R.sub.totLo(V.sub.gtLo). Expression (8) is satisfied when the shift
amount .delta. equals the true threshold voltage difference
.delta.0 between the short transistor Sh and the long transistor
Lo. At that time, the L.sub.m coordinate value DL* of a
hypothetical point at which the threshold voltage V.sub.thLo is
close to zero provides the true channel length reduction DL.
Therefore, the true channel length reduction DL and the series
resistance R.sub.sd may be extracted in a procedure to be described
below.
[0111] Initially, the L.sub.m coordinate value DL* of the
hypothetical point, the L.sub.m-intercept value dL*, and the
channel resistance f per unit length are provided for a given shift
amount .delta. by 11 DL * ( , V gtLo ) = ( L mSh - R totSh R totLo
L mLo ) ( 1 - R totSh R totLo ) - 1 ( 9 ) d L * ( , V gtLo ) = ( L
mSh - R totSh R totLo L mLo ) ( 1 - R totSh R totLo ) - 1 ( 10 ) f
( , V gtLo ) = R totLo - R totSh L mLo - L mSh ( 11 )
[0112] The parameters R.sub.totSh, R.sub.totLo, .delta.R.sub.totSh
and .delta.R.sub.totLo used in Expressions (9) to (11) are
determined by
R.sub.totSh=R.sub.totSh (V.sub.gtLo+.delta.-V.sub.thSh+V.sub.thLo)
(12)
R.sub.totLo=R.sub.totLo (13)
[0113] 12 R totSh = R totSh ( V gtLo + - V thSh + V thLo - V gt 2 )
- R totSh ( V gtLo + - V thSh + V thLo + V gt 2 ) ( 14 ) R totLo =
R totLo ( V gtLo - V gt 2 ) - R totLo ( V gtLo + V gt 2 ) ( 15
)
[0114] The L.sub.m coordinate value DL* of the hypothetical point,
the L.sub.m-intercept value dL*, the rate of change dL*' thereof,
the channel resistance f per unit length, and the rate of change f'
thereof are determined, with the shift amount .delta. changed.
[0115] The function F given in Expression (6), when transformed and
redefined into 13 F ( , V gtLo ) = d L * ( , V gtLo ) + f ( , V
gtLo ) f ' ( , V gtLo ) d L * ' ( , V gtLo ) - DL * ( , V gtLo ) (
16 )
[0116] is easier to determine. The function F defined in Expression
(16) equals zero independently of the gate overdrive V.sub.gtLo
when the shift amount .delta. equals the threshold voltage
difference .delta.0 between the two transistors Lo and Sh. Then,
the shift amount .delta. which minimizes the standard deviation of
the function F in a given region of the gate overdrive V.sub.gtLo
is determined as the true threshold voltage difference
.delta.0.
[0117] FIG. 4 is a graph showing a relationship between the
standard deviation of the function F and the shift amount .delta..
In the graph of FIG. 4, since the standard deviation of the
function F is a minimum when the shift amount .delta. is 0.095 V,
the true threshold voltage difference .delta.0 is set at 0.095
V.
[0118] The value of the true channel length reduction DL is
determined using the value of the above-mentioned threshold voltage
difference .delta.0. For example, the value of the true channel
length reduction DL may be determined in the manner performed in
the step ST1.11 of FIG. 3. Otherwise, the average of the L.sub.m
coordinate values DL*(.delta.0, V.sub.gtLo) of the hypothetical
points at which the gate overdrive V.sub.gtLo of the long
transistor Lo is close to zero may be determined as the true
channel length reduction DL. Using the effective channel length
L.sub.effSh calculated from the true channel length reduction DL,
the series resistance R.sub.sd is determined by
R.sub.totSh(V.sub.st)=L.sub.effSh(V.sub.gt).multidot.f(V.sub.gt)+R.sub.sd(-
V.sub.gt)
[0119] FIGS. 5 to 7 show examples of results of the method of
evaluating the characteristic of the MOS transistor according to
the first preferred embodiment (referred to hereinafter as a KY
method), the S&R method and the TMC method which are applied to
a process for fabricating a MOS transistor with a pattern width of
0.3 .mu.m. FIGS. 5 and 6 suggest that the channel length reduction
DL and the series resistance R.sub.sd extracted by the TMC method
are significantly different from those extracted by the other
methods (S&R and KY methods) because of the uncertainty of the
threshold voltage V.sub.th. FIG. 7 shows that the channel length
reduction DL extracted by the S&R method is significantly
dependent upon the region of the gate overdrive V.sub.gt which is
set for calculation. The channel length reduction DL extracted by
the KY method is stable and is not dependent upon the region of the
gate overdrive V.sub.gt which is set for calculation, as compared
with those extracted by the TMC and S&R methods.
[0120] The relationship between the KY method and the S&R
method can be explicitly shown. The L.sub.m coordinate values DL*
of the hypothetical points determined from the two transistors Sh
and Lo which differ in mask channel length L.sub.m are given by
Expression (10). At a limit as .delta.V.sub.gt approaches zero,
Expression (18) holds. 14 R totSh R totLo = R totSh R totLo = R
totSh ' R totLo ' 1 ri ( 18 )
[0121] Substituting Expression (18) into Expression (10) provides
15 DL * = DL * [ S & R ] ( 1 - 1 ri ) - 1 where DL * [ S &
R ] L mSh - L mLo ri ( 19 )
[0122] where [S&R] denotes a solution by the S&R
method.
[0123] The L.sub.m coordinate value DL* given by Expression (19)
differs by the amount of the correction term (1-1/ri).sup.-1 from
the L.sub.m coordinate value DL*[S&R] of the hypothetical point
calculated by the S&R method which is disclosed in Y. Taur et
al. "A New "Shift and Ratio" Method for MOSFET Channel-Length
Extraction," IEEE Elect. Div. Lett, EDL-13(5), p. 267, 1992
(referred to hereinafter as Reference (1)) where [S&R] denotes
a solution obtained by the S&R method. The difference results
from the fact that the technique disclosed in Reference (1)
neglects the rate of change DL' in the channel length reduction and
the rate of change R.sub.sd' in the series resistance with respect
to the changes in the gate overdrive V.sub.gt when the L.sub.m
coordinate value DL* [S&R] is derived. Without such neglect,
the result given in Expression (12) is obtained.
[0124] If the mask channel length L.sub.mSh of the short transistor
Sh is sufficiently small relative to the mask channel length
L.sub.mLo of the long transistor Lo, the L.sub.m coordinate value
DL*[S&R] of the hypothetical point determined by the S&R
method asymptotically approaches the L.sub.m coordinate value DL*
determined by the KY method. However, there are two differences
between the KY method and the S&R method, which allow the KY
method to provide a more consistent result than does the S&R
method. One of the differences is a difference in method of
determining the difference .delta.0 in threshold voltage V.sub.th
between the two transistors. The S&R method assumes that, when
the gate overdrive V.sub.gt is small, the L.sub.m coordinate values
DL*[S&R] of the hypothetical points have no gate overdrive
dependence (V.sub.gt-dependence). It is because the L.sub.m
coordinate values DL*(V.sub.gt) of the hypothetical points have a
stationary point at or near V.sub.gt=0.7 that the S&R method
provides a suitable result in spite of the V.sub.gt-dependence of
the L.sub.m coordinate values DL*[S&R]. The second difference
is a difference in interpretation of the channel length reduction
DL. In the KY method, the extracted L.sub.m coordinate value DL* of
the hypothetical point near V.sub.gt=0 is defined as the true
channel length reduction DL. The extractable well-defined amount in
the resistance-based method is only the channel length reduction DL
at V.sub.gt=0.
[0125] The function F may be determined using any one of
Expressions (20) to (22) in place of Expression (16) used in the
first preferred embodiment. 16 F ( , V gtLo ) = f 2 ( , V gtLo ) f
' ( , V gtLo ) d L * ' ( , V gtLo ) - R sd * ( , V gtLo ) ( 20 ) F
( , V gtLo ) = R * - f ( , V gtLo ) f ' ( , V gtLo ) R * ' ( , V
gtLo ) - R sd * ( , V gtLo ) ( 21 ) F ( , V gtLo ) = R * ' ( , V
gtLo ) f ' ( , V gtLo ) + D L * ( , V gtLo ) ( 22 )
[0126] The parameter R* in Expressions (21) and (22) denotes the
value of an R.sub.tot-intercept provided by the extrapolation from
the R.sub.tot-L.sub.m characteristics. The use of the Y-intercept
R* or the X-intercept dL* provided at X=0 or Y=0 by the
extrapolation from the R.sub.tot-L.sub.m characteristic curve
(line) drawn in a graph showing the relationship between the mask
channel length L.sub.m on the X-axis and the total drain-to-source
resistance R.sub.tot on the Y-axis may eliminate the need to
differentiate the coordinates (DL*, R.sub.sd*) of the hypothetical
points. There is no difference in accuracy if any one of
Expressions (16), and (20) to (22) is used, but R.sub.sd* must be
calculated if Expressions (20) and (21) are used. Thus, Expression
(16) or (22) is preferably used.
[0127] Although the shift amount .delta. is determined by the
minimum value of the standard deviation of the function F in the
first preferred embodiment, the shift amount .delta. may be
determined by the average value of the function F which is close to
zero or by the minimum value of the sum of squares .SIGMA.F.sup.2
of the function F. However, the final result determined by these
determination methods, unlike the method using the minimum value of
the standard deviation, sometimes contains an error resulting from
an offset of the value of the function F due to calculation
errors.
[0128] Further, although the channel length reduction DL is
determined using the stationary point in the first preferred
embodiment, the L.sub.m coordinate value DL* of a hypothetical
point at which the gate overdrive V.sub.gt has a predetermined
value close to zero may be defined as the channel length reduction
DL For example, the L.sub.m coordinate value DL* of a hypothetical
point at which the gate overdrive V.sub.gt is 0.3 V is defined as
the channel length reduction DL
[0129] In the first preferred embodiment, the channel length
reduction DL is determined by the L.sub.m coordinate value DL* of
the hypothetical point at the stationary point. However, the
average value of DL* in a predetermined range of the gate overdrive
V.sub.gt may be defined as the channel length reduction DL. For
example, the average value of DL* in a range of the gate overdrive
V.sub.gt which satisfies 0.5.ltoreq.V.sub.gt.ltoreq.1.0 is defined
as the channel length reduction DL.
[0130] Further, although the channel length reduction DL is
determined by the L.sub.m coordinate value DL* of the hypothetical
point at the stationary point in the first preferred embodiment,
the maximum value of DL* may be defined as the channel length
reduction DL. When the channel length reduction DL is determined by
other methods, effects similar to those of the first preferred
embodiment are provided.
[0131] Furthermore, although .delta.R.sub.totSh/.delta.R.sub.totLo
is used in Expression (9) in the first preferred embodiment to
determine the L.sub.m coordinate values DL* of the hypothetical
points, R.sub.tOtSh'/R.sub.totLo' may be used in place of
.delta.R.sub.totSh/.del- ta.R.sub.totLo. That is, the calculation
of the rate of change in the total drain-to-source resistance
R.sub.tot of the long transistor Lo and the short transistor Sh
with high accuracy using a high-order approximate formula allows
the extraction of the channel length reduction DL with high
accuracy. For example, when a curve is drawn through points
y.sub.-2, y.sub.-1, y.sub.0, y.sub.1, y.sub.2 and y.sub.3 equally
spaced at intervals h as shown in FIG. 8, the slope of the curve at
the point y.sub.0 may be given by the high-order approximate
formula 17 y 0 ' = 1 12 h ( y - 2 - 8 y - 1 + 8 y 1 - y 2 ) ( 23
)
[0132] The method of evaluating the characteristic of the insulated
gate transistor according to the first preferred embodiment enables
the evaluation with higher accuracy than the conventional methods .
Accordingly, the increase in the accuracy by the use of
R.sub.totSh'/R.sub.totLo' is reflected in the evaluation result
more sufficiently than that of the background art.
[0133] A device for evaluating a characteristic of an insulated
gate transistor according to the first preferred embodiment will
now be described with reference to FIG. 9. The insulated gate
transistor characteristic evaluation device 1 is connected to a
measuring device 3 for measuring an object 2 to be measured. An
example of the object 2 to be measured includes an integrated
circuit with the long and short transistors Lo and Sh incorporated
therein. For instance, an integrated circuit drawn from a lot which
has been subjected to the fabrication steps is set into the
measuring device 3 and then measured therein. The measuring device
3 is controlled by a control portion 4 in the characteristic
evaluation device 1. An input portion 5 provides control
information to the control portion 4, and comprises a keyboard, a
mouse, and the like. Measurement data from the measuring device 3
and the control information are inputted from the control portion 4
to a calculation portion 6. The calculation portion 6 extracts the
effective channel length L.sub.eff and the series resistance
R.sub.sd, based on the data inputted from the input portion 5. An
output portion 7 outputs the extracted effective channel length
L.sub.eff, the extracted series resistance R.sub.sd, and the
control information used during the extraction. The control
information outputted from the output portion 7 is provided from
the control portion 4 and the calculation portion 5.
[0134] The calculation portion 6 comprises a threshold voltage and
hypothetical shift amount determination portion 11 for determining
the threshold voltages V.sub.thLo and V.sub.thSh and hypothetical
shift amounts .delta.; an extraction portion 12 for extracting the
coordinates (DL*, R.sub.sd*) of points of intersection which are
the coordinates of the hypothetical points, and the slopes f of a
characteristic curve at the points of intersection; a true shift
amount determination portion 13 for determining the true shift
amount .delta.0; and a channel length reduction determination
portion 14 for determining the channel length reduction DL, the
effective channel length L.sub.eff, and the series resistance
R.sub.sd. The coordinates of the points of intersection are used
herein as the coordinates of the hypothetical points at which
changes in the total drain-to-source resistance R.sub.tot are
estimated to be approximately zero if the gate overdrive V.sub.gt
is slightly changed based on the L.sub.m-R.sub.tot characteristic
curve. However, the coordinates of the points of intersection may
be determined by other than the method of determining the points of
intersection. Otherwise, the coordinates of other points may be
used as the coordinates of the hypothetical points as above
described. The input portion 5 inputs to the threshold voltage and
hypothetical shift amount determination portion lithe value of the
variable K for determining the upper limit .delta..sub.sup and the
lower limit .delta..sub.inf of the range over which the
hypothetical shift amount .delta. is changed, the range of the
region .OMEGA. of the gate overdrive V.sub.gt to be measured, and
the amount of change .OMEGA. in the hypothetical shift amount
.delta.. The control portion 4 provides the measurement data about
the source-drain current I.sub.ds and the gate-source voltage
V.sub.gs to the threshold voltage and hypothetical shift amount
determination portion 11. Upon receipt of these data, the threshold
voltage and hypothetical shift amount determination portion 11
provides to the extraction portion 12 the threshold voltage
V.sub.thLo of the long transistor Lo and the hypothetical shift
amount .delta. indicative of the difference between the threshold
voltage V.sub.thLo of the long transistor Lo and the threshold
voltage V.sub.thSh of the short transistor Sh. Using the mask
channel length L.sub.m from the input portion 5 and the measurement
data about the source-drain current I.sub.ds and the gate-source
voltage V.sub.gs from the control portion 4, the extraction portion
12 extracts the rates of change dDL*/dV.sub.gt and
dR.sub.sd*/dV.sub.gt in the coordinates (DL*, R.sub.sd*) of the
point of intersection and the slope f of the characteristic curve
in the region .OMEGA. for each shift amount .delta.. Using the rate
of change dDL*/dV.sub.gt in the L.sub.m coordinate of the point of
intersection, the rate of change dR.sub.sd*/dV.sub.gt in the
R.sub.tot coordinate of the point of intersection, and the slope f
of the characteristic curve which are extracted by the extraction
portion 12, the true shift amount determination portion 13
determines the hypothetical shift amount .delta.0 which minimizes
the standard deviation of the function F given by one of
Expressions (16), and (20) to (22) in the region .OMEGA.. After the
true shift amount .delta.0 is determined, the extraction portion 12
outputs the true shift amount .delta.0, and the 1, coordinate DL*
of a point of intersection, the total drain-to-source resistance
R.sub.tot and the slope f of the characteristic curve which are
associated with the true shift amount .delta.0 to the channel
length reduction determination portion 14. The channel length
reduction determination portion 14 determines the channel length
reduction DL, based on the L.sub.m coordinate value DL* of the
hypothetical point at the stationary point, and then performs the
calculations given by Expressions (2) and (7) to determine the
effective channel length L.sub.eff and the series resistance
R.sub.sd. The output portion 7 outputs the channel length reduction
DL, the effective channel length L.sub.eff and the series
resistance R.sub.sd which are determined by the channel length
reduction determination portion 14, the coordinates (DL*,
R.sub.tot) of the points of intersection and the slopes f of the
characteristic curve at the points of intersection which are
extracted by the extraction portion 12, and the true shift amount
.delta.0 determined by the true shift amount determination portion
13.
[0135] The above described arrangement provides the insulated gate
transistor characteristic evaluation device which extracts the
effective channel length L.sub.eff and the series resistance
R.sub.sd with increased accuracy.
[0136] It is needless to say that the insulated gate transistor
characteristic evaluation described in the first preferred
embodiment may be implemented using a computer in such a manner
that the computer reads a characteristic evaluation program 30 for
causing the computer to evaluate the insulated gate transistor
according to the procedure shown in FIG. 3 which is described in
the first preferred embodiment from a recording medium which stores
the characteristic evaluation program 30 therein as shown in FIG.
10. The characteristic evaluation program 30 may be executed to
extract measurement data 33 including the data pertaining to the
effective channel length L.sub.eff and the series resistance
R.sub.sd, for example, based on measurement data 31 from the
measuring device 3 of FIG. 9 and control information 32 from the
input portion 5 as described in the first preferred embodiment.
[0137] A method of fabricating an insulated gate transistor
according to the first preferred embodiment will be described
hereinafter with reference to FIG. 11. First, the short transistor
Sh serving as a target and the long transistor Lo serving as a
reference are prototyped (step ST50). Then, the electrical
characteristics of the short transistor Sh and the long transistor
Lo are measured (step ST51). In this step of measurement are
measured the I.sub.ds-V.sub.ds characteristic, an off leak current
I.sub.off, and a drain current I.sub.dmax of each of the
transistors. The off leak current off is a source-drain current
flowing when V.sub.ds=VDD and V.sub.gs=V.sub.bs=0 V, for example.
The current I.sub.dmax is a source-drain current flowing when
V.sub.ds=V.sub.gs=VDD and V.sub.bs=0 V. The reference character VDD
designates a power supply voltage herein.
[0138] Next, the threshold voltage V.sub.thSh and the effective
channel length L.sub.effSh of the short transistor Sh are extracted
from the I.sub.ds-V.sub.ds characteristic and the like by using the
method of evaluating the characteristic of the insulated gate
transistor described in the first preferred embodiment. Then,
whether or not the threshold voltage V.sub.thSh, the effective
channel length I.sub.effSh and the currents I.sub.dmax and
I.sub.off of the short transistor Sh satisfy specifications is
judged (step ST53). If the specifications are not satisfied, the
flow returns to the step ST50, and prototypes are again produced
using a new mask.
[0139] The method of evaluating the characteristic of the insulated
gate transistor according to the first preferred embodiment may
determine the threshold voltage based on the known mask channel
length and the electrical characteristics with high accuracy,
thereby to reduce the time required for fabrication as compared
with the method which involves the observation of the cross-section
of the insulated gate transistor. Additionally, the method of
evaluating the characteristic of the insulated gate transistor
according to the first preferred embodiment may accurately
determine the range of the effective channel length L.sub.eff for
the desired mask channel length L.sub.m in accordance with the gate
overdrive V.sub.gt. Further, the method of evaluating the
characteristic of the insulated gate transistor according to the
first preferred embodiment may accurately determine the range of
changes in the threshold voltage V.sub.th in corresponding relation
to the range of changes in the effective channel length L.sub.eff
at the same time (See FIG. 13), thereby facilitating quality
control for the threshold voltage V.sub.th in the fabrication
steps.
[0140] Second Preferred Embodiment
[0141] The outline of the method of evaluating the characteristic
of the insulated gate transistor according to a second preferred
embodiment of the present invention will now be described with
reference to FIG. 14. FIG. 14 is a graph showing changes in the
L.sub.m coordinate value DL* versus the gate overdrive V.sub.gt
determined by the method of evaluating the characteristic of the
insulated gate transistor of the first preferred embodiment. The
graph of FIG. 14 depicts the changes in the L.sub.m coordinate
value DL* for five short transistors Sh having different mask
channel length L.sub.mSh when the true threshold voltage is used.
The mask channel length L.sub.mLo of the long transistor Lo serving
as a reference for extraction of the L.sub.m coordinate value DL*
is commonly 21.6 .mu.m. It will be understood from the comparison
between the graphs of FIGS. 14 and 16 that, when the true threshold
voltage is used, the changes in the L.sub.m coordinate value DL*
versus the gate overdrive V.sub.gt are substantially similar
independently of the mask channel length L.sub.mSh of the short
transistor Sh. Thus, if the value of the gate overdrive V.sub.gt
which conforms to the characteristic curves of this graph, for
example, in a range from 0.3 to 1.2 V is found, the true threshold
voltage of the short transistors Sh may be extracted. It should be
noted that the first and second insulated gate transistors, the
first and second overdrives and the first and second estimated
values of the second preferred embodiment are similar in definition
to those of the first preferred embodiment.
[0142] An example of the method of evaluating the characteristic of
the insulated gate transistor according to the second preferred
embodiment of the present invention is described below with
reference to FIGS. 15 and 16. In the method shown in FIG. 15, the
characteristic curves shown in FIG. 14 are extracted by using the
small standard deviation of the characteristic curves in the range
from 0.3 to 1.2 V, for example. The method of evaluating the
characteristic of the insulated gate transistor of the second
preferred embodiment determines the true threshold voltage of the
short transistor by utilizing the dependence of the L.sub.m
coordinate value DL* upon the gate overdrive V.sub.gt. Therefore,
the second preferred embodiment is similar to the first preferred
embodiment in the procedure of the determination of the true
threshold voltage. The method of evaluating the characteristic of
the insulated gate transistor of the second preferred embodiment
differs from that of the first preferred embodiment in the step ST1
of the procedure shown in FIG. 1 but is similar thereto in the step
ST2.
[0143] FIG. 15 shows an example of the procedure of the extraction
of the effective channel length L.sub.eff in the step ST1 according
to the second preferred embodiment. The procedure of the extraction
of the effective channel length L.sub.eff in the method of
evaluating the characteristic of the insulated gate transistor of
the second preferred embodiment differs from that of the first
preferred embodiment in that the steps ST1.12, the step ST1.13 and
the steps ST1.14 to ST1.16 of FIG. 15 are used in place of the
steps ST1.6, the step ST1.7, and the steps ST1.9 to ST1.11 of FIG.
3, respectively.
[0144] The graph of FIG. 16 plots the extracted L, coordinate
values DL* of hypothetical points determined in the step ST1.12 of
FIG. 15 on the Y-axis versus the gate overdrive V.sub.gt on the
X-axis. The L.sub.m coordinate value DL* of the hypothetical point
and the gate overdrive V.sub.gt also outside the region .OMEGA. are
plotted in FIG. 16 for ease of illustration of the relationship
between the L.sub.m coordinate value DL* of the hypothetical point
and the gate overdrive V.sub.gt. In the step ST1.13, the average
value of the L.sub.m coordinate value DL* of the hypothetical point
and the standard deviation .sigma.[DL*] are calculated for the
shift amount .delta..
[0145] If it is judged that the calculation in the step ST1.13 for
the shift amount 6 in the predetermined range from .delta..sub.inf
to .delta..sub.sup has been completed, (step ST1.4), the shift
amount .delta.0 which gives the true channel length reduction DL is
estimated in the step ST1.14. The shift amount .delta.0 estimated
herein is the shift amount .delta.0 which minimizes the standard
deviation .sigma.[DL*]. In the step ST1.15, the true channel length
reduction DL is provided by the average value of the L.sub.m
coordinate value DL* of the hypothetical point for the shift amount
.delta.0. In the step ST1.16, the effective channel length
L.sub.eff is determined by the difference between the mask channel
length L.sub.m and the true channel length reduction DL, and the
series resistance R.sub.sd is determined by Expression (7).
[0146] The device for evaluating the characteristic of the
insulated gate transistor according to the second preferred
embodiment will be described below with reference to FIG. 17. An
insulated gate transistor characteristic evaluation device 1A,
similar to the insulated gate transistor characteristic evaluation
device 1 of the first preferred embodiment, is connected to the
measuring device 3 for measuring the object 2 to be measured. The
elements of the insulated gate transistor characteristic evaluation
device 1A which are designated by the reference characters
identical with those of the characteristic evaluation device 1 of
FIG. 9 are elements corresponding to those of FIG. 9. More
specifically, the characteristic evaluation device 1A is similar to
the characteristic evaluation device 1 except an extraction portion
12A, a true shift amount determination portion 13A and a channel
length reduction determination portion 14A which are included in a
calculation portion 6A. The extraction portion 12A of the
characteristic evaluation device 1A determines the coordinates
(DL*, R.sub.sd*) of points of intersection, with the gate overdrive
V.sub.gt changed in the region .OMEGA.. The true shift amount
determination portion 13A finds the hypothetical shift amount
.delta.0 which minimizes the standard deviation a [DL*] of the
L.sub.m coordinate value DL* of a point of intersection in this
region .OMEGA. to determine the true shift amount .delta.0. The
extraction portion 12A outputs the true shift amount .delta.0 and
its associated L.sub.m coordinate value DL* of the point of
intersection to the channel length reduction determination portion
14A. The channel length reduction determination portion 14A
determines the channel length reduction DL, based on the average of
the L.sub.m coordinate value DL* of the hypothetical points
extending over the region .OMEGA. for the true shift amount
.delta.0.
[0147] The method of fabricating the insulated gate transistor
according to the second preferred embodiment may be provided by
replacing the KY method in the step ST52 of FIG. 11 with the method
of evaluating the characteristic of the insulated gate transistor
of the second preferred embodiment, thereby providing effects
similar to those of the first preferred embodiment.
[0148] In the extraction of the channel length reduction DL
according to the first and second preferred embodiments, the true
channel length reduction DL of the short transistor Sh may be
determined with little influence of the difference between the mask
channel length L.sub.mLo and a gate finished length L.sub.gLo of
the long transistor Lo exerted upon the determination of the
L.sub.m coordinate value DL* of the hypothetical points, if the
mask channel length L.sub.mSh of the short transistor Sh is
sufficiently small relative to the mask channel length L.sub.mLo of
the long transistor Lo (L.sub.mSh<<L.sub.mLo). For instance,
the evaluation of device/circuit performance with a pattern width
of not greater than 0.35 .mu.m requires the extraction of the
channel length reduction DL of each transistor. For the extraction
of the channel length reduction DL for each transistor, two
transistors are used: one short transistor Sh and one long
transistor Lo serving as a reference. In such extraction of the
channel length reduction DL, an error occurs which results from the
difference between a gate finished length L.sub.g and the mask
channel length L.sub.m depending on transistors, which will be
described below. The L.sub.m coordinate value DL* of the
hypothetical point when the mask channel length L.sub.m is used is
given by 18 DL * ( V gt ) = ( L mSh - R totSh ' R totLo ' L mLo ) (
1 - R totSh ' R totLo ' ) - 1 ( 24 )
[0149] The L.sub.g coordinate of a point of intersection in a gate
finished length versus total drain-to-source resistance plane
(L.sub.g-R.sub.tot plane) is designated by DL* *. 19 DL ** ( V gt )
= ( L gSh - R totSh ' R totLo ' L gLo ) ( 1 - R totSh ' R totLo ' )
- 1 ( 25 )
[0150] The difference between the gate finished length L.sub.gLo
and the mask channel length L.sub.mLo of the long transistor Lo is
designated by .DELTA.L.sub.Lo, and the difference between the gate
finished length L.sub.gSh and the mask channel length L.sub.mSh of
the short transistor Sh is designated by .DELTA.L.sub.Sh. Then, the
relationships expressed by
L.sub.gLo=L.sub.mLo+.DELTA.L.sub.Lo (26)
L.sub.gSh=L.sub.mSh+.DELTA.L.sub.Sh (27)
[0151] hold. Using Expression (27) based on Expression (24), the
difference between the L.sub.m coordinate value DL* of the point of
intersection and the L.sub.g coordinate value DL* * of the point of
intersection is 20 DL * - DL ** = - L Sh + R totSh ' R totLo ' ( 1
- R totSh ' R totLo ' ) - 1 L - L Sh + R totSh ' R totLo ' L ( for
L mSh L mLo ) - L Sh + L effSh L effLo L ( 28 )
[0152] where .DELTA.L is defined as
.DELTA.L.ident..DELTA.L.sub.Lo-.DELTA.L.sub.Sh (29)
[0153] Expressions (27) and (28) show that the effective channel
length L.sub.eff of the short transistor Sh is extracted when the
relationship L.sub.mSh<<L.sub.mLo holds. The second term of
the last expression (rightmost side) of Expression (28) represents
an error. 21 L effSh L effLo L < r L effSh ( 30 )
[0154] where r is a relative error. Assuming that
L.sub.Lo.apprxeq.L.sub.m- Lo, Expression (30) is transformed into
22 L mL o > L r ( 31 )
[0155] Expression (31) limits the size of the long transistor Lo.
For example, when .DELTA.L=0.1 .mu.m and r=0.02, the mask channel
length L.sub.mLo of the long transistor Lo is required to be
greater than 5 .mu.m for accurate extraction of the effective
channel length L.sub.effSh of the short transistor Sh.
[0156] The influence of unequal channel widths due to field
isolation variations will now be contemplated. The total
drain-to-source resistance R.sub.tot is expressed by 23 R totSh = L
effSh W effSh g + R sd ( 32 )
[0157] where g is a sheet resistance of a channel.
[0158] Using .DELTA.W (=W.sub.effSh-W.sub.effLo) as the difference
in channel width W between the short transistor Sh and the long
transistor Lo, Expression (32) is transformed into 24 R totSh = L
effSh W effLo + W g + R sd L effSh ( 1 - W W effLo ) W effLo g + R
sd ( 33 )
[0159] Expression (33) shows that the effective channel length
L.sub.effSh appears to be multiplied by (1-.DELTA.W/W.sub.effLo) if
it is assumed that the sheet resistance g is not dependent upon the
effective channel width W.sub.eff. For an error .DELTA.r, 25 L
effSh W W effLo < r L effSh ( 34 )
[0160] is given where r is the relative error.
[0161] Assuming that the effective channel width W.sub.effLo is
approximately equal to the mask channel width W.sub.mLo, Expression
(34) is transformed into 26 W mL o > W r ( 35 )
[0162] Expression (35) limits the mask channel width W.sub.mLo of
the long transistor Lo used for the extraction. For example, when
the effective channel width difference .DELTA.W between the two
transistors Lo and Sh is 0.1 .mu.m and the relative error r is
0.02, the mask channel length L.sub.mLo of the long transistor Lo
is required to be greater than 5 .mu.m for accurate extraction of
the effective channel length L.sub.effSh of the short transistor
Sh.
[0163] The influence of the difference in series resistance
R.sub.sd between transistors used for the extraction will be
contemplated. Assuming that the dependence of the series resistance
R.sub.sd upon the gate overdrive V.sub.gt is negligible, an error
.DELTA.R.sub.sdSh is expressed by 27 R sdSh R sd * - R sd ** L
effSh L effLo - L effSh L effSh L effLo R sd L mSh L mL o R sd ( 36
)
[0164] where A R.sub.sd is given by
.DELTA.R.sub.sd=R.sub.sdSh-R.sub.sdLo (37)
[0165] R.sub.sd*-R.sub.sd** is defined in FIG. 34.
[0166] Using the relative error r, 28 L mSh L mL o R sd < r R
sdSh ( 38 )
[0167] is given. Expression (38) is transformed into 29 L mL o >
1 r R sd R sdSh L mSh ( 39 )
[0168] Expression (39) limits the size of the long transistor Lo.
For example, when .vertline..DELTA.R.sub.sd.vertline./R.sub.sdSh=1,
r=0.05 and L.sub.mSh=0.2 .mu.m, the mask channel length L.sub.mLo
of the long transistor Lo is required to be greater than 4 .mu.m
for accurate extraction of the effective channel length L.sub.effSh
of the short transistor Sh.
[0169] The influence of a saturation drift velocity upon the
extraction of the channel length reduction DL will be contemplated.
The drain current may be estimated as 30 I ds = C OX W eff L eff (
1 + U1 V ds L eff ) - 1 ( V g - V ih - V ds 2 ) ( 40 )
[0170] where .mu. is a mobility, C.sub.ox is an oxide capacitance,
and U1=.mu./(2.multidot.V.sub.sat) where V.sub.sat is a saturation
velocity. The term (1+U1.multidot.V.sub.ds/L.sub.eff).sup.-1
expresses the effect of the saturation drift velocity. Assuming
that the channel resistance per unit channel is not dependent upon
the effective channel length L.sub.eff, the effective channel
length L.sub.effSh of the short transistor Sh effectively appears
to be multiplied by (1+U1.multidot.V.sub.ds/L.sub.eff). As a
result, the extracted channel length reduction DL is smaller by
U1.multidot.V.sub.ds.
[0171] The saturation drift velocity limits the source-drain
voltage V.sub.ds among the measurement bias conditions of the
source-drain current versus source-drain voltage characteristic
(I.sub.ds-V.sub.ds characteristic). FIGS. 18 and 19 show the
dependence (V.sub.ds-dependence) of the extracted values of the
channel length reduction DL upon the source-drain voltage V.sub.ds
for 0.18 .mu.m NMOS and PMOS transistors, respectively. The S&I
method shown in FIGS. 18 and 19 is the method of evaluating the
characteristic of the insulated gate transistor of the second
preferred embodiment. For the PMOS transistor, U1 indicative of the
slope of the characteristic line drawn in the graph is not greater
than about 0.03 .mu.m/V. Thus, when the source-drain voltage
V.sub.ds is not greater than 0.1 V, the extracted values of the
channel length reduction DL have a difference of only not greater
than about 0.003. For the NMOS transistor, on the other hand, the
slope U1 is about 0.15 .mu.m/V. Thus, when the source-drain voltage
V.sub.ds is 0.1 V, the extracted value of the channel length
reduction is about 0.015 .mu.m smaller. The value of the true
effective channel length L.sub.eff is provided by the effective
channel length L.sub.eff at the source-drain voltage V.sub.ds=0 by
the extrapolation from the line indicative of the effective channel
length versus source-drain voltage characteristic, for example, by
using the value of the effective channel length for each drain
voltage inputted from the calculation portion 6 shown in FIG. 9 to
the output portion 7. However, the extracted value from data which
indicates that the source-drain voltage V.sub.ds is 0.05 V is used
for monitoring the effective channel length L.sub.eff in the
fabrication steps. When the extrapolated value is used, the
monitoring must be performed in consideration for the requirement
of data which are at least twice greater and the variations which
might be greater than actual variations.
[0172] The efficient and accurate extraction of a channel length
reduction DLT defined by the difference between the gate finished
length L.sub.g and the effective channel length L.sub.eff is
important for correction of the gate finished length L.sub.g in
parameter extraction associated with logic circuit simulation, for
example, SPICE parameter extraction. For instance, in the SPICE
parameter extraction, an electrical correction is made to the gate
finished length L.sub.g of transistors having a mask channel length
L.sub.m of not greater than about 0.5 .mu.m. The non-linear
relationship between the mask channel length L.sub.m and the gate
finished length L.sub.g is not permitted to be neglected for
transistors having a mask channel length L.sub.m of not greater
than 0.35 .mu.m. Therefore, it is necessary to know the gate
finished length L.sub.g of each of the transistors. However, it is
difficult to measure the gate finished length L.sub.g of all
transistors under an electron microscope. Then, the KY method of
the first preferred embodiment or the S&I method of the second
preferred embodiment may be used to make the electrical correction
to the gate finished length L.sub.g in a manner to be described
below.
[0173] First, the gate finished length L.sub.g of at least one
transistor is measured under an electron microscope by using a
conventional technique. The measured transistor serves as a
reference. Next, the difference DLT between the gate finished
length L.sub.g and the effective channel length L.sub.eff of the at
least one transistor serving as the reference is extracted by the
KY method or the S&I method. Then, the effective channel length
L.sub.eff of a transistor with the gate finished length L.sub.g
having not yet been measured under the electron microscope is
extracted, and the gate finished length L.sub.g of the transistor
is given by the sum of the effective channel length L.sub.eff and
the channel length reduction DLT. An interpolated value of the
channel length reduction DLT is used if two or more transistors
which differ in mask channel length L.sub.m are used as a
reference. It is assumed herein that the variations in the channel
length reduction DLT are negligible relative to the variations in
the gate finished length L.sub.g. FIG. 20 shows the result of the
correction of the gate finished length L.sub.g of a PMOS transistor
having a mask channel length L.sub.m of 0.18 .mu.m by using the KY
method and the S&I method. FIGS. 21 to 23 show the
I.sub.ds-V.sub.ds characteristic for measured values and simulation
results using the values extracted by the KY method when the mask
channel width W.sub.m is 21.6 .mu.m and the mask channel length
L.sub.m is 0.16 .mu.m, 0.18 .mu.m and 0.20 .mu.m, respectively. The
measured values and the simulation results shown in FIGS. 21 to 23
coincide with each other with such accuracy that an error is not
greater than 2%.
[0174] While the invention has been described in detail, the
foregoing description is in all aspects illustrative and not
restrictive. It is understood that numerous other modifications and
variations can be devised without departing from the scope of the
invention.
* * * * *