U.S. patent application number 09/725070 was filed with the patent office on 2002-05-30 for semiconductor device for preventing process-induced charging damages.
This patent application is currently assigned to UNITED MICROELECTRONICS CORP.. Invention is credited to Wang, Mu-Chun.
Application Number | 20020063298 09/725070 |
Document ID | / |
Family ID | 24913044 |
Filed Date | 2002-05-30 |
United States Patent
Application |
20020063298 |
Kind Code |
A1 |
Wang, Mu-Chun |
May 30, 2002 |
Semiconductor device for preventing process-induced charging
damages
Abstract
A semiconductor device for preventing process-induced charging
damages is disclosed. The semiconductor device comprises a
semiconductor layer, at least one transistor comprising a source
region, a drain region, a channel region, a gate oxide layer and a
gate electrode, at least one parasitic capacitor comprising a
conductive layer, a dummy conductive layer constituting a dummy
pattern, and a dielectric layer interposed between the conductive
layer and the dummy conductive layer, a first conductor connecting
the gate electrode and the conductive layer, and a second conductor
connecting the semiconductor layer and the dummy conductive layer.
Furthermore, the dummy conductive layer can be a floating layer
over the semiconductor layer. In such manner, the second conductor
set forth is replaced by an interposed dielectric layer.
Inventors: |
Wang, Mu-Chun; (Pao-Shan
Hsiang, TW) |
Correspondence
Address: |
LOWE HAUPTMAN GILMAN & BERNER, LLP
Suite 310
1700 Diagonal Road
Alexandria
VA
22314
US
|
Assignee: |
UNITED MICROELECTRONICS
CORP.
|
Family ID: |
24913044 |
Appl. No.: |
09/725070 |
Filed: |
November 29, 2000 |
Current U.S.
Class: |
257/379 ;
257/390; 257/532; 257/535; 257/E27.016 |
Current CPC
Class: |
H01L 27/0266 20130101;
H01L 2924/0002 20130101; H01L 27/0629 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/379 ;
257/390; 257/532; 257/535 |
International
Class: |
H01L 029/76; H01L
029/94; H01L 031/062; H01L 023/48 |
Claims
What is claim is:
1. A semiconductor device for preventing process-induced charging
damages, said semiconductor device comprising: a semiconductor
layer; at least one transistor, said transistor comprising a source
region in said semiconductor layer, a drain region in said
semiconductor layer, a channel region in said semiconductor layer
extending between said source region and said drain region, a gate
oxide layer formed over said channel region, and a gate electrode
formed over said gate oxide layer; at least one capacitor over said
semiconductor layer, said capacitor comprising a conductive layer,
a dummy conductive layer forming a dummy pattern, and a dielectric
layer interposed between said conductive layer and said dummy
conductive layer; a first conductor connecting said gate electrode
and said conductive layer; and a second conductor connecting said
dummy conductive layer and said semiconductor layer.
2. The semiconductor device of claim 1, in which said transistor is
an n-type metal oxide semiconductor field effect transistor.
3. The semiconductor device of claim 1, in which said transistor is
a p-type metal oxide semiconductor field effect transistor.
4. The semiconductor device of claim 1, in which said conductive
layer is a copper layer.
5. The semiconductor device of claim 1, in which said conductive
layer is an aluminum layer.
6. The semiconductor device of claim 1, in which said conductive
layers is a polysilicon layer.
7. The semiconductor device of claim 1, in which said dummy
conductive layer is a copper layer.
8. The semiconductor device of claim 1, in which said dummy
conductive layer is an aluminum layer.
9. The semiconductor device of claim 1, in which said dummy
conductive layer is a polysilicon layer.
10. A semiconductor device for preventing process-induced charging
damages, said semiconductor device comprising: a semiconductor
layer; at least one transistor, said transistor comprising a source
region in said semiconductor layer, a drain region in said
semiconductor layer, a channel region in said semiconductor layer
extending between said source region and said drain region, a gate
oxide layer formed over said channel region, and a gate electrode
formed over said gate oxide layer; at least one capacitor over said
semiconductor layer, said capacitor comprising a copper layer, a
dummy conductive layer forming a dummy pattern, and a dielectric
layers interposed between said copper layer and said dummy
conductive layer; a first conductor connecting said gate electrode
and said copper layer; and a second conductor connecting said dummy
conductive layer and said semiconductor layer.
11. The semiconductor device of claim 10, in which said transistor
is an n-type metal oxide semiconductor field effect transistor.
12. The semiconductor device of claim 10, in which said transistor
is a p-type metal oxide semiconductor field effect transistor.
13. The semiconductor device of claim 10, in which said dummy
conductive layer is a copper layer.
14. The semiconductor device of claim 10, in which said dummy
conductive layer is an aluminum layer.
15. The semiconductor device of claim 10, in which said dummy
conductive layer is a polysilicon layer.
16. A semiconductor device for preventing process-induced charging
damages, said semiconductor device comprising: a semiconductor
layer; at least one transistor, said transistor comprising a source
region in said semiconductor layer, a drain region in said
semiconductor layer, a channel region in said semiconductor layer
extending between said source region and said drain region, a gate
oxide layer formed over said channel region, and a gate electrode
formed over said gate oxide layer; at least one capacitor over said
semiconductor layer, said capacitor comprising a portion of said
semiconductor layer, a dummy conductive layer forming a dummy
pattern and above said portion of said semiconductor layer, a
conductive layer above said dummy conductive layer, and two
dielectric layers interposed individually between said conductive
layer and said dummy conductive layer, and between said portion of
said semiconductor layer and said dummy conductive layer; and a
conductor connecting said gate electrode and said conductive
layer.
17. The semiconductor device of claim 16, in which said transistor
is an n-type metal oxide semiconductor field effect transistor.
18. The semiconductor device of claim 16, in which said transistor
is a p-type metal oxide semiconductor field effect transistor.
19. The semiconductor device of claim 16, in which said conductive
layer is a copper layer.
20. The semiconductor device of claim 16, in which said conductive
layer is an aluminum layer.
21. The semiconductor device of claim 16, in which said conductive
layer is a polysilicon layer.
22. The semiconductor device of claim 16, in which said dummy
conductive layer is a copper layer.
23. The semiconductor device of claim 16, in which said dummy
conductive layer is an aluminum layer.
24. The semiconductor device of claim 16, in which said dummy
conductive layer is a polysilicon layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to semiconductor device
technologies and engineering, and more particularly to the
technologies of the protection of semiconductor devices from
process-induced charging damages during semiconductor device
processing.
[0003] 2. Description of the Related Art
[0004] The antenna effect or the floating gate effect is the name
given to the phenomena of induced voltages that can collect on
partially processed leads. The effect is partially prevalent during
plasma processes e.g., etching, deposition, ashing and ion
implantation, and can lead to damage to thin gate oxide regions of
the device under construction.
[0005] Process-induced charging and ensuing gate oxide damage
constitutes a significant yield and reliability detriment for
submicron CMOS technology. Problems occur at many stages of
processing, but are aggravated by long lead lengths at lead
definition following the material of the lead deposition, and the
material of the lead can be, polysilicon, copper and aluminum, for
example. As devices are further scaled to reduced geometries, the
gate oxide becomes progressively thinner and hence more susceptible
to damage, even at reduced voltages.
[0006] Charge accumulation on partially processed leads, and the
resultant voltage increase, can cause voltage overstress and result
in charge trapping in gate oxides and gate oxide breakdown.
Previously, simple n+/p or p+/n junction diodes were used to
protect oxides from the antenna effect during VLSI processing. As
gate oxides have become thinner in reduced geometry devices, such
as 0.5 micron and further reduced geometry devices, gate oxide
damage tends to occur prior to protective junction diode breakdown.
As a consequence, use of the diode for protection from the antenna
effect discussed above becomes ineffective as the gate oxide
thickness is scaled below thicknesses of about 100 angstroms, which
have breakdown voltages on the order of about 16 volts or less.
Accordingly, it would be desirable to provide an alternative type
of protective device that is operable to protect gate oxides having
thicknesses below about 100 angstroms, as can be expected to be
required in the generation ULSI (i.e., less than 100 angstroms gate
oxide thickness) and further reduced geometry devices.
[0007] FIG. 1A depicts a conventional protection device 10 used to
solve the charge induced antenna effect, and FIG. 1B shows the
circuit. It is to be appreciated that the illustrated device can be
constructed in accordance with a variety of known processing
techniques, the specific manner of processing not being relevant to
the following discussion. The protection device 10 includes a
substrate 12 that is typically formed from a semiconductive
material such as silicon, which is doped with a p-type impurity.
The semiconductor substrate 12 can also be formed from a variety of
other semiconductive materials, such as GaAs and HgCdTe, for which
the principles of the present invention that are set forth below
are likewise applicable. In the illustrated structure, a metal
oxide semiconductor field effect transistor (MOSFET) under
construction is designated generally by reference character 14, and
the associated protective component, is designated generally by
reference character 16. The protective component that is presently
utilized in the art is typically an n+/p or a p+/n junction
diode.
[0008] The protection device 10 includes shallow trench isolation
(STI) regions 18a-18d, which can be developed in the substrate 12
in a conventional manner. Interposed between the STI regions 18a
and 18b are source and drain regions 26a, 26b that is formed by
using conventional methods, and a gate oxide region 22 that is
typically thermally grown to a thickness of about 4-20 nm. A layer
of polysilicon 24 is patterned and applied in an appropriate manner
over the gate oxide 22 and doped with an appropriate impurity, such
as phosphorus, to render the polysilicon layer 24 conductive.
Dielectric layer 32 is applied over the polysilicon and underlying
STI regions 18a-18d and is patterned and etched to create a channel
such as a contact opening that extends from an upper surface of the
dielectric layer 32 to an upper surface of the polysilicon layer 24
and a channel that extends from an upper surface of the dielectric
layer 32 to a moat region 36. The contact opening can be filled
with an appropriate metal conductor, such as an alloy of aluminum
or copper, to establish electrical contact between non-adjacent
levels of the protection device 10.
[0009] The illustrated junction diode 16 includes the moat region
36 which is typically doped with an n+ impurity to produce an n+/p
junction diode. The junction diode 16 is electrically connected to
the device gate oxide 22 by a metal lead line 34, thereby
permitting the junction diode to preferentially leak electric
current from the gate oxide region 22 and thereby protect the gate
oxide 22 from currents that may pass through the device. However,
in such manner, a protection diode would need to be designed into
the integrated circuit for each transistor to insure
protection.
[0010] This approach set forth is wasteful of die area because the
introduction of these diodes that include diffusion areas occupy
additional area of the integrated circuit. For example, in certain
designs, the use of diodes can occupy 30%-40% of the area of the
die. Moreover, the introduction of these additional diffusion
areas, by virtue of the layout rules, takes up additional area in
addition to the actual diffusion area to meet these minimum
distance requirements of the layout rule. Therefore, this approach
wastes die area, increases the cost of the integrated circuit, and
sacrifices transistor density. Accordingly, a semiconductor device
for protecting the gate electrode of transistors in a die that save
more diffusion area as compared with the conventional one that use
the protection diodes, and that reduces the cost and space
consumption is desired.
SUMMARY OF THE INVENTION
[0011] It is therefore an object of the invention to provide a
semiconductor device for preventing the process-induced charging
damages by sharing cumulative charges with parasitic capacitors of
the invention used as energy pools.
[0012] It is another object of this invention to provide a
semiconductor device for protecting devices from the
process-induced charging damages, and fighting against charges
build up on the gate oxide of the protected devices by leading the
majority of cumulative charges to the parasitic capacitors.
[0013] It is a further object of this invention to provide a
semiconductor device for protecting devices from the
process-induced charging damages, meanwhile, saving more chip area
than the conventional one by virtue of the use of the parasitic
capacitors.
[0014] It is also an object of this invention to compensate
potential chemical mechanical polishing (CMP) dishing problems by
using a dummy conductive layer constituting a dummy pattern as one
electrode of the parasitic capacitor.
[0015] To achieve these objects, and in accordance with the purpose
of the invention, the invention uses a semiconductor device
comprising a semiconductor layer, at least one transistor
comprising a source region, a drain region, a channel region, a
gate oxide layer and a gate electrode, at least one parasitic
capacitor comprising a conductive layers, a dummy conductive layer
constituting a dummy pattern, and a dielectric layer interposed
individually between the conductive layer and the dummy conductive
layer, a first conductor connecting the gate electrode and the
conductive layer, and a second conductor connecting the
semiconductor layer and the dummy conductive layer. Furthermore,
the dummy conductive layer can be a floating layer over the
semiconductor layer. In such manner, the second conductor set forth
is replaced by an interposed dielectric layer.
[0016] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory only and are not restrictive of the invention, as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The objects, features and advantages of the semiconductor
device for the present invention will be apparent from the
following description in which:
[0018] FIG. 1A shows a schematic cross sectional diagram of a
conventional protection device used to solve the charge induced
antenna effect;
[0019] FIG. 1B shows the circuit of the conventional protection
device shown in FIG. 1A;
[0020] FIG. 2A shows a schematic cross sectional diagram of a first
kind of the protection device of the invention;
[0021] FIG. 2B shows the equivalence protection circuit of the
first kind of the protection device;
[0022] FIG. 3A shows a schematic cross sectional diagram of a
second kind of the protection device of the invention; and
[0023] FIG. 3B shows the equivalence protection circuit of the
second kind of the protection device.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0024] It is to be understood and appreciated that the process
steps and structures described below do not form a complete process
flow for the manufacture of integrated circuits. The present
invention can be practiced in conjunction with various integrated
circuit fabrication techniques that are used in the art, and only
so much of the commonly practiced process steps are included herein
as are necessary to provide an understanding of the present
invention.
[0025] As will be described in greater detail below, the present
invention relates to the provision of a parasitic capacitor in
place of a conventional junction diode for protecting the gate
oxide of the device from cumulative charging damages. Since, for
any capacitance C, where
C=.epsilon.A/t,
[0026] A=surface area of the electrode of the capacitance C,
[0027] .epsilon.=dielectric permittivity of the dielectric
material, and
[0028] t=thickness of the dielectric material.
[0029] With large surface area, the parasitic capacitors of the
present invention can share the majority of process-induced
cumulative charges thereby inhibiting the associated gate oxide of
the protected device from overcharging and breakdown during
processing phase. In addition, the metal electrodes of the
parasitic capacitors provide a dummy pattern, which can compensate
the CMP dishing problem. Furthermore, because the dummy pattern is
formed in the regions where the lead lines of the integrated
circuit are absence, the use of the parasitic capacitors of the
invention can utilize chip area with higher efficiency, meanwhile,
diminish the CMP dishing problem. In addition, due to the larger
capacitance of the parasitic capacitors, one parasitic capacitor
can be connected to more than one protected device, thus designers
or layout engineers can save more chip area.
[0030] FIG. 2A depicts a protection device 40 of the invention used
to prevent the process-induced cumulative charge damages, and FIG.
2B shows the corresponding equivalence protection circuit. It is to
be appreciated that the illustrated device can be constructed in
accordance with a variety of known processing techniques, the
specific manner of process not being relevant to the following
discussion. The protection device 40 includes a substrate 52 that
is typically formed from a semiconductive material such as silicon,
which is doped with a p-type impurity, such as boron ions. The
semiconductor substrate 52 can also be formed from a variety of
other semiconductive materials, such as GaAs and HgCdTe, for which
the principles of the present invention that are set forth below
are likewise applicable. In the illustrated structure, a MOSFET
under construction, which can be treated as a MOS capacitor, is
designated generally by reference character 50, and the associated
protective component, which is a parasitic capacitor, is designated
generally by reference character 60. Source and drain regions 64a,
64b is formed in the semiconductor substrate 52 by using
conventional methods, and a channel region 56 is formed between the
source and drain regions 64a, 64b. A gate oxide region 54 that is
typically thermally grown to a thickness of about 4-20 nm is formed
between the source and drain regions 64a, 64b and on the
semiconductor substrate 52. A gate electrode 58, which can be a
polysilicon layer, is formed by patterning and applying in an
appropriate manner over the gate oxide 54, and doping with an
appropriate impurity, such as phosphorus ions, to render the
polysilicon layer conductive. The gate electrode 58 is connected to
conductive layers 74b and 76 by a lead line 68a. These conductive
layers 74b and 76, that are sited on different levels separately,
become "antennas" unavoidably during processing phases. The
parasitic capacitor 60, comprising a conductive layer 74a as an
electrode and a dummy conductive layer 72 constituting the dummy
pattern as the other electrode, is used to protect the MOSFET 50.
The conductive layer 74a is connected to the gate electrode 58 by
the lead line 68a and the dummy conductive layer 72 is connected to
the semiconductor substrate 52 by the lead line 68a, so that the
parasitic capacitor 60 can share cumulative charges with the MOSFET
50 whenever the antenna effect occurs. The conductive layer 74a and
the dummy conductive layer 72 can be copper, aluminum and
polysilicon, and they are unnecessary the same material.
Furthermore, the electrode 74a of the parasitic capacitor 60 and
the conductive layer 74b are formed together and both are part of
the integrated circuit, whereas the dummy conductive layer 72 is
not. The dummy conductive layer 72 constituting the dummy pattern
can be formed in a similar manner that used to form lead lines of
the integrated circuit in the art. Moreover, it is noted that the
inter-metal dielectric (IMD) layers interposed between the dummy
conductive layer 72 and the conductive layer 74a are not shown in
the illustrated structure. In addition, the parasitic capacitor 60
can also be a stacked multilayer capacitor with
polysilicon-to-metal or polysilicon-to-polysilicon or
metal-to-metal electrodes. In such manner, the parasitic capacitor
60 can be treated as many single capacitors connected in series.
Furthermore, more than one parasitic capacitor similar to the
parasitic capacitor 60 can be connected in parallel in the
integrated circuit.
[0031] Referring to FIG. 2B, the MOSFET 50 and the parasitic
capacitor 60 can be regarded as capacitor C.sub.1 and C.sub.2
connected in parallel, wherein R.sub.1 and R.sub.2 are the
equivalent resistance of the lead line 68a. The equivalent
capacitance C,
C=C.sub.1+C.sub.2,
[0032] wherein
C.sub.1.epsilon.A.sub.1/t.sub.1,
C.sub.2=.epsilon.A.sub.2/t.sub.2,
[0033] A.sub.1=area of the gate electrode 58,
[0034] A.sub.2=area of the electrode of the parasitic capacitor
60,
[0035] t.sub.1=thickness of the gate oxide 54, and
[0036] t.sub.2=average distance between the electrodes of the
parasitic capacitor 60.
[0037] If A.sub.2=2A.sub.1, t.sub.1=t.sub.2, then C.sub.2=2C.sub.1.
For cumulative charges Q and applied voltage V, since Q=CV, the
charges accumulated on C.sub.1 are 0.33Q, and the charges
accumulated on C.sub.2 are 0.667Q.
[0038] In view of the foregoing relationships, the parasitic
capacitor 60 can be constructed to protect the MOSFET 50 from
undesired cumulative charge damages incident to charging for a
prescribed period of time. Furthermore, due to the use of the dummy
pattern as electrodes and larger capacitance of the parasitic
capacitor 60, one parasitic capacitor 60 can be connected to more
than one MOSFET 50 in parallel, thus designers or layout engineers
can save more chip area.
[0039] FIG. 3A depicts a protection device 40' of the invention
used to prevent the cumulative charge damages, and FIG. 3B shows
the corresponding equivalence protection circuit. In this
embodiment, a parasitic capacitor used to protect the MOSFET 50 is
designated generally by reference character 70. The parasitic
capacitor 70 comprises the conductive layer 74a, the dummy
conductive layer 72, and a portion of semiconductor substrate 52
beneath the dummy conductive layer 72. Unlike the parasitic
capacitor 60, the dummy conductive layer 72 of the parasitic
capacitor 70 is "floating", that is, the dummy conductive layer 72
and the portion of semiconductor substrate 52 beneath the dummy
conductive layer 72 constitute an additional capacitor. The
dielectric layers, also known as the inter-metal dielectrics (IMD),
which are interposed between the conductive layer 74a and the dummy
conductive layer 72, and between the dummy conductive layer 72 and
the portion of the semiconductor substrate 52, are not shown in the
structure. Moreover, similar to the parasitic capacitor 60, the
parasitic capacitor 70 also can be a stacked multilayer capacitor
with polysilicon-to-metal or polysilicon-to-polysilicon or
metal-to-metal electrodes. In such manner, the parasitic capacitor
70 can be treated as many single capacitors connected in series. In
addition, similar to the parasitic capacitor 60, more than one
parasitic capacitor 70 can be connected in parallel in the
integrated circuit.
[0040] Referring to FIG. 3B, the parasitic capacitor 70 can be
regarded as capacitors C.sub.2 and C.sub.3 connected in series.
When it connects with the MOSFET 50 in parallel, the equivalent
capacitance C,
C=C.sub.1+(C.sub.2C.sub.3/C.sub.2+C.sub.3),
[0041] wherein
C.sub.2=.epsilon.A.sub.2/t.sub.2,
C.sub.3=.epsilon.A.sub.3/t.sub.3,
[0042] A.sub.2=area of the conductive layer 74a,
[0043] A.sub.3=area of the dummy conductive layer 72,
[0044] t.sub.2=average distance between the electrode 74a and the
dummy conductive layer 72, and t.sub.3=average distance between the
dummy conductive layer 72 and the semiconductor substrate 52.
[0045] If t.sub.1=t.sub.2, t.sub.2=t.sub.3, A.sub.2=2.5A.sub.1, and
A.sub.2=A.sub.3, then C.sub.2=2.5C.sub.1 and C.sub.2=C.sub.3. For
cumulative charges Q and applied voltage V, since Q=CV, the charges
accumulated on C.sub.1 are 0.44Q, and the charges accumulated on
C.sub.2 and C.sub.3 are 0.56Q.
[0046] In view of the foregoing relationships, the parasitic
capacitor 70 can be constructed to protect the MOSFET 50 from
undesired cumulative charge damages incident to charging for a
prescribed period of time since it shares more charges.
Furthermore, due to larger capacitance of the parasitic capacitor
70, one parasitic capacitor 70 can be connected to more than one
MOSFET 50 in parallel, thus designers or layout engineers can save
more chip area.
[0047] Other embodiments of the invention will appear to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein. It is intended that the
specification and examples to be considered as exemplary only, with
a true scope and spirit of the invention being indicated by the
following claims.
* * * * *