U.S. patent application number 09/987340 was filed with the patent office on 2002-05-23 for semiconductor device and method for fabricating the same.
Invention is credited to Nakagawa, Hideo, Tamaoka, Eiji.
Application Number | 20020060354 09/987340 |
Document ID | / |
Family ID | 18824123 |
Filed Date | 2002-05-23 |
United States Patent
Application |
20020060354 |
Kind Code |
A1 |
Nakagawa, Hideo ; et
al. |
May 23, 2002 |
Semiconductor device and method for fabricating the same
Abstract
A plurality of metal interconnects are formed on a lower
interlayer insulating film provided on a semiconductor substrate.
An upper interlayer insulating film is formed so as to cover the
plural metal interconnects. The upper interlayer insulating film
has an air gap between the plural metal interconnects, and a top
portion of the air gap is positioned at a level higher than the
plural metal interconnects.
Inventors: |
Nakagawa, Hideo; (Shiga,
JP) ; Tamaoka, Eiji; (Hyogo, JP) |
Correspondence
Address: |
NIXON PEABODY, LLP
8180 GREENSBORO DRIVE
SUITE 800
MCLEAN
VA
22102
US
|
Family ID: |
18824123 |
Appl. No.: |
09/987340 |
Filed: |
November 14, 2001 |
Current U.S.
Class: |
257/618 ;
257/621; 257/626; 257/734; 257/E21.581; 257/E23.144; 257/E23.167;
438/114; 438/465 |
Current CPC
Class: |
H01L 21/7682 20130101;
H01L 2924/0002 20130101; H01L 23/5329 20130101; H01L 2924/0002
20130101; H01L 23/5222 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/618 ;
257/621; 257/626; 438/114; 438/465; 257/734 |
International
Class: |
H01L 021/44; H01L
029/06; H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 17, 2000 |
JP |
2000-350992 |
Claims
What is claimed is:
1. A semiconductor device comprising: a plurality of metal
interconnects formed on a lower interlayer insulating film provided
on a semiconductor substrate; and an upper interlayer insulating
film covering said plurality of metal interconnects and having an
air gap between said plurality of metal interconnects, wherein a
top portion of said air gap is positioned at a level higher than
said plurality of metal interconnects.
2. The semiconductor device of claim 1, wherein portions of said
lower interlayer insulating film between said plurality of metal
interconnects are trenched by etching, a second insulating film
made from a different material from said lower interlayer
insulating film is formed on said plurality of metal interconnects
with a first insulating film sandwiched therebetween, and said
lower interlayer insulating film has an etching rate higher than an
etching rate of said second insulating film in the etching of said
lower interlayer insulating film.
3. The semiconductor device of claim 2, wherein said lower
interlayer insulating film is made from an inorganic insulating
material including an inorganic component as a principal
constituent and including neither nitrogen nor carbon, or a hybrid
insulating material including an organic component and an inorganic
component, and said second insulating film is made from an
inorganic insulating material including an inorganic material as a
principal constituent and including nitrogen or carbon.
4. The semiconductor device of claim 2, wherein said lower
interlayer insulating film is made from an organic insulating
material including an organic component as a principal constituent,
and said second insulating film is made from an inorganic
insulating material including an inorganic component as a principal
constituent or a hybrid insulating material including an organic
component and an inorganic component.
5. The semiconductor device of claim 2, wherein said lower
interlayer insulating film is made from an inorganic or organic
porous insulating material, and said second insulating film is made
from an inorganic insulating material including an inorganic
component as a principal constituent or a hybrid insulating
material including an organic component and an inorganic
component.
6. A method for fabricating a semiconductor device comprising the
steps of: depositing a first metal film on a lower interlayer
insulating film formed on a semiconductor substrate; forming a
second insulating film made from a different material from said
lower interlayer insulating film on said first metal film with a
first insulating film sandwiched therebetween; forming a contact
plug opening in said second insulating film and said first
insulating film; forming a contact plug by filling said contact
plug opening with a second metal film; forming a transfer pattern
composed of a patterned second insulating film, a patterned first
insulating film and said contact plug by etching said second
insulating film and said first insulating film with a mask pattern
formed on said second insulating film in an interconnect pattern
used as a mask; forming metal interconnects from said first metal
film by etching said first metal film with said transfer pattern
used as a mask; trenching portions of said lower interlayer
insulating film between said metal interconnects by etching said
lower interlayer insulating film under conditions in which said
lower interlayer insulating film has an etching rate higher than an
etching rate of said second insulating film; and forming an upper
interlayer insulating film on said lower interlayer insulating
film, whereby covering said patterned second insulating film and
forming an air gap between said metal interconnects.
7. The method for fabricating a semiconductor device of claim 6,
wherein a top portion of said air gap is positioned at a level
higher than said metal interconnects.
8. The method for fabricating a semiconductor device of claim 6,
wherein said lower interlayer insulating film is made from an
inorganic insulating material including an inorganic component as a
principal constituent and including neither nitrogen nor carbon, or
a hybrid insulating material including an organic component and an
inorganic component, and said second insulating film is made from
an inorganic insulating material including an inorganic material as
a principal constituent and including nitrogen or carbon.
9. The method for fabricating a semiconductor device of claim 6,
wherein said lower interlayer insulating film is made from an
organic insulating material including an organic component as a
principal constituent, and said second insulating film is made from
an inorganic insulating material including an inorganic component
as a principal constituent or a hybrid insulating material
including an organic component and an inorganic component.
10. The method for fabricating a semiconductor device of claim 6,
wherein said lower interlayer insulating film is made from an
inorganic or organic porous insulating material, and said second
insulating film is made from an inorganic insulating material
including an inorganic component as a principal constituent or a
hybrid insulating material including an organic component and an
inorganic component.
11. A method for fabricating a semiconductor device comprising the
steps of: depositing a first metal film on a lower interlayer
insulating film formed on a semiconductor substrate; forming a
second insulating film from a different material from said lower
interlayer insulating film on said first metal film with a first
insulating film sandwiched therebetween; forming a transfer pattern
composed of a patterned second insulating film and a patterned
first insulating film by etching said second insulating film and
said first insulating film with a mask pattern formed on said
second insulating film in an interconnect pattern used as a mask;
forming metal interconnects from said first metal film by etching
said first metal film with said transfer pattern used as a mask;
trenching portions of said lower interlayer insulating film between
said metal interconnects by etching said lower interlayer
insulating film under conditions in which said lower interlayer
insulating film has an etching rate higher than an etching rate of
said second insulating film; and forming an upper interlayer
insulating film on said lower interlayer insulating film, whereby
covering said patterned second insulating film and forming an air
gap between said metal interconnects.
12. The method for fabricating a semiconductor device of claim 11,
wherein a top portion of said air gap is positioned at a level
higher than said metal interconnects.
13. The method for fabricating a semiconductor device of claim 11,
wherein said lower interlayer insulating film is made from an
inorganic insulating material including an inorganic component as a
principal constituent and including neither nitrogen nor carbon, or
a hybrid insulating material including an organic component and an
inorganic component, and said second insulating film is made from
an inorganic insulating material including an inorganic material as
a principal constituent and including nitrogen or carbon.
14. The method for fabricating a semiconductor device of claim 11,
wherein said lower interlayer insulating film is made from an
organic insulating material including an organic component as a
principal constituent, and said second insulating film is made from
an inorganic insulating material including an inorganic component
as a principal constituent or a hybrid insulating material
including an organic component and an inorganic component.
15. The method for fabricating a semiconductor device of claim 11,
wherein said lower interlayer insulating film is made from an
inorganic or organic porous insulating material, and said second
insulating film is made from an inorganic insulating material
including an inorganic component as a principal constituent or a
hybrid insulating material including an organic component and an
inorganic component.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor device
including metal interconnects having an air gap and a method for
fabricating the same.
[0002] A semiconductor device including metal interconnects having
an air gap and a method for fabricating the same according to a
first conventional example will now be described with reference to
FIGS. 11A through 11C, 12A through 12C, 13A through 13C and 14A
through 14C.
[0003] First, as shown in FIG. 11A, a lower interlayer insulating
film 11 of an insulating material is formed on a semiconductor
substrate 10 by chemical vapor deposition (CVD) or spin coating.
Thereafter, although not shown in the drawing, a plug connected to
the semiconductor substrate 10 or an interconnect formed on the
semiconductor substrate 10 is formed in the lower interlayer
insulating film 11.
[0004] Next, a first barrier metal layer 12, a first metal film 13
and a second barrier metal layer 14 are successively deposited on
the lower interlayer insulating film 11. The first barrier metal
layer 12 and the second barrier metal layer 14 are deposited by
sputtering, and the first metal film 13 is formed by the
sputtering, CVD or plating. Thereafter, an insulating film 15 is
formed on the second barrier metal layer 14 by the CVD or spin
coating.
[0005] Then, as shown in FIG. 11B, after forming a first resist
pattern 16 on the insulating film 15 by lithography, the insulating
film 15 is dry etched by using the first resist pattern 16 as a
mask. Thus, plug openings 17 are formed in the insulating film 15
as shown in FIG. 1C.
[0006] Next, as shown in FIG. 12A, a second metal film 18 is
deposited on the insulating film 15 so as to fill the plug openings
17 by the sputtering, CVD or plating.
[0007] Then, as shown in FIG. 12B, an unnecessary portion of the
second metal film 18 present on the insulating film 15 is removed
by chemical mechanical polishing (CMP), thereby forming contact
plugs 19 from the second metal film 18. Thereafter, as shown in
FIG. 12C, the insulating film 15 is dry etched so as to reduce the
thickness thereof. Thus, upper portions of the contact plugs 19
protrude from the insulating film 15.
[0008] Subsequently, as shown in FIG. 13A, a second resist pattern
20 is formed on the insulating film 15 by the lithography. Then, as
shown in FIG. 13B, the insulating film 15 is dry etched by using
the second resist pattern 20 as a mask, thereby forming a patterned
insulating film 15A in the pattern of interconnects.
[0009] Next, as shown in FIG. 13C, the second barrier metal layer
14, the first metal film 13 and the first barrier metal layer 12
are dry etched by using the second resist pattern 20, the patterned
insulating film 15A and the contact plugs 19 as a mask, thereby
forming metal interconnects 21 composed of a patterned second
barrier metal layer 14A, a patterned first metal film 13A and a
patterned first barrier metal layer 12A. In this manner, a
remaining resist 22 in the shape of ridges with facets inclined at
approximately 45 degrees is formed on the patterned insulating film
15A and facets are also formed in top portions of the patterned
insulating film 15A.
[0010] In the first conventional example, the metal interconnects
21 are formed by dry etching the second barrier metal layer 14, the
first metal film 13 and the first barrier metal layer 12 with the
second resist pattern 20, the patterned insulating film 15A and the
contact plugs 19 used as the mask. Instead, the metal interconnects
21 may be formed by dry etching the second barrier metal layer 14,
the first metal film 13 and the first barrier metal layer 12 with
the patterned insulating film 15A and the contact plugs 19 used as
the mask after removing the second resist pattern 20 by ashing. In
this case, the patterned insulating film 15A is sputtered during
the dry etching for forming the metal interconnects 21, and hence,
facets are also formed in the top portions of the patterned
insulating film 15A.
[0011] Next, as shown in FIG. 14A, portions of the lower interlayer
insulating film 11 between the metal interconnects 21 are trenched
by the dry etching. Thus, the remaining resist 22 is removed but is
transferred to the patterned insulating film 15A, resulting in
enlarging the facets of the patterned insulating film 15A.
[0012] Then, as shown in FIG. 14B, an upper interlayer insulating
film 23 is formed over the contact plugs 19, the metal
interconnects 21 and the lower interlayer insulating film 11 by the
CVD and air gaps 24 are formed in the upper interlayer insulating
film 23 between the metal interconnects 21.
[0013] Subsequently, as shown in FIG. 14C, the upper interlayer
insulating film 23 is planarized by the CMP. Thus, the
interconnects having the air gaps are completed. Thereafter, the
aforementioned sequence is repeated, so as to fabricate a
semiconductor device having a multi-layer interconnect
structure.
[0014] Since the upper interlayer insulating film 23 is formed with
the facets formed in the top portions of the patterned insulating
film 15A in the first conventional example, the upper interlayer
insulating film 23 tends to enter the portions between the metal
interconnects 21. Therefore, the top portion of the air gap 24 (a
portion with a triangular cross-section) is positioned at
substantially the same level as the metal interconnect 21.
[0015] A semiconductor device including metal interconnects having
an air gap and a method for fabricating the same according to a
second conventional example will now be described with reference to
FIGS. 15A through 15C, 16A through 16C, 17A through 17C, 18A and
18B.
[0016] First, as shown in FIG. 15A, a lower interlayer insulating
film 31 of an insulating material is formed on a semiconductor
substrate 30 by the CVD or spin coating. Thereafter, although not
shown in the drawing, a plug connected to the semiconductor
substrate 30 or an interconnect formed on the semiconductor
substrate 30 is formed in the lower interlayer insulating film
31.
[0017] Next, a first barrier metal layer 32, a first metal film 33
and a second barrier metal layer 34 are successively deposited on
the lower interlayer insulating film 31. The first barrier metal
layer 32 and the second barrier metal layer 34 are deposited by the
sputtering, and the first metal film 33 is formed by the
sputtering, CVD or plating. Thereafter, an insulating film 35 is
formed on the second barrier metal layer 34 by the CVD or spin
coating.
[0018] Then, after forming a first resist pattern 36 on the
insulating film 35 by the lithography as shown in FIG. 15B, the
insulating film 35 is dry etched by using the first resist pattern
36 as a mask so as to form a patterned insulating film 35A in the
pattern of interconnects as shown in FIG. 15C. Thereafter, the
first resist pattern 36 is removed by the ashing.
[0019] Next, as shown in FIG. 16A, the second barrier metal layer
34, the first metal film 33 and the first barrier metal layer 32
are dry etched by using the patterned insulating film 35A as a
mask, thereby forming metal interconnects 37 composed of a
patterned second barrier metal layer 34A, a patterned first metal
film 33A and a patterned first barrier metal layer 32A. Thus, the
patterned insulating film 35A is sputtered during the dry etching
for forming the metal interconnects 37, and hence, facets are
formed in the top portions of the patterned insulating film
35A.
[0020] Then, as shown in FIG. 16B, portions of the lower interlayer
insulating film 31 between the metal interconnects 37 are trenched
by the dry etching. Thus, the patterned insulating film 35A is
reduced in its thickness with the facets formed in the top portions
thereof.
[0021] Subsequently, as shown in FIG. 16C, an upper interlayer
insulating film 38 is formed over the metal interconnects 37 and
the lower interlayer insulating film 31 by the CVD and air gaps 39
are formed in the upper interlayer insulating film 38 between the
metal interconnects 37.
[0022] Next, after planarizing the upper interlayer insulating film
38 by the CMP as shown in FIG. 17A, a second resist pattern 40 is
formed on the upper interlayer insulating film 38 as shown in FIG.
17B.
[0023] Then, as shown in FIG. 17C, the upper interlayer insulating
film 38 is dry etched by using the second resist pattern 40 as a
mask, thereby forming plug openings 41 in the upper interlayer
insulating film 38. Thereafter, the second resist pattern 40 is
removed by the ashing.
[0024] Subsequently, as shown in FIG. 18A, a second metal film 42
is deposited on the upper interlayer insulating film 38 by the
sputtering, CVD or plating so as to fill the plug openings 41.
[0025] Next, as shown in FIG. 18B, an unnecessary portion of the
second metal film 42 present on the upper interlayer insulating
film 38 is removed by the CMP, so as to form contact plugs 43 from
the second metal film 42. Thus, the interconnects having the air
gaps are completed. Thereafter, the aforementioned sequence is
repeated so as to fabricate a semiconductor device having a
multi-layer interconnect structure.
[0026] Since the upper interlayer insulating film 38 is formed with
the facets formed in the top portions of the patterned insulating
film 35A in the second conventional example, the upper interlayer
insulating film 38 tends to enter the portions between the metal
interconnects 37. Therefore, the top portion of the air gap 39 (a
portion with a triangular cross-section) is positioned at
substantially the same level as the metal interconnect 37.
[0027] If a potential difference is caused between the adjacent
metal interconnects 21 or 37, an electric field is collected at the
upper and lower ends of each metal interconnect 21 or 37. This
results in a problem that the capacitance between the interconnects
is increased.
[0028] Therefore, in the first or second conventional example, the
portions of the lower interlayer insulating film 11 or 31 between
the metal interconnects 21 or 37 are trenched before forming the
upper interlayer insulating film 23 or 38. Thus, the lower ends of
the air gaps 24 or 39 are positioned to be lower than the lower
ends of the metal interconnects 21 or 37, so as to reduce the
capacitance between the interconnects.
[0029] However, the top portions of the air gaps 24 are positioned
at substantially the same level as the metal interconnects 21 as
shown in FIGS. 14B and 14C in the first conventional example and
the top portions of the air gaps 39 are positioned at substantially
the same level as the metal interconnects 37 as shown in FIG. 18B
in the second conventional example. Therefore, the volume of each
air gap 24 or 39 is reduced in a region of the upper interlayer
insulating film 23 or 38 between the upper ends of the metal
interconnects 21 or 37.
[0030] Accordingly, in the first or second conventional example,
since the volume of each air gap 24 or 39 is thus reduced in the
region between the upper ends of the metal interconnects 21 or 37
where the electric field is collected, the capacitance between the
interconnects cannot be sufficiently reduced. In other words,
although the first or second conventional example employs the metal
interconnect structure having an air gap and the portions of the
lower interlayer insulating film 11 or 31 between the metal
interconnects 21 37 are trenched before forming the upper
interlayer insulating film 23 or 38 so as to reduce the capacitance
between the interconnects, the capacitance between the
interconnects cannot be sufficiently reduced by these conventional
techniques.
SUMMARY OF THE INVENTION
[0031] In consideration of the aforementioned conventional problem,
an object of the invention is definitely reducing capacitance
between interconnects in a semiconductor device having a metal
interconnect structure including an air gap.
[0032] In order to achieve the object, the semiconductor device of
this invention comprises a plurality of metal interconnects formed
on a lower interlayer insulating film provided on a semiconductor
substrate; and an upper interlayer insulating film covering the
plurality of metal interconnects and having an air gap between the
plurality of metal interconnects, and a top portion of the air gap
is positioned at a level higher than the plurality of metal
interconnects.
[0033] In the semiconductor device of this invention, since the top
portion of the air gap is positioned at a level higher than the
metal interconnects, a main portion of the air gap, namely, a
portion with a rectangular cross-section, is positioned at the same
level as the metal interconnects. Therefore, the volume of the air
gap in a region between the upper ends of the metal interconnects
where an electric field is collected can be increased, so as to
sufficiently reduce the capacitance between the interconnects. As a
result, the performance and the reliability of the semiconductor
device can be improved.
[0034] In the semiconductor device, it is preferred that portions
of the lower interlayer insulating film between the plurality of
metal interconnects are trenched by etching, that a second
insulating film made from a different material from the lower
interlayer insulating film is formed on the plurality of metal
interconnects with a first insulating film sandwiched therebetween,
and that the lower interlayer insulating film has an etching rate
higher than an etching rate of the second insulating film in the
etching of the lower interlayer insulating film.
[0035] Since the portions of the lower interlayer insulating film
between the plural metal interconnects are thus trenched by the
etching, the lower end of the air gap is positioned at a level
lower than the lower ends of the metal interconnects, and hence,
the volume of the air gap in a region between the lower ends of the
metal interconnects where an electric field is collected can be
increased. Therefore, the capacitance between the interconnects can
be further reduced.
[0036] Furthermore, since the second insulating film made from a
different material from the lower interlayer insulating film and
having an etching rate lower than that of the lower interlayer
insulating film in etching the lower interlayer insulating film is
formed on the plural metal interconnects with the first insulating
film sandwiched therebetween, no facet is formed in a top portion
of the first insulating film when the lower interlayer insulating
film is etched. Therefore, the upper interlayer insulating film
minimally enters the portions between the metal interconnects, and
hence, the top portion of the air gap can be definitely positioned
at a level higher than the metal interconnects.
[0037] In the semiconductor device, it is preferred that the lower
interlayer insulating film is made from an inorganic insulating
material including an inorganic component as a principal
constituent and including neither nitrogen nor carbon, or a hybrid
insulating material including an organic component and an inorganic
component, and that the second insulating film is made from an
inorganic insulating material including an inorganic material as a
principal constituent and including nitrogen or carbon.
[0038] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that of the second insulating film in
etching the lower interlayer insulating film.
[0039] In the semiconductor device, it is preferred that the lower
interlayer insulating film is made from an organic insulating
material including an organic component as a principal constituent,
and that the second insulating film is made from an inorganic
insulating material including an inorganic component as a principal
constituent or a hybrid insulating material including an organic
component and an inorganic component.
[0040] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that the second insulating film in
etching the lower interlayer insulating film.
[0041] In the semiconductor device, it is preferred that the lower
interlayer insulating film is made from an inorganic or organic
porous insulating material, and that the second insulating film is
made from an inorganic insulating material including an inorganic
component as a principal constituent or a hybrid insulating
material including an organic component and an inorganic
component.
[0042] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that of the second insulating film in
etching the lower interlayer insulating film.
[0043] The first method for fabricating a semiconductor device of
this invention comprises the steps of depositing a first metal film
on a lower interlayer insulating film formed on a semiconductor
substrate; forming a second insulating film made from a different
material from the lower interlayer insulating film on the first
metal film with a first insulating film sandwiched therebetween;
forming a contact plug opening in the second insulating film and
the first insulating film; forming a contact plug by filling the
contact plug opening with a second metal film; forming a transfer
pattern composed of a patterned second insulating film, a patterned
first insulating film and the contact plug by etching the second
insulating film and the first insulating film with a mask pattern
formed on the second insulating film in an interconnect pattern
used as a mask; forming metal interconnects from the first metal
film by etching the first metal film with the transfer pattern used
as a mask; trenching portions of the lower interlayer insulating
film between the metal interconnects by etching the lower
interlayer insulating film under conditions in which the lower
interlayer insulating film has an etching rate higher than an
etching rate of the second insulating film; and forming an upper
interlayer insulating film on the lower interlayer insulating film,
whereby covering the patterned second insulating film and forming
an air gap between the metal interconnects.
[0044] In the first method for fabricating a semiconductor device
of this invention, the lower interlayer insulating film is etched
under conditions in which the etching rate of the lower interlayer
insulating film is higher than that of the second insulating film
so as to trench the portions of the lower interlayer insulating
film between the metal interconnects. Therefore, no facet is formed
in a top portion of the first insulating film, and hence, the upper
interlayer insulating film minimally enters the portion between the
metal interconnects. Accordingly, the top portion of the air gap
can be positioned at a level higher than the metal interconnects so
as to increase the volume of the air gap in a region between the
upper ends of the metal interconnects where an electric field is
collected. As a result, the capacitance between the interconnects
can be sufficiently reduced.
[0045] The second method for fabricating a semiconductor device of
this invention comprises the steps of depositing a first metal film
on a lower interlayer insulating film formed on a semiconductor
substrate; forming a second insulating film from a different
material from the lower interlayer insulating film on the first
metal film with a first insulating film sandwiched therebetween;
forming a transfer pattern composed of a patterned second
insulating film and a patterned first insulating film by etching
the second insulating film and the first insulating film with a
mask pattern formed on the second insulating film in an
interconnect pattern used as a mask; forming metal interconnects
from the first metal film by etching the first metal film with the
transfer pattern used as a mask; trenching portions of the lower
interlayer insulating film between the metal interconnects by
etching the lower interlayer insulating film under conditions in
which the lower interlayer insulating film has an etching rate
higher than an etching rate of the second insulating film; and
forming an upper interlayer insulating film on the lower interlayer
insulating film, whereby covering the patterned second insulating
film and forming an air gap between the metal interconnects.
[0046] In the second method for fabricating a semiconductor device
of this invention, the lower interlayer insulating film is etched
under conditions in which the etching rate of the lower interlayer
insulating film is higher than that of the second insulating film
so as to trench the portions of the lower interlayer insulating
film between the metal interconnects. Therefore, no facet is formed
in a top portion of the first insulating film, and hence, the upper
interlayer insulating film minimally enters the portion between the
metal interconnects. Accordingly, the top portion of the air gap
can be positioned at a level higher than the metal interconnects so
as to increase the volume of the air gap in a region between the
upper ends of the metal interconnects where an electric field is
collected. As a result, the capacitance between the interconnects
can be sufficiently reduced.
[0047] In the first or second method for fabricating a
semiconductor device, it is preferred that a top portion of the air
gap is positioned at a level higher than the metal
interconnects.
[0048] Thus, the volume of the air gap in the region between the
upper ends of the metal interconnects where an electric field is
collected can be definitely increased, resulting in definitely
reducing the capacitance between the interconnects.
[0049] In the first or second method for fabricating a
semiconductor device, it is preferred that the lower interlayer
insulating film is made from an inorganic insulating material
including an inorganic component as a principal constituent and
including neither nitrogen nor carbon, or a hybrid insulating
material including an organic component and an inorganic component,
and that the second insulating film is made from an inorganic
insulating material including an inorganic material as a principal
constituent and including nitrogen or carbon.
[0050] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that of the second insulating film in
etching the lower interlayer insulating film.
[0051] In the first or second method for fabricating a
semiconductor device, it is preferred that the lower interlayer
insulating film is made from an organic insulating material
including an organic component as a principal constituent, and that
the second insulating film is made from an inorganic insulating
material including an inorganic component as a principal
constituent or a hybrid insulating material including an organic
component and an inorganic component.
[0052] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that of the second insulating film in
etching the lower interlayer insulating film.
[0053] In the first or second method for fabricating a
semiconductor device, it is preferred that the lower interlayer
insulating film is made from an inorganic or organic porous
insulating material, and that the second insulating film is made
from an inorganic insulating material including an inorganic
component as a principal constituent or a hybrid insulating
material including an organic component and an inorganic
component.
[0054] Thus, the lower interlayer insulating film can easily attain
an etching rate higher than that of the second insulating film in
etching the lower interlayer insulating film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0055] FIGS. 1A, 1B and 1C are cross-sectional views for showing
procedures in a method for fabricating a semiconductor device
according to Embodiment 1 of the invention;
[0056] FIGS. 2A, 2B and 2C are cross-sectional views for showing
other procedures in the method for fabricating a semiconductor
device of Embodiment 1;
[0057] FIGS. 3A, 3B and 3C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of Embodiment 1;
[0058] FIGS. 4A, 4B and 4C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of Embodiment 1;
[0059] FIGS. 5A, 5B and 5C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of Embodiment 1;
[0060] FIG. 6A is a cross-sectional view of a semiconductor device
according to a first or second conventional example and FIG. 6B is
a cross-sectional view of a semiconductor device of Embodiment
1;
[0061] FIGS. 7A, 7B and 7C are cross-sectional views for showing
procedures in a method for fabricating a semiconductor device
according to Embodiment 2 of the invention;
[0062] FIGS. 8A, 8B and 8C are cross-sectional views for showing
other procedures in the method for fabricating a semiconductor
device of Embodiment 2;
[0063] FIGS. 9A, 9B and 9C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of Embodiment 2;
[0064] FIGS. 10A, 10B and 10C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of Embodiment 2;
[0065] FIGS. 11A, 11B and 11C are cross-sectional views for showing
procedures in a method for fabricating a semiconductor device
according to the first conventional example;
[0066] FIGS. 12A, 12B and 12C are cross-sectional views for showing
other procedures in the method for fabricating a semiconductor
device of the first conventional example;
[0067] FIGS. 13A, 13B and 13C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of first conventional example;
[0068] FIGS. 14A, 14B and 14C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of the first conventional example;
[0069] FIGS. 15A, 15B and 15C are cross-sectional views for showing
procedures in a method for fabricating a semiconductor device
according the second conventional example;
[0070] FIGS. 16A, 16B and 16C are cross-sectional views for showing
other procedures in the method for fabricating a semiconductor
device of the second conventional example;
[0071] FIGS. 17A, 17B and 17C are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of the second conventional example; and
[0072] FIGS. 18A and 18B are cross-sectional views for showing
still other procedures in the method for fabricating a
semiconductor device of the second conventional example.
DETAILED DESCRIPTION OF THE INVENTION
[0073] Embodiment 1
[0074] A semiconductor device and a method for fabricating the same
according to Embodiment 1 of the invention will now be described
with reference to FIGS. 1A through 1C, 2A through 2C, 3A through
3C, 4A through 4C and 5A through 5C.
[0075] First, as shown in FIG. 1A, a lower interlayer insulating
film 101 of an insulating material is formed on a semiconductor
substrate 100 by CVD or spin coating. Thereafter, although not
shown in the drawing, a plug connected to the semiconductor
substrate 100 or an interconnect formed on the semiconductor
substrate 100 is formed in the lower interlayer insulating film
101.
[0076] Next, a first barrier metal layer 102, a first metal film
103 and a second barrier metal layer 104 are successively deposited
on the lower interlayer insulating film 101. The first barrier
metal layer 102 and the second barrier metal layer 104 are
deposited by sputtering and the first metal film 103 is formed by
the sputtering, CVD or plating. The first metal film 103 may be
made from a metal with low resistance such as aluminum alloy,
copper, gold, silver or platinum, and the first barrier metal layer
102 and the second barrier metal layer 104 may be made from a
nitride of a metal with a high melting point such as titanium
nitride or tantalum nitride.
[0077] Then, as shown in FIG. 1B, a first insulating film 105, a
second insulating film 106 and a third insulating film 107 are
successively formed on the second barrier metal layer 104 by the
CVD or spin coating. In this case, the second insulating film 106
is made from a different material from the first insulating film
105, and the third insulating film 107 is made from a different
material from the second insulating film 106. Also, the second
insulating film 106 is made from an insulating material having a
lower etching rate S than the lower interlayer insulating film 101
in etching the lower interlayer insulating film 101. The insulating
materials used for the lower interlayer insulating film 101, the
first insulating film 105, the second insulating film 106 and the
third insulating film 107 will be described in detail later.
[0078] Next, after forming a first resist pattern 108 on the third
insulating film 107 by lithography as shown in FIG. 1C, the third
insulating film 107, the second insulating film 106 and the first
insulating film 105 are dry etched by using the first resist
pattern 108 as a mask, thereby forming plug openings 109 as shown
in FIG. 2A.
[0079] Then, after depositing a second metal film 110 on the third
insulating film 107 by the sputtering, CVD or plating as shown in
FIG. 2B, an unnecessary portion of the second metal film 110
present on the third insulating film 107 is removed by CMP, thereby
forming contact plugs 111 from the second metal film 110 as shown
in FIG. 2C.
[0080] Next, after forming a second resist pattern 112 on the third
insulating film 107 as shown in FIG. 3A, the third insulating film
107 is dry etched by using the second resist pattern 112 as a mask,
so as to form a patterned third insulating film 107A in the pattern
of interconnects as shown in FIG. 3B.
[0081] Then, as shown in FIG. 3C, the second insulating film 106 is
dry etched by using the second resist pattern 112 and the patterned
third insulating film 107A as a mask, so as to form a patterned
second insulating film 106A in the pattern of interconnects.
[0082] Subsequently, as shown in FIG. 4A, the first insulating film
105 is dry etched by using the second resist pattern 112, the
patterned third insulating film 107A and the patterned second
insulating film 106A as a mask, so as to form a patterned first
insulating film 105A in the pattern of interconnects. In this
manner, a transfer pattern composed of the patterned third
insulating film 107A, the patterned second insulating film 106A,
the patterned first insulating film 105A and the contact plugs 111
is formed. Thereafter, the second resist pattern 112 is removed by
ashing as shown in FIG. 4B, and the resultant semiconductor
substrate is cleaned.
[0083] Next, as shown in FIG. 4C, the second barrier metal layer
104, the first metal film 103 and the first barrier metal layer 102
are dry etched by using the transfer pattern as a mask, thereby
forming metal interconnects 113 composed of a patterned second
barrier metal layer 104A, a patterned first metal film 103A and a
patterned first barrier metal layer 102A. In this manner, the
patterned third insulating film 107A is sputtered, and hence is
formed into a third insulating film 107B having facets in top
portions thereof.
[0084] Then, as shown in FIG. 5A, the lower interlayer insulating
film 101 is dry etched under conditions in which the etching rate
of the lower interlayer insulating film 101 is higher than the
etching rate of the second insulating film 106, thereby trenching
portions of the lower interlayer insulating film 101 between the
metal interconnects 113. In this etching, although the third
insulating film 107B having the facets in the top portions thereof
is removed, the patterned second insulating film 106A and the
patterned first insulating film 105A still have a rectangular
cross-section. In other words, no facets are formed in the top
portions of the patterned second insulating film 106A and the
patterned first insulating film 105A. In this etching, even when
the third insulating film 107B having the facets in the top
portions thereof is not completely removed, it is harmless.
[0085] Next, as shown in FIG. 5B, an upper interlayer insulating
film 114 is formed over the patterned second insulating film 106A,
the contact plugs 111 and the lower interlayer insulating film 101
by the CVD, and air gaps 115 are formed in the upper interlayer
insulating film 114 between the metal interconnects 113. Since this
procedure for forming the upper interlayer insulating film 114 is
carried out with no facets formed in the top portions of the
patterned second insulating film 106A and the patterned first
insulating film 105A, the upper interlayer insulating film 114
minimally enters the portions between the metal interconnects 113.
Therefore, the top portion of each air gap 115 (a portion with a
triangular cross-section) is positioned at a level higher than the
metal interconnect 113.
[0086] Then, as shown in FIG. 5C, the upper interlayer insulating
film 114 is planarized by the CMP. Thus, an interconnect structure
having an air gap is obtained. Thereafter, the aforementioned
sequence is repeated, so as to fabricate a semiconductor device
having a multi-layer interconnect structure.
[0087] FIG. 6A shows the cross-sectional structure of a
semiconductor device according to the first or second conventional
example and FIG. 6B shows the cross-sectional structure of the
semiconductor device of Embodiment 1.
[0088] As is obvious from FIG. 6A, since the patterned insulating
film 15A (35A) has the facets in the top portions thereof in the
semiconductor device of the first or second conventional example,
the upper interlayer insulating film 22 (38) tends to enter the
portions between the metal interconnects 21 (37). Therefore, the
height h.sub.1 of each air gap 23 (39) composed of a main portion
23a (39a) (with a rectangular cross-section) and a top portion 23b
(39b) (with a triangular cross-section) is merely slightly larger
than the height h.sub.0 of the metal interconnect 21 (37) above the
bottom of the air gap. Accordingly, the top portion 23b (39b) of
the air gap 23 (39) is positioned at substantially the same level
as the metal interconnect 21 (39).
[0089] In contrast, as is obvious from FIG. 6B, since no facets are
formed in the top portions of the patterned second insulating film
106A and the patterned first insulating film 105A in the
semiconductor device of Embodiment 1, the upper interlayer
insulating film 114 minimally enters the portions between the metal
interconnects 113. Therefore, the height h.sub.2 of each air gap
115 composed of a main portion 115a (with a rectangular
cross-section) and a top portion 115b (with a triangular
cross-section) is much larger than the height h.sub.0 of the metal
interconnect 113 above the bottom of the air gap. Accordingly, the
top portion 115b of the air gap 115 is positioned at a level higher
than the metal interconnect 113.
[0090] According to Embodiment 1, since the top portion 115b of
each air gap 115 is positioned at the level higher than the metal
interconnect 113, the volume of the air gap 115 in a region between
the upper ends of the metal interconnects 113 where an electric
field is collected can be increased. As a result, the capacitance
between the interconnects can be sufficiently reduced, so as to
improve the performance and the reliability of the semiconductor
device.
[0091] Embodiment 2
[0092] A semiconductor device and a method for fabricating the same
according to Embodiment 2 of the invention will now be described
with reference to FIGS. 7A through 7C, 8A through 8C, 9A through 9C
and 10A through 10C.
[0093] First, as shown in FIG. 7A, a lower interlayer insulating
film 201 of an insulating material is formed on a semiconductor
substrate 200 by the CVD or spin coating in the same manner as in
Embodiment 1. Thereafter, although not shown in the drawing, a plug
connected to the semiconductor substrate 200 or an interconnect
formed on the semiconductor substrate 200 is formed in the lower
interlayer insulating film 201. Then, a first barrier metal layer
202, a first metal film 203 and a second barrier metal layer 204
are successively deposited on the lower interlayer insulating film
201.
[0094] Next, as shown in FIG. 7B, a first insulating film 205 and a
second insulating film 206 are successively formed on the second
barrier metal layer 204 by the CVD or spin coating. In this case,
the second insulating film 206 is made from a different material
from the first insulating film 205. Also, the second insulating
film 206 is made from an insulating material having a lower etching
rate than the lower interlayer insulating film 201 in etching the
lower interlayer insulating film 201. The insulating materials used
for the lower interlayer insulating film 201, the first insulating
film 205 and the second insulating film 206 will be described in
detail later.
[0095] Then, after forming a first resist pattern 207 on the second
insulating film 206 as shown in FIG. 7C, the second insulating film
206 and the first insulating film 205 are dry etched by using the
first resist pattern 207 as a mask, thereby forming a patterned
second insulating film 206A and a patterned first insulating film
205A both in the pattern of interconnects as shown in FIG. 8A.
Thus, a transfer pattern composed of the patterned second
insulating film 206A and the patterned first insulating film 205A
is formed. Thereafter, the first resist pattern 207 is removed by
the ashing, and the resultant substrate is cleaned.
[0096] Next, as shown in FIG. 8B, the second barrier metal layer
204, the first metal film 203 and the first barrier metal layer 202
are dry etched by using the transfer pattern as a mask, thereby
forming metal interconnects 208 composed of a patterned second
barrier metal layer 204A, a patterned first metal film 203A and a
patterned first barrier metal layer 202A.
[0097] Then, as shown in FIG. 8C, the lower interlayer insulating
film 201 is dry etched under conditions in which the etching rate
of the lower interlayer insulating film 201 is higher than the
etching rate of the second insulating film 206, thereby trenching
portions of the lower interlayer insulating film 201 between the
metal interconnects 208. In this etching, the patterned second
insulating film 206A and the patterned first insulating film 205A
keep their rectangular cross-section, namely, no facets are formed
in top portions of the patterned second insulating film 206A and
the patterned first insulating film 205A.
[0098] Subsequently, as shown in FIG. 9A, an upper interlayer
insulating film 209 is formed over the metal interconnects 208 and
the lower interlayer insulating film 201 by the CVD, and air gaps
210 are formed in the upper interlayer insulating film 209 between
the metal interconnects 208. The procedure for forming the upper
interlayer insulating film 209 is carried out with no facets formed
in the top portions of the patterned second insulating film 206A
and the patterned first insulating film 205A. Therefore, the upper
interlayer insulating film 209 minimally enters the portions
between the metal interconnects 208, and hence, a top portion of
each air gap 210 (a portion with a triangular cross-section) is
positioned at a level higher than the metal interconnect 208.
[0099] Next, after planarizing the upper interlayer insulating film
209 by the CMP as shown in FIG. 9B, a second resist pattern 211 is
formed on the upper interlayer insulating film 209 as shown in FIG.
9C.
[0100] Then, as shown in FIG. 10A, the upper interlayer insulating
film 209 is dry etched by using the second resist pattern 211 as a
mask, thereby forming plug openings 212 in the upper interlayer
insulating film 209. Thereafter, the second resist pattern 211 is
removed by the ashing.
[0101] Next, as shown in FIG. 10B, a second metal film 213 is
deposited on the upper interlayer insulating film 209 by the
sputtering, CVD or plating so as to fill the plug openings 212.
[0102] Then, as shown in FIG. 10C, an unnecessary portion of the
second metal film 213 present on the upper interlayer insulating
film 209 is removed by the CMP, so as to form contact plugs 214
from the second metal film. Thus, an interconnect structure having
an air gap is completed. When the aforementioned sequence is
repeated, a semiconductor device having a multi-layer interconnect
structure can be fabricated.
[0103] Since the top portion of each air gap 210 is positioned at
the level higher than the metal interconnects 208 in Embodiment 2,
the volume of the air gap in a region between the upper ends of the
metal interconnects 208 where an electric field is collected can be
increased. Therefore, the capacitance between the interconnects can
be sufficiently reduced, resulting in improving the performance and
the reliability of the semiconductor device. (Insulating materials
used for lower and upper interlayer insulating films and first,
second and third insulating films)
[0104] Combinations of insulating materials used for the lower
interlayer insulating film 101 (201), the upper interlayer
insulating film 114 (209), the first insulating film 105 (205), the
second insulating film 106 (206) of Embodiments 1 and 2 and the
third insulating film 107 of Embodiment 1 will now be specifically
described. The following description is applicable to both
Embodiments 1 and 2 unless otherwise mentioned.
[0105] First combination
[0106] In a first combination, the lower interlayer insulating film
is made from an inorganic insulating material including an
inorganic component as a principal constituent and including
neither nitrogen nor carbon, or a hybrid insulating material
including an organic component and an inorganic component; and the
second insulating film is made from an inorganic insulating
material including an inorganic component as a principal
constituent and including nitrogen or carbon.
[0107] Examples of the lower interlayer insulating film are an
inorganic insulating film such as a silicon oxide film or a silicon
oxide fluorinated film, and a hybrid insulating film such as a
silicon oxide film including a hydrogen atom or a hydrocarbon
compound like a methyl group. In this case, the upper interlayer
insulating film is also made from an inorganic insulating film such
as a silicon oxide film or a silicon oxide fluorinated film, or a
hybrid insulating film such as a silicon oxide film including a
hydrogen atom or a hydrocarbon compound like a methyl group.
[0108] An example of the second insulating film is an inorganic
insulating film including nitrogen or carbon, such as a silicon
nitride film, a silicon oxide nitrided film, a silicon carbide film
or a silicon oxide carbonated film.
[0109] When this combination is employed, the etching resistance of
the second insulating film can be increased in the dry etching of
the lower interlayer insulating film, and hence, the lower
interlayer insulating film can easily attain an etching rate higher
than that of the second insulating film.
[0110] Examples of the first insulating film are a silicon oxide
film, a silicon oxide fluorinated film, a silicon oxide film
including a hydrogen atom or a hydrocarbon compound like a methyl
group, and what is called a low-k film including an organic
component as a principal constituent.
[0111] Also, examples of the third insulating film of Embodiment 1
are a silicon oxide film, a silicon oxide fluorinated film, a
silicon oxide film including a hydrogen atom or a hydrocarbon
compound like a methyl group, and what is called a low-k film
including an organic component as a principal constituent.
[0112] Second combination
[0113] In a second combination, the lower interlayer insulating
film is made from an organic insulating material including an
organic component as a principal constituent; and the second
insulating film is made from an inorganic insulating material
including an inorganic component as a principal constituent or a
hybrid insulating material including an organic component and an
inorganic component.
[0114] An example of the lower interlayer insulating film is an
organic film of an organic polymer such as an aromatic polymer. In
this case, the upper interlayer insulating film may be made from an
organic film, an inorganic film or a hybrid film. When the upper
interlayer insulating film is made from an organic film, a
multi-layer interconnect structure including a plurality of
interconnect structures described in Embodiment 1 or 2 can be
realized. When the upper interlayer insulating film is made from an
inorganic film or a hybrid film, the film structure can be
optimized in each layer divided by interlayer insulating films.
[0115] Examples of the second insulating film are an inorganic
insulating film such as a silicon oxide film, a silicon oxide
fluorinated film, a silicon nitride film, a silicon oxide nitrided
film, a silicon carbide film or a silicon oxide carbonated film,
and a hybrid insulating film such as a silicon oxide film including
a hydrogen atom or a hydrocarbon compound like a methyl group.
[0116] When this combination is employed, the etching resistance of
the second insulating film can be increased in the dry etching of
the lower interlayer insulating film. Therefore, the lower
interlayer insulating film can easily attain an etching rate higher
than that of the second insulating film.
[0117] Furthermore, the interlayer insulating film can attain a
lower dielectric constant than in the first combination, and hence,
a higher performance multi-layer interconnect structure with low
capacitance can be realized.
[0118] Examples of the first insulating film are a silicon oxide
film, a silicon oxide fluorinated film, a silicon oxide film
including a hydrogen atom or a hydrocarbon compound like a methyl
group, what is called a low-k film including an organic component
as a principal constituent, and what is called a porous film having
fine pores.
[0119] Examples of the third insulating film of Embodiment 1 are a
silicon oxide film, a silicon oxide fluorinated film, a silicon
oxide film including a hydrogen atom or a hydrocarbon compound like
a methyl group, what is called a low-k film including an organic
component as a principal constituent, and what is called a porous
film having fine pores.
[0120] Third combination
[0121] In a third combination, the lower interlayer insulating film
is made from an inorganic or organic porous insulating material;
and the second insulating film is made from an inorganic insulating
material including an inorganic component as a principal
constituent, or a hybrid insulating material including an organic
component and an inorganic component.
[0122] An example of the lower interlayer insulating film is an
inorganic or organic porous film having fine pores.
[0123] Examples of the second insulating film are an inorganic
insulating film such as a silicon oxide film, a silicon oxide
fluorinated film, a silicon nitride film, a silicon oxide nitrided
film, a silicon carbide film or a silicon oxide carbonated film,
and a hybrid insulating film such as a silicon oxide film including
a hydrogen atom or a hydrocarbon compound like a methyl group.
[0124] When this combination is employed, the etching resistance of
the second insulating film can be increased in the dry etching of
the lower interlayer insulating film. Therefore, the lower
interlayer insulating film can easily attain an etching rate higher
than that of the second insulating film.
[0125] Furthermore, the interlayer insulating film can attain a
lower dielectric constant than in the first and second
combinations, and hence, a much higher performance multilayer
interconnect structure with low capacitance can be realized.
[0126] Examples of the first insulating film are a silicon oxide
film, a silicon oxide fluorinated film, a silicon oxide film
including a hydrogen atom or a hydrocarbon compound like a methyl
group, what is called a low-k film including an organic component
as a principal constituent, and what is called a porous film having
fine pores.
[0127] Examples of the third insulating film of Embodiment 1 are a
silicon oxide film, a silicon oxide fluorinated film, a silicon
oxide film including a hydrogen atom or a hydrocarbon compound like
a methyl group, what is called a low-k film including an organic
component as a principal constituent, and what is called a porous
film having fine pores.
* * * * *