U.S. patent application number 09/988962 was filed with the patent office on 2002-05-23 for thin film transistor having high mobility and high on-current and method for manufacturing the same.
Invention is credited to Haga, Hiroshi, Tanabe, Hiroshi.
Application Number | 20020060322 09/988962 |
Document ID | / |
Family ID | 18825852 |
Filed Date | 2002-05-23 |
United States Patent
Application |
20020060322 |
Kind Code |
A1 |
Tanabe, Hiroshi ; et
al. |
May 23, 2002 |
Thin film transistor having high mobility and high on-current and
method for manufacturing the same
Abstract
In a thin film transistor (TFT) including an insulating
substrate and a polycrystalline silicon island formed on the
insulating layer, a grain size of the polycrystalline silicon
island is elongated along one direction. A source region, a channel
region and a drain region are arranged in the polycrystalline
silicon island in parallel with the direction.
Inventors: |
Tanabe, Hiroshi; (Tokyo,
JP) ; Haga, Hiroshi; (Tokyo, JP) |
Correspondence
Address: |
ROSENMAN & COLIN LLP
575 MADISON AVENUE
NEW YORK
NY
10022-2585
US
|
Family ID: |
18825852 |
Appl. No.: |
09/988962 |
Filed: |
November 19, 2001 |
Current U.S.
Class: |
257/66 ; 257/347;
257/E21.413; 257/E29.151; 257/E29.293 |
Current CPC
Class: |
H01L 27/1285 20130101;
H01L 27/14643 20130101; H01L 27/1214 20130101; H01L 29/78675
20130101; H01L 29/66757 20130101; H01L 29/4908 20130101 |
Class at
Publication: |
257/66 ;
257/347 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 20, 2000 |
JP |
2000-353031 |
Claims
1. A thin film transistor comprising: an insulating substrate; a
polycrystalline silicon island formed on said insulating layer, a
grain size of said polycrystalline silicon island being elongated
along one direction; and a source region, a channel region and a
drain region arranged in said polycrystalline silicon island in
parallel with said direction.
2. The thin film transistor as set forth in claim 1, wherein said
insulating substrate comprises a glass substrate.
3. A method for manufacturing a thin film transistor, comprising
the steps of: forming an amorphous silicon layer on an insulating
substrate; irradiating said amorphous silicon layer with a laser
line beam along a first direction, so that a portion of said
amorphous silicon layer irradiated with said laser line beam is
converted into a polycrystalline silicon layer; patterning said
polycrystalline silicon layer into a polycrystalline silicon
island; and forming a source region, a channel region and a drain
region of said thin film transistor in said polycrystalline silicon
island.
4. The method as set forth in claim 3, wherein said source region,
said channel region and said drain region of said thin film
transistor are arranged along a second direction perpendicular to
said first direction.
5. The method as set forth in claim 3, wherein said laser line beam
irradiating step irradiates said amorphous silicon layer with said
laser line beam, so that polycrystalline silicon is grown from
portions of said amorphous silicon layer close to edges of said
laser line beam to a portion of said amorphous silicon layer close
to a center of said laser line beam. said polycrystalline silicon
layer being divided into two regions at a line corresponding to the
center of said laser line beam.
6. The method as set forth in claim 5, wherein said polycrystalline
silicon island is located within either of the two regions of said
polycrystalline silicon layer.
7. The method as set forth in claim 3, wherein said insulating
substrate comprises a glass substrate.
8. A method for manufacturing a thin film transistor, comprising
the steps of: forming an amorphous silicon layer on an insulating
substrate; irradiating said amorphous silicon layer with a laser
line beam along a first direction, so that polycrystalline silicon
is grown from portions of said amorphous silicon layer close to
edges of said laser line beam to a portion of said amorphous
silicon layer close to a center of said laser line beam, thus
forming a polycrystalline silicon layer divided into two regions at
a line corresponding to the center of said laser line beam;
patterning said polycrystalline silicon layer into a
polycrystalline silicon island; and forming a source region, a
channel region and a drain region of thin film transistor in either
of the two regions of said polycrystalline silicon island along a
second direction perpendicular to said first direction.
9. The method as set forth in claim 8, wherein said insulating
substrate comprises a glass substrate.
10. A method for manufacturing a P-channel type thin film
transistor and an N-channel type, comprising the steps of: forming
an amorphous silicon layer on an insulating substrate; irradiating
said amorphous silicon layer with a plurality of laser line beams
along first direction, so that portions of said amorphous silicon
layer irradiated with said laser line beams are converted into a
plurality of polycrystalline silicon layers; patterning each of
said polycrystalline silicon layers into a plurality of
polycrystalline silicon islands; and forming a source region, a
channel region and a drain region of said P-channel type thin film
transistor in one of said polycrystalline silicon islands of one of
said polycrystalline silicon layers and a source region, a channel
region and a drain region of said N-channel thin film transistor in
one of said polycrystalline silicon islands of the other of said
polycrystalline silicon layers.
11. The method as set forth in claim 10, wherein said source
region, said channel region and said drain region of said P-channel
type thin film transistor said source region, said channel region
and said drain region of said N-channel thin film transistor are
arranged along a second direction perpendicular to said first
direction.
12. The method as set forth in claim 10, wherein said laser line
beam irradiating step irradiates said amorphous silicon layer with
said laser line beams, so that polycrystalline silicon is grown
from portions of said amorphous silicon layer close to edges of
each of said laser line beams to portions of said amorphous silicon
layers close to centers of each of said laser line beams. each of
said polycrystalline silicon layers being divided into two regions
at a line corresponding to the centers of said laser line
beams.
13. The method as set forth in claim 12, wherein each of said
polycrystalline silicon islands is located within either of the two
regions of one of said polycrystalline silicon layers.
14. The method as set forth in claim 10, wherein said insulating
substrate comprises a glass substrate.
15. A method for manufacturing a P-channel thin film transistor and
an N-channel thin film transistor, comprising the steps of: forming
an amorphous silicon layer on an insulating substrate; irradiating
said amorphous silicon layer with a plurality of laser line beams
along a first direction, so that polycrystalline silicon is grown
from portions of said amorphous silicon layer close to edges of
each of said laser line beams to portions of said amorphous silicon
layer close to a center of each of said laser line beams, thus
forming a plurality of polycrystalline silicon layers each divided
into two regions at a line corresponding to the center of each of
said laser line beams; patterning either of the two regions of each
of said polycrystalline silicon layers into a plurality of
polycrystalline silicon islands and forming a source region, a
channel region and a drain region of said P-channel type thin film
transistor in either of the two regions of one of said
polycrystalline silicon islands belonging to one of said
polycrystalline silicon layers and a source region, a channel
region and a drain region of said N-channel thin film transistor in
either of the two regions of one of said polycrystalline silicon
islands belonging to the other of said polycrystalline silicon
layers along a second direction perpendicular to said first
direction.
16. The method as set forth in claim 15, wherein said insulating
substrate comprises a glass substrate.
17. An image input apparatus comprising: an insulating substrate; a
plurality of polycrystalline silicon islands formed on said
insulating substrate; a plurality of pixels each including thin
film transistors and a photodiode formed above said thin film
transistors, each of said thin film transistors having a source
region, a channel region and a drain region formed in one of said
polycrystalline silicon islands.
18. The apparatus as set forth in claim 17, wherein a grain size of
said polycrystalline silicon islands is elongated along one
direction, said source region, said channel region and said drain
region of each of said film transistors being in parallel with said
direction.
19. The apparatus as set forth in claim 17, wherein said insulating
substrate comprises a glass substrate.
20. The apparatus as set forth in claim 17, further comprising: an
additional photodiode, formed on said insulating substrate and
surrounding all of said pixels, for detecting whether or not light
is incident to all of said pixels; and a reset circuit, connected
between said additional photodiode and all of said pixels, for
generating a reset signal when said additional photodiode detects
that light is incident to all of said pixels, so that said
photodiode of each of said pixels is reset by said reset
signal.
21. The apparatus as set forth in claim 17, wherein said photodiode
comprises a Schottky barrier diode.
22. The apparatus as set forth in claim 17, wherein said photodiode
comprises a PIN diode.
23. The apparatus as set forth in claim 20, wherein said additional
photodiode comprises a Schottky barrier diode.
24. The apparatus as set forth in claim 20, wherein said additional
photodiode comprises a PIN diode.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a thin film transistor
(TFT), a method for manufacturing the TFT, and apparatuses using
the TFT.
[0003] 2. Description of the Related Art
[0004] Generally, TFTs are manufactured on an insulating substrate
by using a hydrogen-passivated amorphous silicon technology and a
polycrystalline silicon technology.
[0005] According to the hydrogen-passivated amorphous silicon
technology, since the maximum temperature during the manufacturing
steps thereof is low, i.e., about 300.degree. C., the mobility of
carriers is low,i.e., about 1 cm.sup.2/V sec. Also, an insulating
substrate can be a glass substrate having a low melting
temperature, which would decrease the manufacturing cost.
[0006] However, in an active matrix-type liquid crystal display
(LCD) apparatus manufactured by the hydrogen-passivated amorphous
silicon technology, TFTs manufactured by the hydrogen-passivated
amorphous silicon technology are used as the switching elements of
pixels of a display panel of the LCD apparatus, and the TFTs are
driven by a driver of an integrated circuit apparatus connected to
a periphery of the display panel. As a result, since the display
panel is connected to the driver for driving the display panel by a
tape automated bonding (TAB) process or a wire bonding process, if
the connection pitch between the display panel and the driver
becomes small, it is actually impossible to connect the display
panel to the driver.
[0007] On the other hand, according to the polycrystalline silicon
technology, since the maximum temperature during the manufacturing
steps thereof is high, i.e., about 1000.degree. C., the mobility of
carriers is about 30 to 100 cm.sup.2/V.multidot.sec. For example, a
high temperature annealing process is required to convert amorphous
silicon into polycrystalline silicon. Also, if TFTs manufactured by
the polycrystalline silicon technology are used as the switching
elements of pixels of a display panel of an active matrix-type LCD
apparatus, a driver for driving the display panel can also be
formed on the same substrate of the display panel, so that the
above-mentioned theremocompressing bonding process or wire bonding
process is unnecessary.
[0008] In the polycrystalline silicon technology, since the maximum
temperature is high as stated above, the insulating substrate has
to be a fused quart substrate having a high melting temperature,
for example. This would increase the manufacturing cost.
[0009] In order to decrease the manufacturing cost, i.e., in order
to decrease the temperature for converting amorphous silicon into
polycrystalline silicon to adopt a glass substrate having a low
melting temperature, a laser technology has been combined with the
polycrystalline silicon technology.
[0010] In a prior art method for manufacturing a TFT by the
polycrystalline silicon technology combined with the laser
technology, first, a substrate covering layer made of silicon oxide
is deposited on a glass substrate by a low pressure chemical vapor
deposition (LPCVD) process or the like. Next, an amorphous silicon
(a-Si) layer is deposited on the substrate covering layer by an
LPCVD process or the like. Next, the amorphous silicon layer is
irradiated with a laser beam by moving the glass substrate along
X-and Y-directions. This will be explained later in detail.
[0011] In the above-described prior art method, however, the laser
beam has a rectangular size of several millimeters or several
hundred micrometers. Additionally, the energy of the laser beam is
relatively low, for example, 300 mj/cm.sup.2, and also, the slope
of the energy with respect to the X- or Y-direction is relatively
gentle. As a result, the amorphous silicon layer is converted into
a polycrystalline silicon layer which has a randomly-small grain
size. Thus, since the polycrystalline silicon layer forming a
source region, a channel region and a drain region has a
randomly-small grain size, the mobility of carriers is so low that
the ON-current is low.
SUMMARY OF THE INVENTION
[0012] It is an object of the present invention to provide a TFT
having a high mobility of carriers and a high ON-current and a
method for manufacturing such a TFT.
[0013] Another object is to provide various kinds of apparatuses
using such a TFT.
[0014] According to the present invention, in a TFT including an
insulating substrate and a polycrystalline silicon island formed on
the insulating layer, a grain size of the polycrystalline silicon
island is elongated along one direction. A source region, a channel
region and a drain region are arranged in the polycrystalline
silicon island in parallel with the direction.
[0015] Also, in a method for manufacturing a TFT, an amorphous
silicon layer is formed oh an insulating substrate. Then, the
amorphous silicon layer is irradiated with a laser line beam along
one direction, so that a portion of the amorphous silicon layer
irradiated with the laser line beam is converted into a
polycrystalline silicon layer. Then, the polycrystalline silicon
layer is patterned into a polycrystalline silicon island. Then, a
source region, a channel region and a drain region of the TFT are
formed in the polycrystalline silicon island.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The present invention will be more clearly understood from
the description set forth below, as compared with the prior art,
with reference to the accompanying drawings, wherein:
[0017] FIG. 1 is a cross-sectional views illustrating a prior art
TFT;
[0018] FIG. 2 is a diagram illustrating a pulse laser apparatus for
manufacturing the polycrystalline silicon island of FIG. 1;
[0019] FIGS. 3A and 3B are plan views for explaining a prior art
method for manufacturing the TFT of FIG. 1;
[0020] FIGS. 4A, 5A, 6A, 7A and 8B are cross-sectional views for
explaining an embodiment of the method for manufacturing a TFT
according to the present invention;
[0021] FIGS. 4B, 5B, 6B, 7B and 8B are plan views of the TFT of
FIGS. 4A, 5A, 6A, 7A and 8A, respectively;
[0022] FIG. 9 and 10 are cross-sectional view illustrating
modifications of FIGS. 7A and 8A, respectively;
[0023] FIGS. 11A and 11B are scanning electron microscope (SEM)
photographs showing the polycrystalline silicon layer of FIGS. 5A
and 5B;
[0024] FIG. 12 is a diagram illustrating a digital camera to which
the TFT according to the present invention is applied;
[0025] FIG. 13 is a detailed plan view of the image input unit of
FIG. 12;
[0026] FIG. 14 is a timing diagram for showing the operation of the
image input unit of FIG. 13;
[0027] FIG. 15 is a cross-sectional view of the photodiode and the
reset TFT of FIG. 13;
[0028] FIG. 16 is a circuit diagram illustrating a static random
access memory (SRAM) cell to which the TFT according to the present
invention is applied; and
[0029] FIG. 17A is a diagram illustrating a projector to which the
TFT according to the present invention is applied; and
[0030] FIG. 17B is a circuit diagram of the light valve of FIG.
17A.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0031] Before the description of the preferred embodiment, a prior
art method for manufacturing a TFT will be explained with reference
to FIGS. 1, 2, 3A and 3B.
[0032] In FIG. 1, which illustrates a prior art TFT, reference
numeral 1 designates a glass substrate on which a substrate
covering layer 2 made of silicon oxide is formed. Also, a
polycrystalline silicon island 3' including a source region S, a
channel region C and a drain region D is formed on the substrate
covering layer 2. The polycrystalline silicon island 3' is covered
by gate insulating layers 4-1 and 4-2. Note that the gate
insulating layers 4-1 and 4-2 can be formed by a single layer.
[0033] Additionally, patterned gate electrode layers 5-1 and 5-2
are formed on the gate insulating layers 4-1 and 4-2. The patterned
gate electrode layers 5-1 and 5-2 are covered by a passivation
layer 6. Note that the patterned gate electrode layers 5-1 and 5-2
can be formed by a single layer.
[0034] Further, contact holes are perforated in the gate insulating
layers 4-1 and 4-2 and the passivation layer 6. A metal layer 7 is
buried in the contact holes.
[0035] The polycrystalline silicon island 3' of FIG. 1 is formed by
using a pulse layer irradiation apparatus as illustrated in FIG.
2.
[0036] In FIG. 2, laser beams emitted from a pulse laser source 201
passes through mirrors 202 and 203, a beam homogenizer 204 and a
mirror 205 to reach a target 206. For example, the target 206 is
formed by a glass substrate 2061, a substrate covering layer 2062
and an amorphous silicon layer 2063.
[0037] A prior art method for manufacturing the TFT of FIG. 1 will
be explained next with reference to FIGS. 3A and 3B.
[0038] First, a substrate covering layer 2 made of silicon oxide is
deposited on a glass substrate 1 by a low pressure chemical vapor
deposition (LPCVD) process or the like.
[0039] Next, an amorphous silicon (a-Si) layer is deposited on the
substrate covering layer 2 by an LPCVD process or the like.
[0040] Next, referring to FIG. 3A, the amorphous silicon layer is
irradiated with a laser beam emitted from the pulse laser apparatus
of FIG. 2 by moving the glass substrate 1 along X-and Y-directions.
In this case, the laser beam has a square size of several
millimeters or several hundred micrometers. Additionally, the
energy of the laser beam is relatively low, for example, about 300
to 500 mJ/cm.sup.2, and also, the slope of the energy with respect
to the X- or Y-direction is relatively gentle. As a result, the
amorphous silicon layer is converted into a polycrystalline silicon
layer which has a randomly-small grain size as shown in FIG.
3A.
[0041] Next, referring to FIG. 3B, polycrystalline silicon islands
3' are formed by performing a photolithography and etching process
upon the polycrystalline silicon layer.
[0042] Thereafter, gate insulating layers 4-1 and 4-2, patterned
gate electrode layers 5-1 and 5-2, a passivation layer 6, and a
metal layer 7 are formed to complete the TFT of FIG. 1.
[0043] In the manufacturing method as shown in FIGS. 3A and 3B,
however, since the polycrystalline silicon island 3 has a
randomly-small grain size, the mobility of carriers is so low that
the ON-current is low.
[0044] An embodiment of the method for manufacturing a TFT
according to the present invention will be explained next with
reference to FIGS. 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A and 8B. Note
that FIGS. 4A, 5A, 6A, 7A and 8A are cross-sectional views taken
along the line A-A of FIGS. 4B, 5B, 6B, 7B and 8B,
respectively.
[0045] First, referring to FIGS. 4A and 4B, an about 0.5 to 1.1 mm
thick glass substrate 1 is subject to a cleaning and rinsing
process to remove contaminants such as organic matter, metal or
small particles from the surface of the glass substrate 1. Then, in
order to prevent harmful impurities from diffusing from the glass
substrate 1, an about 1 .mu.m thick substrate covering layer 2 made
of silicon oxide is deposited on the glass substrate 1 by an LPCVD
process using silane gas and oxygen gas. Note that the substrate
covering layer 2 can be deposited by a plasma CVD process using
tetraethoxysilane (TEOS) gas and oxygen gas an atmospheric pressure
CVD (APCVD) process using TEOS gas and ozone gas, or a remote
plasma CVD process where a deposition area is separated from a
plasma gas generation area. Then, an about 60 to 80 nm thick
amorphous silicon layer 3 is deposited on the substrate covering
layer 2 by an LPCVD process using disilane gas at a temperature of
about 500.degree. C. In this case, the hydrogen concentration of
the amorphous silicon layer 3 is less than 1 atom percent to
prevent the emission of hydrogen atoms from the amorphous silicon
layer 3 by a laser irradiation process which will be carried out
later. If a large number of hydrogen atoms are emitted from the
amorphous silicon layer 3, the surface of a polycrystalline silicon
layer converted therefrom greatly fluctuates. Also, the
above-mentioned amorphous silicon layer 3 having a low hydrogen
concentration can be deposited by a plasma CVD process using silane
gas and hydrogen gas, or tetrafluoro-silane gas and hydrogen
gas.
[0046] Next, referring to FIGS. 5A and 5B, the glass substrate 1 is
again subject to a cleaning and rinsing process to remove
contaminants such as organic matter, metal, small particles and
silicon oxide from the surface of the amorphous silicon layer 3.
Then, the glass substrate 1 is entered into the pulse laser
apparatus of FIG. 2 where the amorphous silicon layer 3 is
irradiated with laser line beams under an atmosphere of pure
nitrogen gas at a 700 Torr (8.33 .times.10.sup.4 Pa). In this case,
the laser line beams have a rectangular size of 5 .mu.m.times.100
.mu.m. Also, the energy of the laser beams is relatively high, for
example, about 400 to 900 mJ/am.sup.2, and also, the slope of the
energy with respect to the Y-direction is relatively sharp. As a
result, as illustrated in FIG. 5B, crystalline silicon seeds (not
shown) are randomly generated at portions of the amorphous silicon
layer 3 at Y=Y1, Y2, Y1' and Y2' where the temperature is close to
a melting point of silicon. Then, polycrystalline silicon is grown
from the crystalline silicon seeds toward the center of each of the
laser line beams at Y=Y3 and Y3'. Finally, the growth of
polycrystalline silicon stops at Y=Y3 and Y3'. Thus, a
polycrystalline silicon layer 3' is obtained to include elongated
grains having a length of an approximately half of the width of the
laser line beams. As a result, the polycrystalline silicon layer 3'
has stripes each of which is divided into two regions 31 and 32.
Then, nitrogen is exhausted from the pulse laser apparatus, and
then, oxygen gas is introduced thereinto.
[0047] Next, referring to FIGS. 6A and 6B, an about 10 nm thick
gate insulating layer 4-1 made of silicon oxide is deposited on the
entire surface by a plasma CVD process using silane gas, helium gas
and oxygen gas at a temperature of about 350.degree. C. Note that
the gate insulating layer 4-1 can be deposited by a plasma CVD
process using TEOS gas and oxygen gas or an APCVD process using
TEOS gas and ozone gas. Thereafter, as occasion demands, a hydrogen
plasma process and an annealing process are carried out. Then, the
gate insulating layer 4-1 and the polycrystalline silicon layer 3'
are patterned by a photolithography and etching process, so that
islands formed by the gate insulating layer 4-1 and the
polycrystalline silicon layer 3' are formed. In this case, the
sides of the islands (3', 4-1) are tapered to suppress gate leakage
currents. However, the gate insulating layer 4-1 can be
deleted.
[0048] Next, referring to FIGS. 7A and 7B, the glass substrate 1 is
again subject to a cleaning and rinsing process to remove
contaminants such as organic matter, metal and small particles from
the surface of the gate insulating layer 4-1 and the like. Then, an
about 30 nm thick gate insulating layer 4-2 made of silicon oxide
is deposited on the entire surface by a plasma CVD process using
silane gas and oxygen gas at a temperature of about 450.degree. C.
Note that the gate insulating layer 4-2 can be deposited by a
plasma CVD process using TEOS gas and oxygen gas or an APCVD
process using TEOS gas and ozone gas. Then, an about 80 nm thick
gate electrode layer 5-1 made of phosphorus-doped polycrystalline
silicon is deposited on the gate insulating layer 4-2 by a plasma
CVD process or an LPCVD process, and an about 110 nm thick gate
electrode layer 5-2 made of tungsten silicide is deposited on the
gate electrode layer 5-1 by a sputtering process. Then, the gate
electrode layers 5-1 and 5-2 are patterned by a photolithography
and etching process. Then, impurity ions are implanted into the
polycrystalline silicon islands 3' in self-alignment with the
patterned gate electrode layers 5-1 and 5-2. For example, if the
impurity ions are of an n-type, source regions S and drain regions
D of an n+-type are formed within the polycrystalline silicon
islands 3'. On the other hand, if the impurity ions are of a
p-type, source regions S and drain regions D of a p+-type are
formed within the polycrystalline silicon islands 3'. Note that
undoped regions of the polycrystalline silicon islands 3' serve as
channel regions C.
[0049] Finally, referring to FIGS. 8A and 8B, a passivation layer 6
made of silicon oxide is deposited on the entire surface by a
plasma CVD process using TEOS gas and oxygen gas or an APCVD
process using TEOS gas and ozone gas. Note that, the passivation
layer 6 can be made of silica coating material or organic coating
material, silicon nitride. As occasion demands, the passivation
layer 6 is flatten by an annealing process or the like. Then,
contact holes CONT are perforated in the gate insulating layers 4-1
and 4-2 and the passivation layer 6 by a photolithography and
etching process thereupon. Then, a metal layer 7 made of aluminum,
aluminum alloy, copper, copper alloy or refractory metal such as
tungsten or molybdenum is deposited on the entire surface by a
sputtering process or the like, and the metal layer 7 is patterned
by a photolithography and etching process.
[0050] In FIG. 8B, note that a CMOS inverter formed by a P-channel
TFT and two N-channel TFTs.
[0051] In FIGS. 9 and 10, which are cross-sectional views of
modifications of FIGS. 7A and 8A, respectively, the implantion of
impurity ions is performed directly upon the polycrystalline
silicon islands 3'. In this case, the gate insulating layers 4-1
and 4-2 are etched by using the gate electrode layers 5-1 and 5-2
as an etching mask before the implantation of impurity ions.
[0052] In the above-described embodiment, the irradiation of laser
line beams to the amorphous silicon layer 3 can be carried out by
using alignment marks. For example, the alignment marks made of
tungsten silicide or the like are formed on the substrate covering
layer 2 before the irradiation of laser beams to the amorphous
silicon layer 3. On the other hand, alignment marks are formed on
the amorphous silicon layer 3 simultaneously with the irradiation
of laser line beams to the amorphous silicon layer 3. Thereafter,
the patterning of the polycrystalline silicon layer 3' into the
islands is carried out by using the above-mentioned alignment
marks.
[0053] The inventors have actually obtained the polycrystalline
silicon layer 3' of FIGS. 5A and 5B as shown in SEM photographs as
shown in FIGS. 11A and 11B. Note that FIG. 11B is an enlargement of
FIG. 11A. Apparently, the polycrystalline silicon layer 3' has
elongated grains along the Y direction and is divided into the two
regions 31 and 32.
[0054] In the above-described embodiments, since the TFTs are
formed so that the running direction of carriers is along the Y
direction, i.e., the growth direction of crystal, the mobility of
carriers is so high that the ON current is high. Additionally,
since each of the TFTs are formed within either of the regions 31
and 32, the mobility of carriers is further increased, so that the
ON current is further increased. Note that if each of the TFTs is
formed across the regions 31 and 32, the mobility of carriers is a
little decreased so that the ON current is a little decreased.
[0055] Apparatuses to which the TFT of the present invention is
applied will be explained next with reference to FIGS. 12, 13, 14,
15, 16, 17A and 17B.
[0056] A first example is a digital camera as illustrated in FIGS.
12, 13, 14 and 15.
[0057] In FIG. 12, a digital camera is constructed by a camera body
1201 on which a lens 1202 is mounted. An image input unit 1203 is
incorporated into the camera body 1201. For example, the image
input unit 1203 has the same size as the size of a 35 -mm
photographic film. Therefore, in the digital camera of FIG. 12, the
image input unit 1203 can be replaced with 35 -mm photographic
films. Also, a microcomputer 1204 formed by a central processing
unit (CPU), a flash memory, an encoder, an interface and the like
is incorporated into the camera body 1201, and can be connected by
a flexible cable 1205 to the image input unit 1203.
[0058] In FIG. 13, which is a detailed plan view of the image input
unit 1203 of FIG. 12, the image input unit 1203 is constructed by a
glass substrate 1301 corresponding to the glass substrate 1 of the
embodiment of the TFT according to the present invention, a pixel
array section 1302, and peripheral circuits such as an X-scanning
circuit 1303, a Y-scanning circuit 1304 and a reset circuit 1305.
In this case, the glass substrate 1301 is 1.1 mm, 0.7 mm or 0.5 mm
thick, and has a size of 48 mm.times.35 mm. Also, the pixel array
section 1302 has a size of 36 mm.times.24 mm.
[0059] The pixel array section 1302 is constructed by a plurality
of photodiode-type active pixels each including a 20 .mu.m.times.20
.mu.m photodiode PD such as a Schottky barrier diode buffered by a
source follower TFT Q1, a selection TFT Q2 and a reset TFT Q3. The
TFT Q1 is selected by the X-scanning circuit 1303, while the TFT Q2
is selected by the Y-scanning circuit 1304. Also, the TFT Q3 is
turned ON by a reset signal RST of the reset circuit 1305, thereby
resetting the voltage of the photodiode PD at V.sub.cc (see: Eric
R. Fossum, FIG. 4 of "CMOS Image Sensor: Electronic Camera On A
Chip", IEDM Digest, pp. 17-25, 1995). Note that a PIN diode can be
used as the photodiode PD. The TFTs Q1, Q2 and Q3 are those
according to the embodiment of the present invention.
[0060] Also, a photodiode 1302a such as a Schottky barrier diode is
provided at a periphery area of the pixels to detect whether or not
a shutter (not shown) in the camera body 1201 is opened. That is,
as shown in FIG. 14(A), when the shutter is opened, the photodiode
1302a generates a detection signal D as shown in FIG. 14(B). As a
result, the reset circuit 1305 receives the detection signal D and
generates a reset signal RST as shown in FIG. 14(C) in response to
a rising edge of the detection signal D. Therefore, the TFTs Q3 of
all the pixels are turned ON, so that the voltage of the photodiode
PD are reset at V.sub.cc. Then, when a predetermined time period
has passed after the reset signal RST is generated, the scanning
circuits 1303 and 1304 are operated as shown in FIG. 14 (D) so that
image information stored in the photodiodes PD of all the pixels
are transmitted to the microcomputer 1204 which performs data
processing thereupon. Note that a PIN diode can be used as the
photodiode 1302a.
[0061] In FIG. 15, which is a detailed cross-sectional view of the
photodiode PD and the TFT Q3 of FIG. 13, the TFT Q3 is formed on
the glass substrate 1301 in accordance with the embodiment of the
present invention. That is, the TFT Q3 is constructed by a
polycrystalline silicon island 1501, a source region S, a channel
region C and a drain region D corresponding to the polycrystalline
silicon island 3' of FIG. 8A or 10, a gate electrode 1502
corresponding to the gate electrode layers 5-1 and 5-2 of FIG. 8A
or 10, and an insulating layer 1503 corresponding to the gate
insulating layers 4-1 and 4-2 and the passivation layer 6 of FIG.
8A or 10. Also, a contact hole is perforated in the insulating
layer 1503 above the source region S of the polycrystalline silicon
island 1501. Further, a Cr lower electrode layer 1504, an intrinsic
amorphous silicon layer 1505, a P.sup.+-type amorphous silicon
layer 1506 and an upper indium tin oxide (ITO) upper transparent
electrode layer 1507 are sequentially formed to form the photodiode
PD. Note that, if the photodiode PD is replaced by a PIN diode, an
n-type amorphous silicon layer is inserted between the Cr under
electrode layer 1504 and the intrinsic amorphous silicon layer
1505.
[0062] In FIG. 15, only the TFT Q3 is illustrated, however, the
TFTs Q1 and Q2 are also formed in the same way as the TFT Q1, so
that the photodiode PD is formed over the TFTs Q1, Q2 and Q3.
[0063] A second example is an SRAM cell as illustrated in FIG. 16.
In FIG. 16, one memory cell is provided at each intersection
between two word lines WL1 and WL2 and two complementary date lines
DL1 and DL2. Thus memory cell is constructed by a flip-flop formed
by two cross-coupled inverters, and two N-channel transfer MOS
transistors Q.sub.t1 and Q.sub.t2 connected between the flip-flop
and the data lines DL1 and DL2. The transfer transistors Q.sub.t1
and Q.sub.t2 are controlled by voltages at the word lines WL1 and
WL2, respectively. Each of the inverters includes a P-channel load
TFT Q.sub.p1 (Q.sub.p2) and an N-channel driving bulk MOS
transistor Q.sub.d1 (Q.sub.d2) between a power supply voltage line
V.sub.cc and a ground voltage line V.sub.ss.
[0064] The P-channel TFTs Q.sub.p1 and Q.sub.p2 are those according
to the present invention.
[0065] A third example is a projector as illustrated in FIGS. 17A
and 17B.
[0066] In FIG. 17A, the projector is constructed by a halogen lamp
1701, dichotic lenses 1702 to 1707, light valves 1708, 1709 and
1710, a projection lens 1711 and a screen 1712. In this case, a red
component R is generated by the lenses 1702, 1705, 1706 and 1707
and the light valve 1708; a blue component B is generated by the
lenses 1702, 1703, 1706 and 1707 and the light valve 1709; and a
green component G is generated by the lenses 1702, 1703, 1704 and
1707 and the light valve 1710.
[0067] As illustrated in FIG. 17B, each of the light valves 1708,
1709 and 1710 is an active matrix-type liquid crystal display (LCD)
apparatus which is constructed by a plurality of pixels P.sub.ij at
intersections between data bus lines DL.sub.i and gate bus lines
GL.sub.j. One of the data bus lines SL.sub.i is driven by a data
driver 1721 and one of the gate bus lines GL.sub.j is driven by a
gate driver 1722. Also, each of the pixels P.sub.ij is constructed
by one TFT Q and one liquid crystal cell C. The TFT Q is one
according to the embodiment of the present invention.
[0068] As explained hereinabove according to the present invention,
in a TFT, the mobility of carriers can be increased, and
accordingly, the ON current can be increased.
* * * * *