U.S. patent application number 09/274430 was filed with the patent office on 2002-05-16 for perimeter matrix ball grid array circuit package with a populated center.
Invention is credited to BARROW, MICHAEL.
Application Number | 20020057558 09/274430 |
Document ID | / |
Family ID | 24497765 |
Filed Date | 2002-05-16 |
United States Patent
Application |
20020057558 |
Kind Code |
A1 |
BARROW, MICHAEL |
May 16, 2002 |
PERIMETER MATRIX BALL GRID ARRAY CIRCUIT PACKAGE WITH A POPULATED
CENTER
Abstract
A ball grid array (BGA) integrated circuit package which has an
outer two-dimensional array of solder balls and a center
two-dimensional array of solder balls located on a bottom surface
of a package substrate. The solder balls are typically reflowed to
mount the package to a printed circuit board. Mounted to an
opposite surface of the substrate is an integrated circuit that is
electrically coupled to the solder balls by internal routing within
the package. The outer array of solder balls are located the
dimensional profile of the integrated circuit to reduce solder
stresses induced by the differential thermal expansion between the
integrated circuit and the substrate. The center solder balls are
typically routed directly to ground and power pads of the package
to provide a direct thermal and electrical path from the integrated
circuit to the printed circuit board.
Inventors: |
BARROW, MICHAEL; (EL DORADO
HILLS, CA) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD
SEVENTH FLOOR
LOS ANGELES
CA
90025
|
Family ID: |
24497765 |
Appl. No.: |
09/274430 |
Filed: |
March 22, 1999 |
Current U.S.
Class: |
361/760 ;
257/E23.069; 257/E23.07; 257/E23.105 |
Current CPC
Class: |
Y10T 29/49155 20150115;
H01L 24/48 20130101; H01L 2224/48091 20130101; H01L 23/50 20130101;
H01L 23/49838 20130101; H01L 23/3677 20130101; H01L 2924/3011
20130101; H01L 21/4853 20130101; H01L 2224/48227 20130101; H01L
24/16 20130101; H01L 2924/14 20130101; H01L 2924/30107 20130101;
H01L 23/49816 20130101; Y10T 29/49222 20150115; H01L 2924/15311
20130101; Y10T 29/49144 20150115; H01L 2924/00014 20130101; H01L
23/3128 20130101; H05K 3/3436 20130101; H01L 2224/16 20130101; H01L
2924/181 20130101; Y10T 29/49204 20150115; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/45099 20130101; H01L 2924/00014 20130101; H01L 2224/05599
20130101; H01L 2924/00014 20130101; H01L 2224/85399 20130101; H01L
2924/181 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2224/45015 20130101; H01L 2924/207 20130101 |
Class at
Publication: |
361/760 |
International
Class: |
H05K 007/02 |
Claims
What is claimed is:
1. A ball grid array package, comprising: a substrate which has a
top surface and an opposite bottom surface, said bottom surface
having an outer array of contact pads each separated from each
other by a first distance, and a center array of contact pads each
separated from each other by a second distance, said center array
of contact pads being separated from said outer array of contact
pads by a third distance which is larger than the first and second
distances; and, a plurality of solder balls attached to said
contact pads of said substrate.
2. The package as recited in claim 1, wherein said top surface of
said substrate has a plurality of bond pads.
3. The package as recited in claim 2, wherein said top surface of
said substrate has a ground bus that is connected to said center
array of contact pads by a plurality of vias that extend through
said substrate.
4. The package as recited in claim 3, wherein said outer array of
contact pads has at least five rows of contact pads.
5. The package as recited in claim 4, wherein said top surface of
said substrate has a power bus that is connected to said center
array of contact pads by a plurality of vias that extend through
said substrate.
6. The package as recited in claim 5, wherein said center array of
contact pads is arranged in a four by four matrix.
7. A ball grid array integrated circuit package, comprising: a
substrate which has a top surface and an opposite bottom surface,
said top surface having a plurality of bond pads, said bottom
surface having an outer array of contact pads each separated from
each other by a first distance, and a center array of contact pads
each separated from each other by a second distance, said center
array of contact pads being separated from said outer array of
contact pads by a third distance which is larger than the first and
second distances; a plurality of solder balls attached to said
contact pads of said substrate; and, an integrated circuit that is
mounted to said substrate and coupled to said bond pads.
8. The package as recited in claim 7, wherein said top surface of
said substrate has a ground bus that is coupled to said integrated
circuit and connected to said center array of contact pads by a
plurality of vias that extend through said substrate.
9. The package as recited in claim 8, wherein said outer array of
contact pads has at least five rows of contact pads.
10. The package as recited in claim 9, wherein said top surface of
said substrate has a power bus that is connected to said center
array of contact pads by a plurality of vias that extend through
said substrate.
11. The package as recited in claim 10, wherein said center array
of contact pads is arranged in a four by four matrix.
12. The package as recited in claim 11, wherein said integrated
circuit is enclosed by an encapsulant.
13. The package as recited in claim 7, wherein said outer array of
contact pads is located outside an outer dimensional profile of
said integrated circuit.
14. A method for assembling a ball grid array integrated circuit
package, comprising the steps of: a) providing a substrate which
has a top surface and an opposite bottom surface, said bottom
surface having an outer array of contact pads each separated from
each other by a first distance, and a center array of contact pads
each separated from each other by a second distance, said center
array of contact pads being separated from said outer array of
contact pads by a third distance which is larger than the first and
second distances; b) mounting an integrated circuit to said top
surface of said substrate; and, c) attaching a plurality of said
solder balls to said contact pads.
15. The method as recited in claim 14, further comprising the step
of encapsulating said integrated circuit.
16. The method as recited in claim 15, further comprising the step
of coupling said integrated circuit to said substrate with a
plurality of bond wires.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an integrated circuit
package.
[0003] 2. Description of Related Art
[0004] Integrated circuits are typically mounted to a package that
is soldered to a printed circuit board. One such type of integrated
circuit package is a ball grid array ("BGA") package. BGA packages
have a plurality of solder balls located on a bottom external
surface of a package substrate. The solder balls are ref lowed to
attach the package to the printed circuit board. The integrated
circuit is mounted to a top surface of the package substrate, and
electrically coupled to the solder balls by internal routing within
the package.
[0005] FIG. 1 shows a solder ball array of a prior art BGA package
2. The solder balls 4 are arranged in a two-dimensional pattern
across the bottom surface of the package. The integrated circuit 6
is centrally located on the opposite side of the package 2. The
package 2 is typically constructed from a material which has a
coefficient of thermal expansion that is different than the thermal
expansion coefficient of the integrated circuit. It has been found
that the differential thermal expansion between the integrated
circuit and the package will induce temperature related stresses
that fail solder joints in an area which corresponds to the outer
edges of the circuit die.
[0006] FIG. 2 shows a BGA package 2 of the prior art which has an
outer two dimensional array of solder balls 4. The solder balls 4
are located away from the package area that is beneath the
integrated circuit 6. Locating the solder balls 4 away from the
integrated circuit 6 reduces the thermal stresses on the solder
joints created by the differential expansion between the package
and the integrated circuit. Although effective in reducing solder
failure the outer array pattern limits the input/output (I/O) of
the package. Additionally, the integrated circuit generates heat
which conducts through the solder balls and into the printed
circuit board. Locating the solder balls at the outer perimeter of
the package increases the thermal path through the package
substrate. The longer path increases the thermal impedance of the
package and the junction temperature of the integrated circuit. It
would be desirable provide a BGA package that has a longer product
life, lower thermal impedance and higher I/O than BGA packages of
the prior art.
SUMMARY OF THE INVENTION
[0007] The present invention is a ball grid array ("BGA")
integrated circuit package which has an outer two-dimensional array
of solder balls and a center two-dimensional array of solder balls
located on a bottom surface of a package substrate. The solder
balls are typically reflowed to mount the package to a printed
circuit board. Mounted to an opposite surface of the substrate is
an integrated circuit that is electrically coupled to the solder
balls by internal routing within the package. The outer array of
solder balls are located outside the dimensional profile of the
integrated circuit to reduce solder stresses induced by the
differential thermal expansion between the integrated circuit and
the substrate. The center solder balls are typically routed
directly to ground and power pads of the package to provide a
direct thermal and electrical path from the integrated circuit to
the printed circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The objects and advantages of the present invention will
become more readily apparent to those ordinarily skilled in the art
after reviewing the following detailed description and accompanying
drawings, wherein:
[0009] FIG. 1 is a bottom view of a ball grid array integrated
circuit package of the prior art;
[0010] FIG. 2 is a bottom view of a ball grid array integrated
circuit package of the prior art;
[0011] FIG. 3 is a side cross-sectional view of a ball grid array
package of the present invention;
[0012] FIG. 4 is a bottom view of the package shown in FIG. 3;
[0013] FIG. 5 is a bottom view of an alternate ball grid array
package.
DETAILED DESCRIPTION OF THE INVENTION
[0014] Referring to the drawings more particularly by reference
numbers, FIGS. 3 and 4 shows a ball grid array ("BGA") integrated
circuit package 10 of the present invention. The package 10
includes a substrate 12 that has a top surface 14 and an opposite
bottom surface 16. Mounted to the top surface 14 of the substrate
12 is an integrated circuit 16. The integrated circuit 18 is
typically a microprocessor. Although a microprocessor is described,
it is to be understood that the package 10 may contain any
electrical device(s).
[0015] The top surface 14 of the substrate 12 has a plurality of
bond pads 20 and a ground bus 22. The substrate 12 may also have a
separate power bus 23 concentrically located about the integrated
circuit 18 and ground pad 22. The integrated circuit 18 is coupled
to the bond pads 20 and busses 22 and 23 by bond wires 24. The
integrated circuit 16 is typically enclosed by an encapsulant 26.
Although bond wires 24 are shown and described, the integrated
circuit 18 can be mounted and coupled to the substrate with solder
balls located on the bottom surface of the circuit die in a package
and process commonly referred to as "C4" or "flip chip"
packaging.
[0016] The bottom surface 16 of the substrate 12 has a plurality of
contact pads 28. The contact pads 28 are coupled to the bond pads
20 and busses 22 and 23 by vias 30 and internal routing 32 within
the substrate 12. The substrate can be constructed with
conventional printed circuit board, or co-fired ceramic, packaging
processes known in the art.
[0017] A plurality of solder balls 34 are attached to the contact
pads 28 with known ball grid array processes. The solder balls 34
are typically reflowed to attach the package 10 to a printed
circuit board (not shown).
[0018] The contact pads 28 are arranged in an outer two-dimensional
array 36 and a center two-dimensional array 38. Bach array contains
a plurality of contact pads 28 that are separated from each other
by a number of dielectric spaces 40. The outer array 36 is
separated from the center array 38 by a dielectric area 42. The
outer array 38 is preferably located outside of the outer
dimensional profile of the integrated circuit 18. In this manner
the solder joints of the outer array 38 are not subjected to
stresses created by the difference in the coefficient of thermal
expansion of the integrated circuit 18 and the expansion
coefficient of the substrate 12. The center array 38 is located
near the origin of the integrated circuit 16 in an area that does
not undergo as much thermal expansion as the outer edges of the
circuit die. Therefore the solder stresses created by the
differential thermal expansion is minimal in the area of the center
array 38. The separated arrays provide a pattern that minimizes the
stresses on the solder joints.
[0019] The outer array 36 is typically coupled to the signal lines
of the integrated circuit 16. The center array 38 is preferably
coupled to the ground bus 20 and power bus 23 of the substrate 12.
The vias 30 that couple the busses 22 and 23 to the center contact
pads 38 provide a direct thermal path through the substrate. The
direct path lowers the thermal impedance of the package 10 and the
junction temperature of the integrated circuit 18. Additionally,
the short electrical path lowers the self-inductance and reduces
the switching noise of the integrated circuit 18.
[0020] In the preferred embodiment, the package 10 contains 292
contact pads 28 on a 27 by 27 millimeter (mm) wide substrate 12, or
352 contact pads 28 on a 35 by 35 mm substrate 12. The dielectric
space 40 between the contact pads 28 is typically 1.27 mm. The
package 10 typically has a height of approximately 2.5 mm.
[0021] The package 10 is assembled by attaching the solder balls 34
to the contact pads 28. The integrated circuit 18 is mounted and
coupled to the substrate 12. The integrated circuit 18 is then
enclosed by the encapsulant 26. The BGA package 10 is typically
shipped to an end user that mounts the package 10 to a printed
circuit board by reflowing the solder balls 34.
[0022] FIG. 5 shows an alternate embodiment of a package 10 which
has five or six rows of contact pads 28 in the outer array 36' of
the substrate 12'. The additional pads 28 increase the input/output
(I/O) of the package 10. The outer array 36' is preferably outside
the outer dimensional profile of the integrated circuit 18 to
minimize the stresses on the solder joints. The package 10' may
provide 324 contact pads 28 on a 27 by 27 mm substrate 10. The
longer rows of the package 60 provide the approximate I/O of a 35
by 35 mm package, within the footprint of a 27 by 27 mm
package.
[0023] While certain exemplary embodiments have been described and
shown in the accompanying drawings, it is to be understood that
such embodiments are merely illustrative of and not restrictive on
the broad invention, and that this invention not be limited to the
specific constructions and arrangements shown and described, since
various other modifications may occur to those ordinarily skilled
in the art.
* * * * *