U.S. patent application number 09/531177 was filed with the patent office on 2002-05-16 for semiconductor integrated circuit device and its manufacturing method.
Invention is credited to Haga, Ryo, Miyano, Shinji, Wada, Osamu, Yabe, Tomoaki.
Application Number | 20020056907 09/531177 |
Document ID | / |
Family ID | 11519690 |
Filed Date | 2002-05-16 |
United States Patent
Application |
20020056907 |
Kind Code |
A1 |
Wada, Osamu ; et
al. |
May 16, 2002 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING
METHOD
Abstract
On a semiconductor substrate, there are formed a first macro
cell having wiring layers of three layers each formed of a metal
wiring layer (for example, an aluminum wiring) and a second macro
cell having wiring layers of three layers each formed of a metal
wiring layer similar to the first macro cell. The first macro cell
is formed to have a wiring structure of three wiring layers though
the originally necessary number of metal wiring layers is two. The
metal wiring layer of each layer on the first macro cell is formed
of the same material as the metal wiring layer of the corresponding
each layer on the second macro cell. Moreover, the metal wiring
layer of each layer is formed to have the same film thickness. In
order to connect the first and second macro cells to each other, a
macro interconnection wiring is formed to be included in the third
wiring layer (uppermost wiring layer).
Inventors: |
Wada, Osamu; (Yokohama-shi,
JP) ; Haga, Ryo; (Yokohama-shi, JP) ; Yabe,
Tomoaki; (Fujisawa-shi, JP) ; Miyano, Shinji;
(Yokohama-shi, JP) |
Correspondence
Address: |
Banner & Witcoff Ltd
1001 G Street NW
Washington
DC
20001-4597
US
|
Family ID: |
11519690 |
Appl. No.: |
09/531177 |
Filed: |
March 21, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09531177 |
Mar 21, 2000 |
|
|
|
09000551 |
Dec 30, 1997 |
|
|
|
Current U.S.
Class: |
257/700 ;
257/758; 257/E23.151; 257/E27.105 |
Current CPC
Class: |
H01L 2924/0002 20130101;
Y10S 257/903 20130101; H01L 27/118 20130101; H01L 23/528 20130101;
H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/700 ;
257/758 |
International
Class: |
H01L 023/053 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 9, 1997 |
JP |
9-002091 |
Claims
1. A semiconductor integrated circuit device comprising: a
semiconductor substrate having first and second macro cells each
having a plurality of elements formed; and wiring layers of N
layers (N.gtoreq.3) formed on said semiconductor substrate
sequentially from a first wiring layer to an N-th wiring layer,
wherein N-1 wiring layer on said first macro cell includes a first
wiring pattern having a plurality of pattern segments, N-th wiring
layer on said first macro cell includes a second wiring pattern
having one or more same pattern segments among the plurality of
pattern segments, and the plurality of pattern segments include one
or more contact pattern, respectively.
2. The semiconductor integrated circuit device according to claim
1, wherein one or more pattern segments of said second wiring
pattern are arranged at the same position as one or more pattern
segments of said first wiring pattern with the same shape on a plan
of said substrate.
3. The semiconductor integrated circuit device according to claim
1, further comprising a contact plug for connecting the contact
pattern of said second wiring pattern to the contact pattern of
said same pattern segment of said first wiring pattern.
4. The semiconductor integrated circuit device according to claim
1, wherein said first wiring pattern forms a power supply line for
supplying operation power of said first macro cell, and a signal
line for transmitting a signal of said first macro cell.
5. The semiconductor integrated circuit device according to claim
4, one or more pattern segments of said second wiring pattern form
the same power supply line as said power supply line of said first
wiring pattern.
6. The semiconductor integrated circuit device according to claim
4, wherein one or more pattern segments of said second wiring
pattern form the same signal line as a critical path in said signal
line of said first wiring pattern.
7. The semiconductor integrated circuit device according to claim
1, wherein said N-th wiring layer includes a macro interconnection
wire for connecting said first and second macro cells to each
other.
8. The semiconductor integrated circuit device according to claim
1, wherein each of said wiring layer of N layers has an equal
thickness.
9. The semiconductor integrated circuit device according to claim
1, further comprising insulating layers of N layers formed on each
of said semiconductor substrate and said wiring layers of N layers,
and each of said insulating layers has an equal thickness.
10. The semiconductor integrated circuit device according to claim
1, wherein said N-th wiring layer is the thickest among said wiring
layers of N layers.
11. The semiconductor integrated circuit device according to claim
1, wherein surfaces of said first to N-th wiring layers are
flattened, respectively.
12. The semiconductor integrated circuit device according to claim
1, wherein said first macro cell is a memory section, and said
second macro cell is an ASIC section.
13. The semiconductor integrated circuit device according to claim
1, wherein the pattern segment of said second pattern is a pattern
segment multiplied by a predetermined value in a line width
direction as compared with the pattern segment of said first wiring
pattern, and said predetermined value is an arbitrary value in a
positive number and a decimal.
14. A semiconductor integrated circuit device comprising: a
semiconductor substrate having first and second macro cells each
having a plurality of elements formed; and wiring layers of N
layers (N.gtoreq.3) formed on said semiconductor substrate
sequentially from a first wiring layer to an N-th wiring layer,
wherein N-2 wiring layer on said first macro cell includes a first
wiring pattern having a plurality of pattern segments, each of said
plurality of pattern segments has at least one contact pattern, N-1
wiring layer on said first macro cell includes one or more same
contact pattern as the contact pattern formed on said first wiring
pattern, and the Nth wiring layer on said first macro cell includes
a second wiring pattern having one or more same pattern segments
among the plurality of pattern segments.
15. The semiconductor integrated circuit device according to claim
14, wherein one or more pattern segments of said second wiring
pattern are arranged at the same position as one or more pattern
segments of said first wiring pattern with the same shape on a plan
of said substrate.
16. The semiconductor integrated circuit device according to claim
14, further comprising a first contact plug for connecting the
contact pattern of said second wiring pattern to the contact
pattern of said N-1 wiring layer, and a second contact plug for
connecting the contact pattern of said N-1 wiring layer to the
contact pattern of said same pattern segment of said first wiring
pattern.
17. The semiconductor integrated circuit device according to claim
14, wherein said first wiring pattern forms a power supply line for
supplying operation power of said first macro cell, and a signal
line for transmitting a signal of said first macro cell.
18. The semiconductor integrated circuit device according to claim
17, one or more pattern segments of said second wiring pattern form
the same power supply line as said power supply line of said first
wiring pattern.
19. The semiconductor integrated circuit device according to claim
17, wherein one or more pattern segments of said second wiring
pattern form the same signal line as a critical path in said signal
line of said first wiring pattern.
20. The semiconductor integrated circuit device according to claim
14, wherein said N-th wiring layer includes a macro interconnection
wire for connecting said first and second macro cells to each
other.
21. The semiconductor integrated circuit device according to claim
14, wherein each of said wiring layer of N layers has an equal
thickness.
22. The semiconductor integrated circuit device according to claim
14, further comprising insulating layers of N layers formed on each
of said semiconductor substrate and said wiring layers of N layers,
and each of said insulating layers has an equal thickness.
23. The semiconductor integrated circuit device according to claim
14, wherein said N-th wiring layer is the thickest among said
wiring layers of N layers.
24. The semiconductor integrated circuit device according to claim
14, wherein surfaces of said first to N-th wiring layers are
flattened, respectively.
25. The semiconductor integrated circuit device according to claim
14, wherein said first macro cell is a memory section, and said
second macro cell is an ASIC section.
26. A semiconductor integrated circuit device comprising: a
semiconductor substrate having a plurality of macro cells whose
necessary number of metal wiring layers differs; and a plurality of
metal wiring layers formed on said semiconductor substrate, wherein
an uppermost wiring layer of the macro cell whose necessary number
of metal wiring layers is smaller is formed of the same wiring
layer as an uppermost wiring layer of the macro cell whose
necessary number of metal wiring layers is larger.
27. A method of manufacturing a semiconductor integrated circuit
device in which first and second macro cell regions whose necessary
number of metal wiring layers formed on a semiconductor substrate
differs are embedded on the same chip comprising the step of:
forming an uppermost wiring layer of the macro cell whose necessary
number of metal wiring layers is smaller is formed of the same
wiring layer as an uppermost wiring layer of the macro cell whose
necessary number of metal wiring layers is larger.
28. A method of manufacturing a semiconductor integrated circuit
device comprising the steps of: forming a semiconductor substrate
having first and second macro cells each having a plurality of
elements formed; and forming wiring layers of N layers (N.gtoreq.3)
on said semiconductor substrate sequentially from a first wiring
layer to an N-th wiring layer, the step of forming the wiring
layers of N layers includes a sub-step of forming said N-1 wiring
layer to include a first pattern having a plurality of pattern
segments, and a sub-step of forming said N-th wiring layer on said
first macro cell to include a second wiring pattern having one or
more same pattern segments among the plurality of pattern segments,
and the plurality of pattern segments include one or more contact
pattern, respectively.
29. The method according to claim 28, wherein the step of forming
the wiring layers of N layers includes a sub-step of forming said
second wiring pattern such that one or more pattern segments of
said second wiring pattern are arranged at the same position as one
or more pattern segments of said first wiring pattern with the same
shape on a plan of said substrate.
30. The method according to claim 28, further comprising the step
of forming a contact plug for connecting the contact pattern of
said second wiring pattern to the contact pattern of said same
pattern segment of said first wiring pattern.
31. The method according to claim 28, wherein the step of forming
the wiring layers of N layers includes a sub-step of forming said
Nth wiring layer such that the pattern segment of said second
pattern is a pattern segment multiplied by a predetermined value in
a line width direction as compared with the pattern segment of said
first wiring pattern wherein said predetermined value is an
arbitrary value in a positive number and a decimal.
32. A method of manufacturing a semiconductor integrated circuit
device comprising the steps of: forming a semiconductor substrate
having first and second macro cells each having a plurality of
elements formed; and wiring layers of N layers (N.gtoreq.3) formed
on said semiconductor substrate sequentially from a first wiring
layer to an N-th wiring layer, wherein the step of forming said
wiring layers of N layers includes: a sub-step of forming said N-2
wiring layer such that the N-2 wiring layer on said first macro
cell includes a first wiring pattern having a plurality of pattern
segments wherein each of said plurality of pattern segments has at
least one contact pattern: a sub-step of forming said N-1 wiring
layer such that said N-1 wiring layer on said first macro cell
includes one or more same contact pattern as the contact pattern
formed on said first wiring pattern; and a sub-step of forming said
Nth wiring layer such that said Nth wiring layer on said first
macro cell includes a second wiring pattern having one or more same
pattern segments among the plurality of pattern segments.
33. The method according to claim 32, wherein the step of forming
the wiring layers of N layers includes a sub-step of forming said
second wiring pattern such that one or more pattern segments of
said second wiring pattern are arranged at the same position as one
or more pattern segments of said first wiring pattern with the same
shape on a plan of said substrate.
34. The method according to claim 32, further comprising the step
of forming a first contact plug for connecting the contact pattern
of said second wiring pattern to the contact pattern of said N-1
wiring layer, and a second contact plug for connecting the contact
pattern of said N-1 wiring layer to the contact pattern of said
same pattern segment of said first wiring pattern.
35. The method according to claim 32, wherein the step of forming
the wiring layers of N layers includes a sub-step of forming said
Nth wiring layer such that the pattern segment of said second
pattern is a pattern segment multiplied by a predetermined value in
a line width direction as compared with the pattern segment of said
first wiring pattern wherein said predetermined value is an
arbitrary value in a positive number and a decimal.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor integrated
circuit device including a macro cell on which three or more wiring
layers is required to be formed, and its manufacturing method.
Particularly, the present invention relates to a semiconductor
integrated circuit device in which a plurality of macro cells whose
originally necessary number of metal wiring layers differs is
embedded on the same semiconductor chip, and its manufacturing
method.
[0002] Moreover, the present invention relates to a large scale
integrated circuit (LSI) in which an ASIC (application-specific
integrated circuit) section and a semiconductor memory section are
embedded, and its manufacturing method.
[0003] This application is based on Japanese Patent Application No.
9-2091, filed on Jan. 9, 1997, the contents of which is cited
herein by reference. This application is based on Japanese Patent
Application No. 9-2091, filed on Jan. 9, 1997, the contents of
which is cited herein by reference. In recent years, in the
manufacture of LSI, there is a case in which a plurality of kinds
of macro cells is embedded on the same semiconductor chip. In this
case, the originally necessary number of metal wiring layers, which
is formed on a semiconductor substrate, differs.
[0004] For example, as shown in FIG. 1, there is a case in which an
ASIC section 61 and a memory section 62 are formed in an adjacent
area on an LSI chip 60. Further, as shown in FIG. 2, there is a
case in which an ASIC section 61 having three wiring layers and a
memory section having two wiring layers are embedded on a
semiconductor substrate 70.
[0005] On the LSI chip 60, ASIC section 60 has a first wiring layer
71, a second wiring layer 72, and a third wiring layer 73. Though
the memory section 62 has the first and second wiring layers, but
no third wiring layer 73.
[0006] In FIG. 2, reference numeral 72a shows a first contact plug
for connecting the second wiring layer 72 to the first wiring layer
71. Reference numeral 73a shows a second contact plug for
connecting the third wiring layer 73 to the second wiring layer 72.
Reference numeral 74 is a first insulating layer on the
semiconductor substrate. Reference numeral 75 is a second
insulating layer on the first wiring layer 71. Reference numeral 76
is a third insulating layer on the second wiring layer 72.
Reference numeral 77 is a fourth insulating layer formed on the
third wiring layer 76 of the memory section 62 and the third wiring
layer 73 of the ASIC section 61.
[0007] In forming the third wiring layer 73 of the ASIC section 61
on the same chip as the memory section, a surface of the second
wiring layer 72 is flattened in the conventional process as shown
in FIG. 2. Due to this, a film thickness of the second wiring layer
72 is reduced, and its wiring resistance is increased. However, it
is assumed that the macro cell whose number of the necessary wiring
layers is small (memory cell section 62 in this example), the
uppermost wiring layer (second wiring layer 72) is used as a power
supply line. In this case, a potential drop, which is caused by an
increase in the wiring resistance, is increased. Also, it is
assumed that the uppermost wiring layer is used as a signal line,
which determines an operation velocity of the memory, that is, a
critical path. In this case, a wiring delay is increased by an
increase in the wiring resistance. Due to this, an electrical
characteristic (performance) as an LSI chip is lowered.
[0008] Thus, in the conventional LSI in which a plurality of macro
cells whose originally necessary number of metal wiring layers
differs is embedded on the same semiconductor chip, the film
thickness of the wiring layer having a macro cell whose number of
the necessary wiring layers is small is reduced, and its wiring
resistance is increased. As a result, the potential drop and the
wiring delay are increased by the increase in the wiring
resistance.
BRIEF SUMMARY OF THE INVENTION
[0009] An object of the present invention is to provide a
semiconductor integrated circuit device, which can restrict an
increase in wiring resistance and prevent an increase in a
potential drop and a wiring delay caused by the wiring resistance
when a plurality of macro cells whose originally necessary number
of metal wiring layers differs is embedded on the same chip, and
its manufacturing method.
[0010] According to a first aspect of the present invention, there
is provided a semiconductor integrated circuit device comprising: a
semiconductor substrate having first and second macro cells each
having a plurality of elements formed; and wiring layers of N
layers (N.gtoreq.3) formed on said semiconductor substrate
sequentially from a first wiring layer to an N-th wiring layer,
wherein N-1 wiring layer on said first macro cell includes a first
wiring pattern having a plurality of pattern segments, N-th wiring
layer on said first macro cell includes a second wiring pattern
having one or more same pattern segments among the plurality of
pattern segments, and the plurality of pattern segments include one
or more contact pattern, respectively.
[0011] According to a second aspect of the present invention, there
is provided a semiconductor integrated circuit device comprising: a
semiconductor substrate having first and second macro cells each
having a plurality of elements formed; and wiring layers of N
layers (N.gtoreq.3) formed on said semiconductor substrate
sequentially from a first wiring layer to an N-th wiring layer,
wherein N-2 wiring layer on said first macro cell includes a first
wiring pattern having a plurality of pattern segments, each of said
plurality of pattern segments has at least one contact pattern, N-1
wiring layer on said first macro cell includes one or more same
contact pattern as the contact pattern formed on said first wiring
pattern, and the Nth wiring layer on said first macro cell includes
a second wiring pattern having one or more same pattern segments
among the plurality of pattern segments.
[0012] According to a third aspect of the present invention, there
is provided a semiconductor integrated circuit device comprising: a
semiconductor substrate having a plurality of macro cells whose
necessary number of metal wiring layers differs; and a plurality of
metal wiring layers formed on said semiconductor substrate, wherein
an uppermost wiring layer of the macro cell whose necessary number
of metal wiring layers is smaller is formed of the same wiring
layer as an uppermost wiring layer of the macro cell whose
necessary number of metal wiring layers is larger.
[0013] According to a fourth aspect of the present invention, there
is provided a method of manufacturing a semiconductor integrated
circuit device in which first and second macro cell regions whose
necessary number of metal wiring layers formed on a semiconductor
substrate differs are embedded on the same chip comprising the step
of: forming an uppermost wiring layer of the macro cell whose
necessary number of metal wiring layers is smaller is formed of the
same wiring layer as an uppermost wiring layer of the macro cell
whose necessary number of metal wiring layers is larger.
[0014] According to a fifth aspect of the present invention, there
is provided a method of manufacturing a semiconductor integrated
circuit device comprising the steps of: forming a semiconductor
substrate having first and second macro cells each having a
plurality of elements formed; and forming wiring layers of N layers
(N.gtoreq.3) on said semiconductor substrate sequentially from a
first wiring layer to an N-th wiring layer, the step of forming the
wiring layers of N layers includes a sub-step of forming said N-1
wiring layer to include a first pattern having a plurality of
pattern segments, and a sub-step of forming said N-th wiring layer
on said first macro cell to include a second wiring pattern having
one or more same pattern segments among the plurality of pattern
segments, and the plurality of pattern segments include one or more
contact pattern, respectively.
[0015] According to a sixth aspect of the present invention, there
is provided a method of manufacturing a semiconductor integrated
circuit device comprising the steps of: forming a semiconductor
substrate having first and second macro cells each having a
plurality of elements formed; and wiring layers of N layers
(N.gtoreq.3) formed on said semiconductor substrate sequentially
from a first wiring layer to an N-th wiring layer, wherein the step
of forming said wiring layers of N layers includes: a sub-step of
forming said N-2 wiring layer such that the N-2 wiring layer on
said first macro cell includes a first wiring pattern having a
plurality of pattern segments wherein each of said plurality of
pattern segments has at least one contact pattern: a sub-step of
forming said N-1 wiring layer such that said N-1 wiring layer on
said first macro cell includes one or more same contact pattern as
the contact pattern formed on said first wiring pattern; and a
sub-step of forming said Nth wiring layer such that said Nth wiring
layer on said first macro cell includes a second wiring pattern
having one or more same pattern segments among the plurality of
pattern segments.
[0016] Thus, according to the above-mentioned structure and the
method, the increase in the wiring resistance can be restricted
even if the film thicknesses of the wiring layer of the macro cell
whose originally necessary number of wiring layers is small is
reduced when a plurality of macro cells whose originally necessary
number of metal wiring layers is embedded on the same semiconductor
chip. As a result, the potential drop caused by the increase in the
wiring resistance and the increase in the wiring delay can be
restricted, thereby preventing the deterioration of the
performance.
[0017] Additional object and advantages of the invention will be
set forth in the description which follows, and in part will be
obvious from the description, or may be learned by practice of the
invention. The object and advantages of the invention may be
realized and obtained by means of the instrumentalities and
combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0018] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
preferred embodiments of the invention, and together with the
general description given above and the detailed description of the
preferred embodiments given below, serve to explain the principles
of the invention.
[0019] FIG. 1 is a view showing one example of a pattern layout in
which an ASIC section and a memory section are arranged in an
adjacent area on an LSI chip;
[0020] FIG. 2 is a view showing parts of a cross-section of a
metallic wiring structure of an LSI on which the ASIC section of a
three-layered wiring and a memory section of a two-layered wiring
are embedded on a semiconductor substrate according to prior
art;
[0021] FIG. 3 is a view showing parts of a cross-section of a metal
wiring structure of an LSI of a first embodiment of the present
invention;
[0022] FIGS. 4A and 4B are views respectively showing contact
patterns formed in the metal wirings of the second and third wiring
layers of the metal wiring layers of FIG. 3;
[0023] FIG. 5 is a view showing one example of a wiring pattern of
the second wiring layer in the memory section of FIG. 3;
[0024] FIGS. 6A to 6C are views respectively showing the wiring
patterns of the third wiring layer in the memory section of FIG.
3;
[0025] FIG. 7 is a view showing parts of a cross-section of a metal
wiring structure of an LSI of a second embodiment of the present
invention;
[0026] FIGS. 8A to 8C are views respectively showing contact
patterns formed in the metal wirings of the second and third wiring
layers of the metal wiring layers of FIG. 7;
[0027] FIGS. 9A and 9B are views respectively showing modifications
of contact patterns formed in the metal wirings of the second and
third wiring layers of the metal wiring layers of FIG. 7;
[0028] FIGS. 10A to 10E are cross-sectional views respectively
showing metal wiring processes of the LSI of FIG. 3;
[0029] FIG. 11 is a cross-sectional view showing a modification of
the metal wiring process of the LSI of FIG. 3; and
[0030] FIGS. 12A to 12D are cross-sectional views respectively
showing metal wiring processes of the LSI of FIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
[0031] Embodiments of the present invention will now be described
with reference to the accompanying drawings.
[0032] In the LSI of this invention, a plurality of macro cells
whose originally necessary number of metal wiring layers differs is
embedded on the same semiconductor chip to have metal wiring layers
of N (N.gtoreq.3) layers. Then, the feature of the LSI of this
invention lies in the metal wiring structure of the macro cell
whose originally necessary number of metal wiring layers is
small.
[0033] FIG. 3 is a view showing parts of a cross-section of a metal
wiring structure of an LSI of a first embodiment of the present
invention. FIGS. 4A and 4B are views respectively showing contact
patterns formed in the metal wirings of the second and third wiring
layers of the metal wiring layers of FIG. 3.
[0034] The LSI of FIG. 3 comprises a first macro cell 11 and a
second macro cell 12. The first macro cell 11 has a wiring layer of
three layers. Each of three layers, which is made of a metal wire
layer (e.g., aluminum wiring), is formed on the semiconductor
substrate 10. Similarly, the second macro cell 12 has a wiring
layer of N layers. Each of N layers is formed on the semiconductor
substrate 10, and is made of a metal wiring layer.
[0035] The first macro cell 11 is an ASIC section including at
least one of a logic section such as a CPU and an analog section.
The second macro cell 12 is e.g., a semiconductor memory section in
which a memory cell array is formed. A sensing amplifier, a row
decoder, a secondary sensing amplifier and a write buffer, or other
circuit section may be formed in the semiconductor memory section.
Similar to the ASIC section 61 and the memory section 62 of FIG. 2,
the first macro cell 11 and the memory section 12 may be arranged
in the adjacent area on the LSI chip.
[0036] First, the following will explain the ASIC section 11.
[0037] In the ASIC section 11, the number of necessary metal wiring
layers is three. On the semiconductor substrate 10, a first
insulating layer 21, a first wiring layer 22, a second insulating
layer 23, a second wiring layer 24, a third insulating layer 25, a
third wiring layer 26, and a fourth insulating layer 27 are
sequentially stacked. Moreover, the ASIC section 11 has a first
contact plug 24a for connecting the second wiring layer 24 to the
first wiring layer 22, and a second contact plug 26a for connecting
the third wiring layer 26 to the second wiring layer 24.
[0038] The film thickness of the first wiring layer 22 can be e.g.
500 nm. Also, the film thickness of the second wiring layer 24 can
be e.g. 500 nm. The film thickness of the third wiring layer 26 can
be e.g. 1000 nm. Moreover, the film thickness of the second
insulating layer 23 can be e.g. 600 nm. The film thickness of the
third insulating layer 25 can be e.g. 700 nm. Also, the film
thickness of the fourth insulating layer 27 can be e.g. 600 nm.
[0039] The first and second contact plugs 24a and 26a may be formed
by a burying process. Also, the first contact plug 24a may be
formed as a part of the second wiring layer 24 at the same time.
Also, the second contact plug 26a may be formed as a part of the
third wiring layer 26 at the same time.
[0040] Next, the following will explain the memory section 12.
[0041] In the memory section 12, though the originally necessary
number of metal wiring layers is two, the memory section 12 may be
formed to have a three-layered wiring structure similar to the ASIC
section 11. Moreover, each layer of the memory section 12 can be
formed of the same material as the corresponding each layer of the
ASIC 11. Also, each layer of the memory section 12 can be formed to
have the same film thickness as the corresponding each layer of the
ASIC 11.
[0042] Furthermore, in order to connect the ASIC section 11 to the
memory section 12, e.g., a macro cell interconnection wiring 13 is
formed to be included in the third wiring layer.
[0043] The memory section 12 has the first insulating layer 21, the
first wiring layer 22, the second insulating layer 23, the second
wiring layer 24, the third insulating layer 25, the third wiring
layer 26, and the fourth insulating layer 27, which are
sequentially stacked on the semiconductor substrate 10. The ASIC
section 11 has the first contact plug 24a for connecting the second
wiring layer 24 to the first wiring layer 22, and the second
contact plug 26a for connecting the third wiring layer 26 to the
second wiring layer 24.
[0044] The first and second contact plugs 24a and 26a may be formed
by the burying process. Also, the first contact plug 24a may be
formed as a part of the second wiring layer 24 at the same time.
Also, the second contact plug 26a may be formed as a part of the
third wiring layer 26 at the same time.
[0045] Next, the following will explain the wiring pattern to be
designed on the second and third wiring layers 24 and 26 in the
memory section 12 with reference to FIGS. 5A to 6C. FIGS. 4A and 4B
are views each showing a contact pattern included in each of the
wiring patterns of the third and second wiring layers of FIG. 3.
FIG. 5 shows an example of the wiring pattern of the second wiring
layer of the memory cell section 12 (second macro cell). FIGS. 6A
to 6C show examples of patterns, which can be used as a wiring
pattern of the third wiring layer of the memory section.
[0046] The wiring pattern formed on the second wiring layer 24
comprises a plurality of pattern segments as shown in FIG. 5. A
pattern segment 121 shown by a thick line width is a power supply
line, and pattern segments 122 shown by a thin line width are
signal lines. Generally, the respective pattern segments have at
least one contact pattern as shown in FIG. 4B. In other words, FIG.
4B shows an enlarged part of each pattern segment. As shown in FIG.
4B, a contact pattern 24c is provided on a part 24b of the pattern
segment.
[0047] The contact patterns shown in FIG. 5 are formed in
accordance with a design rule, and they are connected to the first
wiring layer or the third wiring layer through contact plugs 24a
and 26a.
[0048] Next, the following will explain the third wiring layer 26.
In the LSI memory section 12 of the first embodiment, some examples
of the wiring patterns, which are applicable to the third wiring
layer, are shown with reference to FIGS. 6A to 6C.
[0049] The wiring pattern shown in FIG. 6A is an example to which
the same wiring pattern as the wiring pattern formed on the second
wiring layer 24 (FIG. 5) is applied. Moreover, in the wiring
pattern, a contact pattern is formed at the same position as the
wiring pattern formed in the second wiring layer 24. In other
words, if the part of each pattern segment is enlarged, the
enlarged part is shown in FIG. 4A. That is, a contact pattern 26c
is formed on a part 26b of the pattern segment. These contact
patterns are formed in accordance with the design rule, and they
are connected to the second wiring layer through the contact plug
26a.
[0050] Thus, the second wiring layer 24 and the third wiring layer
26 have the above-mentioned wiring patterns, thereby making it easy
to execute the process in generating the pattern of the metal
wiring layer of LSI by CAD (Computer Assistant Design).
[0051] In the case of generating the pattern of each metal wiring
layer by CAD, the wiring pattern of the first layer 22 and that of
the second wiring layer 24 are different from each other. However,
a load on the software of CAD is reduced since the wiring patter of
the second layer 24 and that of the third layer are the same as
each other. Similarly, since the contact patterns of the second and
third wiring layers are formed at the same position, the load on
the software of CAD is reduced.
[0052] Next, the wiring pattern shown in FIG. 6B will be explained.
The wiring pattern of FIG. 6B shows that only a pattern segment
121, serving as a power supply line, is extracted from the wiring
pattern of the second wiring layer (FIG. 5). Even in this wiring
pattern, the contact pattern is formed at the same position as the
contact pattern of the power supply line of the wiring pattern of
FIG. 6A.
[0053] In generating the wiring pattern of FIG. 6B by CAD, only the
pattern segment is extracted from the wiring pattern of the second
wiring layer, so that the wiring pattern can be generated. As a
result, the load on the software of CAD is reduced.
[0054] Next, the wiring pattern of FIG. 6C will be explained. The
wiring pattern of FIG. 6C shows only a critical path, i.e., a
signal line for determining the operation speed of LSI, which is
extracted from the plurality of pattern segments, serving as signal
lines of the wiring pattern of the second wiring layer (FIG. 5).
Even in this wiring pattern, the contact pattern is formed at the
same position as the contact pattern of the critical path of the
wiring pattern of FIG. 6A.
[0055] In generating the wiring pattern of FIG. 6C, only the
critical path is extracted from the wiring pattern of the second
wiring layer, so that the wiring pattern can be generated. As a
result, the load on the software of CAD is reduced.
[0056] As the other wiring patterns, which can be used in the third
wiring layer, there may be used a pattern in which only the signal
is extracted from the wiring pattern of FIG. 6C.
[0057] As explained above, according to the wiring structure of LSI
of the first embodiment, in forming the ASIC section 11 and the
memory section 12 on the same chip, the wiring layout of the second
wiring layer 24 of the memory section 12 is formed on the third
wiring layer 26 on the same scale. The film thickness of the wiring
is formed to have the same as the thickness of the third wiring
layer 26 of the ASIC section 11.
[0058] Therefore, it is assumed that there is used the process of
flattening the surface of the metal wiring layer other than the
uppermost metal wiring layer and the surface of the insulating
layer other than the uppermost insulating layer. Even if the film
thickness of the second wiring layer 24 of the memory section 12 is
reduced, the reduction of the film thickness is compensated by the
wiring pattern 26b of the third wiring layer. As a result, the
increase in the wiring resistance of the wiring pattern of the
second wiring layer can be restrained.
[0059] It is assumed that only the power supply line for supplying
the operation power of the memory section 12 is provided as the
wiring pattern of the second wiring layer. In this case, the
increase in the wiring resistance of the wiring pattern of the
second layer can restrained, the voltage drop caused by the
increase can be restrained, and the deterioration of the
performance can be controlled.
[0060] It is assumed that the power supply line for supplying the
operation power of the memory section 12 and the signal line for
transmitting the signal of the memory section 12 are provided as
the wiring pattern of the second wiring layer. In this case, the
increase in the wiring resistance of the wiring pattern of the
second layer can restrained, the voltage drop caused by the
increase, and the increase in the wiring delay can be restrained,
and the deterioration of the performance can be controlled. In the
power supply line and the signal line of the wiring pattern of the
second wiring layer, only the signal line (critical path) for
determining the operation speed of the memory section 12 may be
provided as the wiring pattern of the third wiring layer.
[0061] The wiring pattern of the third wiring layer is the same as
that of the second wiring pattern, and both have the same
potential, and a capacitive coupling therebetween is relatively
small.
[0062] Next, the following will explain the second embodiment of
the present invention.
[0063] FIG. 7 shows one example of the cross-section of the metal
wiring structure of LSI of the second embodiment of the present
invention. FIGS. 8A to 8C show the enlarged parts (including the
contact patterns) of the wiring patterns of the third wiring layer
of FIG. 7, the second wiring layer, and the first wiring layer,
respectively.
[0064] As compared with the metal wiring structure of the LSI of
the first embodiment, the LSI of the second embodiment has the
structure in which only the contact pattern 24c of the first wiring
layer is formed on the wiring pattern of the second wiring layer in
the memory section 12a. In other words, the wiring pattern 24b of
the first embodiment is not formed in the second embodiment.
Moreover, in the second embodiment, the wiring pattern of the third
wiring layer of the memory section 12a is the same as the wiring
pattern of the first wiring layer 22. The other structure of the
second embodiment is the same as the first embodiment, and the same
reference numerals are added to the common portions, and the
explanation is omitted.
[0065] According to the wiring structure of the LSI of the second
embodiment, in forming the ASIC section 11 and the memory section
12 on the same chip, the wiring layout of the second wiring layer
24 of the memory section 12a is originally formed on the third
wiring layer 26. In this case, the film thickness of the wiring is
formed to have the same thickness of the third wiring layer of the
ASIC section 11. On the second wiring layer 24 of the memory
section 12a, there is formed the pattern on which only the contact
pattern 24c of the wiring layout formed on the third wire layer 26
is left. Then, the diameter of the contact pattern 24c formed on
the second wiring layer 24 may be set to V1+2.times.h1 where a
diameter of the contact pattern on the first wiring layer 22 of the
memory section 12a is V1, a fringe of the contact pattern 24c of
the second wiring layer 24 is h1.
[0066] The above contact pattern design can simplify the software
processing on the CAD, thereby improving the coefficient of the
design processing.
[0067] Therefore, even if the film thickness of the contact pattern
24c of the second wiring layer 24 is reduced by the use of the
process for flattening the surface of the second wiring layer 24,
the film thickness can be compensated by the third wiring layer 26.
As a result, the increase in the wiring resistance can be
restrained.
[0068] The pattern of the second wiring layer 24 is only the
contact pattern 24c. Then, the ratio of the pattern area of the
second wiring layer 24 to the pattern area of the third wiring
layer 26 is small, and the ratio of the pattern area of the second
wiring layer 24 to the pattern area of the second wiring layer 22
is small. Since the distance between the third wiring layer 26 and
the first wiring layer 22 is large, the capacitive coupling between
the opposing wiring patterns is smaller than the case of the first
embodiment.
[0069] Furthermore, the second embodiment can be applied to a case
in which the difference between the number of wiring layers
necessary to the metal wiring of the ASIC section 11 and the number
of wiring layers necessary to the metal wirings of the memory
section 12a are two or more. In other words, the wiring layers
having only the contact pattern formed are layered to correspond to
the difference, so that the same effect as the mentioned above can
be obtained.
[0070] Next, the following will explain the wiring structure of the
LSI of the third embodiment of the present invention.
[0071] In this third embodiment, the wiring width of the wiring
pattern of the second wiring layer and that of the wiring pattern
of the third wiring layer is different from each other. FIGS. 9A
and 9B show the enlarged parts (including the contact patterns) of
the wiring patterns of the third and second wiring layers,
respectively. The contact patterns 24c and 26c shown in these
figures are formed to have a difference in conversion between the
wiring width of the wiring pattern 26b of the third wiring layer
and that of the wiring pattern 24b of the second wiring layer. The
other structure of the second embodiment is the same as the first
embodiment, and the same reference numerals are added to the common
portions, and the explanation is omitted.
[0072] The third embodiment can be applied to a case in which the
design rule of the third wiring layer 26 is 1.2 times as large as
that of the second wiring layer 24. More specifically, it is
assumed that a maximum wiring width of the wiring pattern 24b of
the second wiring layer is 0.5 .mu.m and a maximum wiring width of
the wiring pattern 26b of the third wiring layer is 0.6 .mu.m. The
wiring pattern 26b of the third wiring layer is designed such that
both sides of the wiring width of the wiring pattern 24b of the
second wiring layer are enlarged by .DELTA.T =0.05 .mu.m.
[0073] According to the wiring structure of the LSI of the third
embodiment, if the design rule of the second wiring layer 24 and
that of the third wiring layer 26 are different from each other,
the difference in conversion between the wiring widths is provided
to correspond to the design rule of each of the wiring layers. This
is useful in realizing the chip structure, which does not violate
the design rule.
[0074] Moreover, the above contact pattern design can simplify the
software processing on the CAD, thereby improving the coefficient
of the design processing.
[0075] Next, the following will explain the manufacturing method of
the LSI of the first embodiment of the present invention with
reference to FIGS. 10A to 10E.
[0076] The element is formed in each of the first macro cell area
11 and the second macro cell area 12, so that the first insulating
layer 21 is formed on the semiconductor substrate. On the first
insulating layer 21, there is formed the first wiring layer 22 for
electrically conducting the respective electrodes of the element
formed on the semiconductor substrate with a predetermined pattern.
Moreover, the second insulating layer 23 is formed on the first
wiring layer (FIG. 10A).
[0077] Next, in the second insulating layer 23, there is formed a
hole for forming the contact plug on the contact pattern on the
wiring pattern of the first wiring layer. Then, a burying
processing is provided to the hole, thereby forming the first
contact plug 24a (FIG. 10B).
[0078] After forming the contact plug 24a, there is formed the
second wiring layer 24 in which the wiring pattern is designed to
be different from the first wiring layer. Then, on the second
wiring layer, there is formed the third insulating layer 25 (FIG.
10C).
[0079] Next, in the third insulating layer 25, there is formed a
hole for forming the contact plug on the contact pattern formed on
the wiring pattern of the second wiring layer. Then, a burying
processing is provided to the hole, thereby forming the first
contact plug 26a (FIG. 10D).
[0080] After forming the contact plug 26a, the third wiring layer
24 is formed. In the memory section 12, there is formed the third
wiring layer 26 in which the same wiring pattern as the second
wiring layer is designed (FIGS. 5 and 6A). Also, in forming the
third wiring layer, the macro interconnection wiring 13 is
simultaneously formed. On these third wiring layer 26 and the macro
interconnection wiring layer 13, there is formed the fourth
insulating layer 27. Thereby, the manufacture of LSI is completed
(FIG. 10E).
[0081] In forming the wiring layer other than the third wiring
layer 26 and the insulating layer, there is a case in which the
surface of the wiring layer or that of the insulating layer is
flattened.
[0082] Also, the wiring pattern shown in FIG. 6B or FIG. 6C can be
used as the wiring pattern of the second wiring layer.
[0083] Further, according to the above-mentioned manufacturing
method, the wiring width of the wiring pattern of the third wiring
layer can be made different from that of the second wiring
layer.
[0084] The contact plug 24 is used to connect the wiring contact
pattern of the second wiring layer to the contact pattern of the
first wiring layer 22. Then, the contact plug 24 may be formed
simultaneously with the wiring pattern 24b of the second wiring
layer when the second wiring layer 24 is formed after forming the
hole on the second insulating layer 23.
[0085] The contact plug 26a is used to connect the wiring contact
pattern of the third wiring layer to the contact pattern of the
second wiring layer 24. Similar to the case of the contact plug
24a, the contact plug 26a may be formed simultaneously with the
wiring pattern of the third wiring layer in forming the third
wiring layer 26.
[0086] The LSI of the third embodiment can be manufactured by the
above-mentioned manufacturing method. The detailed explanation of
the manufacturing method of the LSI of the third embodiment will be
omitted.
[0087] Next, the following will explain the manufacturing method of
the LSI of the second embodiment with reference to FIGS. 12A to
12D.
[0088] First of all, the element is formed in each of the first
macro cell area 11 and the second macro cell area 12a, so that the
first insulating layer 21 is formed on the semiconductor substrate.
Thereafter, since the processing up to the formation of the contact
plug 24a is the same as the above-mentioned manufacturing method,
the specific explanation will be omitted.
[0089] After forming the contact plug 24a, on the ASIC section 11,
there is formed the second wiring layer 24 in which the wiring
pattern different from the first wiring layer is designed. On the
other hand, in the memory section 12a, there is formed the contact
pattern 24c of FIG. 8B on the contact plug 24a (FIG. 12A). A
lithography processing and a flattening processing must be
performed in forming the contact pattern in the memory section
12a.
[0090] Next, on the second wiring layer 24 and the contact pattern
24c, there is formed the third insulating layer 25 (FIG. 12B). In
the third insulating layer 25, there is formed the hole for forming
the contact plug on the contact pattern of the second wiring layer.
Then, the burying processing is provided to the hole, so that the
contact plug 26a is formed (FIG. 12C).
[0091] After forming the contact plug 26a, the third wiring layer
26 is formed. In the memory section 12a, there is formed the third
wiring layer 26 in which the same wiring pattern as the first
wiring layer is designed (FIGS. 5 and 6A). In forming the third
wiring layer, the macro interconnection wiring 13 is simultaneously
formed. On these third wiring layer 26 and the macro
interconnection wiring layer 13, there is formed the fourth
insulating layer 27. Thereby, the manufacture of LSI is completed
(FIG. 12D).
[0092] In forming the wiring layer other than the third wiring
layer 26 and the insulating layer, there is a case in which the
surface of the wiring layer or that of the insulating layer is
flattened.
[0093] Further, according to the above-mentioned manufacturing
method, the wiring width of the wiring pattern of the third wiring
layer can be made different from that of the second wiring
layer.
[0094] The contact plug 24a is used to connect the wiring contact
pattern of the second wiring layer to the contact pattern of the
first wiring layer 22. Then, similar to the case explained with
reference to FIG. 11, the contact plug 24a may be formed
simultaneously with the wiring pattern 24b of the second wiring
layer when the second wiring layer 24 is formed after forming the
hole on the second insulating layer 23. Also, the wiring contact
pattern of the third wiring layer may be formed in the same
method.
[0095] Thus, according to the present invention, the increase in
the wiring resistance can be restricted even if the film
thicknesses of the wiring layer of the macro cell whose originally
necessary number of wiring layers is small is reduced when a
plurality of macro cells whose originally necessary number of metal
wiring layers is embedded on the same semiconductor chip. As a
result, the potential drop caused by the increase in the wiring
resistance and the increase in the wiring delay can be restricted,
thereby preventing the deterioration of the performance.
[0096] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalent.
* * * * *