U.S. patent application number 09/351203 was filed with the patent office on 2002-05-09 for system and method for generating a flat mask design for projecting a circuit pattern to a spherical semiconductor device.
Invention is credited to Feng, Zhiqiang, Fukano, Atsuyuki, Koide, Hideki.
Application Number | 20020056074 09/351203 |
Document ID | / |
Family ID | 22233236 |
Filed Date | 2002-05-09 |
United States Patent
Application |
20020056074 |
Kind Code |
A1 |
Fukano, Atsuyuki ; et
al. |
May 9, 2002 |
System and method for generating a flat mask design for projecting
a circuit pattern to a spherical semiconductor device
Abstract
The present invention provides a method for segmenting and
mapping a two-dimensional conventional circuit pattern to a flat
mask for projection onto a three-dimensional surface. The circuit
pattern is first segmented into a plurality of circuit segments
enclosed in a plurality of base units of an imposed grid system.
Subsequently, locations and the boundary conditions for a plurality
of mask segments on the mask are determined such that no unneeded
overlapping at the boundaries of the projected image on the
spherical shaped semiconductor device is possible. The mask, along
with a photolithography system having a plurality of mirrors,
projects the circuit pattern onto the spherical shaped
semiconductor device.
Inventors: |
Fukano, Atsuyuki; (Addison,
TX) ; Feng, Zhiqiang; (Nagareyama-shi, JP) ;
Koide, Hideki; (Tokyo, JP) |
Correspondence
Address: |
David M. O'Dell
Haynes and Boone, L.L.P.
3100 Bank of America Plaza
901 Main Street
Dallas
TX
75202-3789
US
|
Family ID: |
22233236 |
Appl. No.: |
09/351203 |
Filed: |
July 9, 1999 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60092442 |
Jul 10, 1998 |
|
|
|
Current U.S.
Class: |
716/55 |
Current CPC
Class: |
G03F 7/70425 20130101;
G03F 1/50 20130101; G03F 7/24 20130101; G03F 7/70433 20130101; G03F
7/703 20130101; G03F 7/70216 20130101 |
Class at
Publication: |
716/20 |
International
Class: |
G06F 017/50 |
Claims
What is claimed is:
1. A method for generating a mask from a conventional design
pattern for projection by a photolithography system onto a three
dimensional surface, the method comprising the steps of: segmenting
the design pattern into a plurality of design segments; and mapping
each design segment onto a mask segment of the mask based on a
predetermined relation.
2. The method of claim 1 wherein the step of segmenting further
includes the steps of: imposing a grid system, wherein boundaries
of the design segment are defined by a polygonal shape base unit of
the grid system; and identifying a plurality of points at which the
segmented design intersect with the boundaries of the polygonal
shape base unit.
3. The method of claim 1 wherein the mask segments are on a
plurality of radially concentric orbits on the mask.
4. The method of claim 1 wherein the number of mask segments is
predetermined by the configuration of the photolithography system;
and wherein the mask segments are located to prevent unnecessary
image overlapping when the mask segments are projected onto the
three dimensional surface.
5. The method of claim 1 wherein the step of mapping further
includes the steps of: determining boundary conditions of the mask
segments; and mapping each design pattern of each design segment
onto the corresponding mask segment by using an intermediate
graphic entity according to the boundary conditions of the mask
segments; wherein the boundary conditions of the mask segments are
determined to prevent unnecessary overlapping of the mask segment
after being projected onto the three dimensional surface.
6. A method for generating a mask from a conventional circuit
design for projection onto a surface of a non-planar semiconductor
device, the method comprising the steps of: imposing a grid system
on the circuit design, the grid system having a first number of
columns and a second number of rows; segmenting the circuit design
into a plurality of circuit segments, wherein the circuit segment
is enclosed in the grid segment; identifying a plurality of
intersection points in each grid segment at which the circuit
segment crosses boundaries of the grid segment; converting the grid
segment to a plurality of mask segments by establishing boundary
conditions for each of the mask segments using a predetermined
relationship to prevent overlapping at boundaries of the projected
image on the non-planar shaped semiconductor device; and mapping
the circuit segments onto the mask, the mask having a number of
circular orbits corresponding to the first number of columns, and a
number of mask segments on each orbit corresponding to the second
number of rows.
7. The method of claim 6 wherein the mask segments on each orbit is
a uniform distance from the neighboring mask segments.
8. The method of claim 6 wherein the orbits are radially
concentric.
9. The method of claim 6 wherein the grid segments from the same
row in the grid system reside on the same orbit.
10. The method of claim 6 wherein the mask segments mapped from the
grid segments of the same column are aligned.
11. A system for generating a mask from a circuit design for
projection onto a surface of a spherical semiconductor device to
implement the circuit design thereon, the system comprising: means
for imposing a grid system on the circuit design, the grid system
having a first number of columns and a second number of rows; means
for segmenting the circuit design into a plurality of circuit
segments, wherein the circuit segment is enclosed in the grid
segment; means for identifying a plurality of intersection points
in each grid segment at which the circuit segment crosses
boundaries of the grid segment; means for converting the grid
segment to a plurality of mask segments by establishing boundary
conditions for each of the mask segments using a predetermined
relationship to prevent overlapping at boundaries of the projected
image on the spherical shaped semiconductor device; and means for
mapping the circuit segments onto the mask, the mask having a
number of circular orbits corresponding to the first number of
columns, and a number of mask segments on each orbit corresponding
to the second number of rows.
12. The system of claim 11 wherein the mask segments on each orbit
keeps a uniform distance from the neighboring mask segments.
13. The system of claim 11 wherein the orbits having different
diameters from the same center point.
14. The system of claim 11 wherein the grid segments from the same
row in the grid system reside on the same orbit.
15. The system of claim 11 wherein the grid segments from the same
column are aligned; and wherein the aligned mask segments can be
exposed to a light source simultaneously in a photo lithographic
process.
16. A system for projecting a circuit design onto the surface of a
spherical shape semiconductor device, said system comprising: a
mask having a plurality of separate mask segments thereon
containing the information of the circuit design; and a mirror
assembly having a plurality of mirror segments for projecting the
mask segments onto the spherical shaped semiconductor device;
wherein there is no unnecessary overlapping at the boundaries of
the images projected from any two mask segments.
17. The system of claim 16 wherein the circuit design is divided
into a plurality of circuit segments to be mapped to the mask
segments.
18. The system of claim 16 wherein the mask has a plurality of
concentric orbits, and where the plurality of mask segments reside
on the orbits and have prescribed distances maintained from
neighboring mask segments.
19. The system of claim 18 wherein each of the orbits has the same
number of mask segments.
20. The system of claim 18 wherein the mask segments on each of the
orbits are radially aligned.
21. The system of claim 16 wherein the mirrors assembly has the
same number of mirror segments as the number of mask segments for
projecting the circuit design on to the spherical shaped
semiconductor device.
Description
CROSS REFERENCE
[0001] This application claims the benefit of U.S. Provisional
Application Ser. No. 60/092,442, filed on Jul. 10, 1998.
BACKGROUND OF THE INVENTION
[0002] The invention relates generally to photolithography, and
more particularly, to a system and method for mapping a
two-dimensional flat grid design to a special mask design for
further projection onto a three-dimensional object.
[0003] Conventional integrated circuits, or "chips," are formed
from two dimensional or flat surface semiconductor wafers. The
semiconductor wafer is first manufactured in a semiconductor
material manufacturing facility and is then provided to a
fabrication facility. At the latter facility, several layers are
processed onto the semiconductor wafer surface using various design
concepts, such as very large scale integrated ("VLSI") design.
Although the processed chip includes several layers of materials
fabricated thereon, the chip still remains relatively flat.
[0004] One of the most important steps of manufacturing the chip is
to process the semiconductor substrate through a series of photo
lithographical processes so that the VLSI design can be transferred
to the relative flat plane of the wafer. Since the VLSI design
normally defines the entire circuit design, including different
layers of materials such as poly, metal, etc., a plurality of photo
masks must be made to facilitate the photolithography for each of
those layers. In a conventional mask design process, it is
conventional to project the pattern for each layer of material of
the entire circuit to a flat glass mask, usually in a rectangular
shape. Although several intermediate technical steps are involved,
the making of the mask is a straightforward one-to-one projection
from the VLSI design to the glass. In other words, the VLSI design
is directly projected to the mask.
[0005] In patent application Ser. No. 08/858,004 filed on May 16,
1997, a method and apparatus for manufacturing spherical-shaped
semiconductor integrated circuit devices is disclosed. The above
patent describes and teaches certain methods for performing
photolithography on a spherical substrate.
[0006] However, there are numerous problems associated with imaging
a two-dimensional circuit design to a three-dimensional object,
such as a sphere. Since the circuit design on the mask is projected
on the sphere, a conventional mask produced directly from the
circuit design does not work. For example, a rectangular entity on
the VLSI design can not maintain its shape while it is projected on
the sphere. Thus, direct projection from the VLSI design to the
glass mask can no longer be used. A new type of mask design is
needed to accommodate the need of producing the circuit on the
sphere.
[0007] Therefore, what is needed is a system and method for mapping
a conventional circuit design onto a special mask for projection
onto a three-dimensional surface such as a spherical shaped
semiconductor device.
SUMMARY OF THE INVENTION
[0008] The present invention, accordingly, provides a system and
method for mapping a two-dimensional circuit pattern to a flat
mask, which is further projected onto a three dimensional
substrate. To this end, one embodiment of the method generates a
mask containing a conventional circuit pattern for projection onto
a surface of a spherical semiconductor device. The circuit pattern
is separated into a plurality of circuit segments, so that each
circuit segment is enclosed in a polygonal shape. The circuit
segments are then mapped into mask segments. And the boundary
conditions for each of the mask segments are adjusted to prevent
unnecessary overlapping at boundaries of the projected image on the
sphere.
[0009] In one embodiment of the invention, the mask has a plurality
of radially concentric circular orbits wherein the mapped circuit
segments, referred to as mask segments, reside.
[0010] An advantage of the present invention is that the mask
remains two-dimensional. Therefore, the mask can be made like any
conventional mask using the conventional mask making tools.
[0011] Another advantage of the present invention is that the
circuit pattern can be completed using conventional design tools
without excessive concerns about having the circuit design being
implemented on a three dimensional surface instead of a flat
surface.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates a schematic of a two-dimensional circuit
pattern overlapping a grid system on an x-y plane.
[0013] FIG. 2 is a detailed illustration of a portion of the
circuit of FIG. 1.
[0014] FIG. 3 is a detailed illustration of the portion of the
circuit in FIG. 2 where additional intersection or boundary points
between the circuit pattern and the grid are identified.
[0015] FIG. 4 illustrates a schematic of the two-dimensional
circuit pattern of FIG. 1 separated into segments.
[0016] FIG. 5 is a detailed illustration of a portion of the
schematic of FIG. 4.
[0017] FIG. 6 shows a mask design created by mapping the segments
of the circuit pattern of FIG. 1 for projecting the circuit pattern
onto a spherical surface.
[0018] FIG. 7 illustrates a portion of the mask of FIG. 6
illuminated and projected onto a spherical surface using a
photolithography system having a plurality of mirrors.
[0019] FIG. 8 illustrates a detailed view of three aligned mask
segments.
[0020] FIG. 9a shows steps to form one type of mask segment in FIG.
6 adjusted for three-dimensional application.
[0021] FIG. 9b shows steps to form another type of mask segment in
FIG. 6 adjusted for three-dimensional application.
[0022] FIG. 9c shows steps to form a third type mask segment type
in FIG. 6 adjusted for three-dimensional application.
[0023] FIG. 10 presents a close view of the grid system of FIG. 1
with a coordinate system imposed thereon.
[0024] FIG. 11a illustrates the boundary conditions of a first type
of mask segments of FIG. 6.
[0025] FIG. 11b illustrates the boundary conditions of a second
type of mask segments of FIG. 6
[0026] FIG. 11c illustrates the boundary conditions of a third type
of mask segments of FIG. 6.
DESCRIPTION OF THE EMBODIMENTS
[0027] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Techniques and requirements that are only specific
to certain embodiments should not be imported into other
embodiments. Also, specific examples of measurements, quantities,
and processes are described below to help clarify the invention.
These are, of course, merely examples and are not intended to limit
the invention from that described in the claims.
[0028] Before continuing, several terms may be defined for better
clarity. The set of all points P in space whose distance r is
called the "sphere" of radius R and center O. A sphere is a surface
and not a solid body, although it may enclose a solid body, which
is properly called interior of the sphere. In particular, the
center of a sphere is not a point of the sphere but is a point of
the interior of the sphere. The section of the sphere made by a
plane passing through the center O of the sphere is called a "great
circle" (or geodesics) of the sphere. The section of the sphere
made by a plane which does not pass through the center of the
sphere is called a "small circle" of the sphere.
[0029] Referring now to FIGS. 1, 2, and 3, a grid system 20 having
a plurality of grid segments 21 contains a circuit pattern 22. In
one embodiment, the grid system has three rows and fifteen columns
(3.times.15) for the purpose of facilitating one-to-one mapping of
the circuit pattern to a mask. The number of columns and rows, as
discussed further below, are largely determined by the
configuration a photolithography system having a plurality of
mirrors, such as one disclosed and explained in the U.S. patent
(U.S. Ser. No. 60/092,295), which is herein incorporated by
reference. The circuit pattern 22 falls within a plurality of the
grid segments 21. The grid segments 21 are used as the base units
to divide the entire circuit pattern 22 into sections for mapping
onto a mask (FIG. 6), which is further projected onto a spherical
shaped device as discussed below. A conventional circuit pattern
usually defines the design pattern by using multiple polygons,
usually rectangles and squares, the boundary of which can be
identified by a group of corner points. As shown in FIG. 2, a
plurality of critical points 24 are identified that define numerous
entities of the circuit pattern. In additional to these critical
points 24, boundary points 26, as shown in FIG. 3, which are
intersection points between the circuit entities and the grid
segments, should also be recognized for mapping purpose. Since each
grid segment 21 shares a common boundary with an adjacent segment,
the boundary points 26 are normally shared by or meshed with
adjacent circuit portions.
[0030] For simplifying the mapping process, it is understood that
each grid segment 21 has the same size in the two-dimensional grid
system. Further, each grid segment 21 is labeled distinctively as
follows: A(1), A(2), . . . , A(15); B(1), B(2), . . . , B(15);
C(1), C(2), . . . , C(15), whereas the rows are indicated by A, B
and C, and columns by numeral (1) to (15). Thus every grid segment
21 can be swiftly and easily identified if needed.
[0031] Referring now to FIG. 4, each grid segment 21 containing
parts of the circuit 22 is separated from adjacent grid segments.
Specifically, FIG. 4 shows specific parts of the circuit 22
enclosed within the grid segments 21, hereinafter referred to as
circuit segments. Referring also to FIG. 5, a detailed view of the
segmented circuit segments is presented. All the critical points 24
and boundary points 26 are clearly identified.
[0032] Turning now to FIG. 6, a layout of a mask 30 is shown with a
plurality of mask segments 31 created or mapped from the circuit
segments 21 of FIG. 5. The mask segments 31 contain information for
projection onto a three-dimensional surface, such as a spherical
shape semiconductor device. Each circuit segment 21 is mapped to a
mask segment 31 in a unique position on the flat mask 30. In this
particular embodiment, the original grid system 20 in FIG. 1 has
three rows, A, B and C. After mapping, the mask has correspondingly
three orbits Am, Bm, and Cm respectively, wherein each orbit has 15
mask segments 31. FIG. 6 illustrates the mask segments 31 as small
squares for the sake of simplicity. However, it is understood that
in the preferred embodiment, the mask segments 31 are in distorted
shapes. FIGS. 8-11 discuss different shapes for the mask segments,
below.
[0033] Another feature of the layout of the mask 30 is that the
circuit segments 21 originally belonging to the same column are now
aligned in the three orbits. For example, A(15), B(15) and C(15) of
the grid system 20, are now aligned linearly as Am(15), Bm(15) and
Cm(15). This is for the convenience of exposing and projecting the
circuit pattern onto the sphere in a photo lithographic
process.
[0034] As shown in FIG. 7, when the aligned mask segments 31, such
as Am(15), Bm(15) and Cm(15), are exposed to a light source, images
or patterns thereon are projected simultaneously on a mirror
assembly 32. For the sake of example, the mirror assembly 32 may be
of the type described in the above-incorporated U.S. patent (U.S.
Ser. No. 60/092,295). The mirror assembly 32 is represented, for
the sake of simplicity, by three mirrors Ar, Br, and Cr. These
mirrors Ar, Br, and Cr reflect three mask segments 31 onto a sphere
34 to form three segments on the sphere. Although not shown, more
mirrors corresponding to all the mask segments 31 simultaneously
project the remaining mask segments onto the sphere 34. After the
projection, three belt shaped areas 36 (hereinafter "belts") are
formed in such a way that they occupy a middle section of the
sphere 34, much like the stripe around a ball used for pocket
billiards.
[0035] The boundaries of each belt are small circles parallel to a
common great circle. That is, an imaginary great circle 37, shown
as a phantom line on the sphere 34 in FIG. 7, resides in the middle
of the center belt, and the other two belts are equally spaced from
the great circle 37 with boundaries defined by a plurality of small
circles. The belts 36 are further segmented by a plurality of great
circles 38, which are perpendicular to the great circle 37, to form
a plurality of spherical segments 39. These spherical segments 39
corresponds to the mask segments 31 on the mask 30. In this
particular embodiment, pattens on mask segments Bm(n) form the
center belt, and mask segments Am(n) and Cm(n) form two other
belts, on both sides of Bm(n).
[0036] In addition, the design of the mask 30 depends largely on
the design of the entire photolithography system. For example, if
it is determined that three belts on the spherical shaped
semiconductor device are desired, then the mask should have only
three orbits, and each orbit requires a ring of mirrors as
explained in the above mentioned U.S. patent (U.S. Ser. No.
60/092,295). Similarly, if a certain number of spherical segment 39
is desired, then each ring of mirrors may have the same number of
mirrors, and therefore, each orbit may have the same number of mask
segments thereon. Further, the distance between the centers of the
mirrors, such as D1 and D2 in FIG. 7, affect the distance necessary
between corresponding orbits on the mask 30. Moreover, other
factors such as the distance between the mask 30 to the center of
the mirrors, the distance between the spherical shaped
semiconductor devices and the mirrors, and the configuration of the
mirror arrangement, e.g., the angle at which each mirror tilts, all
collectively affect the design of the mask.
[0037] To design the mask 30, the shape of each mask segment 31
should be determined once the orbits and mask segments are
determined. FIG. 8 is a detailed view of one group of the aligned
mask segments of FIG. 7. Since all the mask segments 31 on a
particular orbit share the same shape, the three mask segments
shown in FIG. 8 represent all the shapes of the mask segments in
this particular case. It can be seen that each mask segment is in a
rather distorted shape. Further, each aligned mask segment is
maintained a certain distance apart from the other as mentioned
above. The distance kept between any two orbits is to prevent
"unnecessary" image overlapping of the circuit pattern on the
sphere projected from the mask segments of two different
orbits.
[0038] The shapes of the mask segments 31 bear a certain
mathematical relationships with the spherical segments. As shown in
FIG. 7, since the shape of each of the spherical segments 39 is a
result of the projection of a mask segment through a mirror, a
one-to-one relationship can be determined between the boundary
lines of the spherical segment 39 and the boundary lines of the
mask segment 31. However, this relationship may likely change every
time any change has been made to the configuration of the elements
of the entire photolithography system, such as the configuration of
the mask, the mirrors, and the size of the spherical shaped
semiconductor devices.
[0039] Through the aid of modern computing tools such as a
computer, a series of mathematical calculations can precisely
determine the shapes of the mask segments. The objective is to
avoid any "unnecessary" image overlapping on the boundary of any
two spherical segments 39 on the sphere due to distortion of the
circuit pattern on the mask segments 31 after the projection.
Certain overlapping on the boundaries of the spherical segments 39
may be desired to merge the circuit pattern on each segment, but no
excessive overlapping are desired and the overlapping should be
consistent.
[0040] Once the shapes of the mask segments are defined, that is,
the four corners and four boundary lines of each mask segment are
identified, specific mapping operations may occur. Specifically, in
order to map the circuit pattern in each circuit segment 21 of
FIGS. 4 and 5 to a mask segment 31, further mathematical
derivations are necessary. Since in this case, only three different
types of mask segment logically exist, only three different
conversion methods are involved.
[0041] FIGS. 9a, 9b, and 9c suggest potential steps taken by a
computer to form the mask segments on the different orbits. In FIG.
9a, (Xa(n), Ya(n)) denotes the coordinates of any point on one mask
segment on the orbit Am. Three intermediate steps are taken to
modify the shape of an original circuit segment 21, wherein any
point in the circuit segment 21 is represented by (X, Y).
[0042] In step one, all four corners of the circuit segment 21 are
changed to the known four corners of the mask segment 31.
Coordinate (X1, Y1) represents all points in this first
intermediate shape 40.
[0043] In step two, all the points in the first intermediate shape
40 denoted by coordinate system of (X1, Y1) are formed into a
second intermediate shape 42, whereas all the points therein are
denoted by the coordinate (X2, Y2). Since only the right side
boundary is expanded and curved, all the coordinates in the Y1 or
Y2 direction do not change; only the coordinates in the X1 or X2
direction change. Two sets of mathematical formulas can be found to
represent the changes. One is for the points in the center area
bound by the phantom lines 44 and 46 inclusive, and the another for
all the points above the line 44 or below the line 46.
[0044] Finally, in step three, the top and bottom boundaries of the
second intermediate shape 42 can be expanded and curved to obtain
the desired mask segment 31 of orbit Am. If the orbit is the outer
most orbit, the left side boundary of the second intermediate shape
42 does not need to change since, after the projection, there will
be no overlapping with any neighboring spherical segments on that
boundary. Consequently only one set of mathematical formulas is
needed for points on the left of the phantom line 48. In FIG. 9b,
similar changes are made to the mask segments of orbit Cm. Since
orbit Am and Cm reside equidistant on opposite sides of the
"equator" of the spherical shaped semiconductor device, the overall
shape of the mask segments on orbit Cm are basically mirror images
of the mask segments on orbit Am, although the data contained in
each mask segment may be different. Thus similar intermediate steps
are suggested to map any point, with the only difference being the
left, top and bottom boundaries. If FIG. 9c, for the mask segments
on orbit Bm, since only the top and bottom boundaries need to be
changed into curves, only one step is taken to achieve the final
result and consequently only one mathematical formula is
involved.
[0045] For the sake of illustration, some detailed mathematical
formulas are provided below to explain the transformation from the
circuit segments 21 to the mask segments 31. It is understood,
however, that the formulas are for a specific embodiment and for a
specific configuration of the entire photolithography system, and
are not intended to limit the invention.
[0046] Now turning to FIG. 10, as described above relating to FIG.
1, in order to generated the mask 30, the grid 20 is divided into
3.times.15 circuit segments 21. It is assumed that each circuit
segment 21 is a 209.4.times.209.4 .mu.m square. Accordingly, in the
grid system, the center point of each segment 21 can be assigned
with a unique coordinate. For the sake of reference, the origin of
the coordinate system is set at the center segment B(8) having the
coordinates (X, Y). Thus, the center of segment C(1) has coordinate
(Xc(1), Yc(1)), which is a displacement from the origin according
to the following equation:
Xc(1)=X+209.4 .mu.m equation (1)
Yc(1)=Y+7.times.209.4 .mu.m equation (2)
[0047] Consequently, the coordinates for the center points of the
circuit segments 21 on column A, B and C can be generally
represented as follows:
Xa(n)=X-209.4 equation (3)
Xb(n)=X equation (4)
Xc(n)=X+209.4 equation (5)
Ya(n)=Yb(n)=Yc(n)=Y-209.4(n-8) equation (6)
[0048] where n=1, 2, . . . , 15 and wherein all distances are
measured in .mu.m.
[0049] In a particular circuit segment, the span of of the circuit
segments 21 parallel to the X axis is determined as follows:
1 A(n): -0.5 L > X .gtoreq. -1.5 L B(n): 0.5 L > X .gtoreq.
-0.5 L 1.5 L .gtoreq. X .gtoreq. 0.5 L
[0050] and the span of the segments 21 along the Y axis is as shown
below:
2 A(1), B(1), C(1): 7.5 L .gtoreq. Y .gtoreq. 6.5 L A(2), B(2),
C(2): 6.5 L > Y .gtoreq. 5.5 L A(3), B(3), C(3): 5.5 L > Y
.gtoreq. 4.5 L A(4), B(4), C(4): 4.5 L > Y .gtoreq. 3.5 L A(5),
B(5), C(5): 3.5 L > Y .gtoreq. 2.5 L A(6), B(6), C(6): 2.5 L
> Y .gtoreq. 1.5 L A(7), B(7), C(7): 1.5 L > Y .gtoreq. 0.5 L
A(8), B(8), C(8): 0.5 L > Y .gtoreq. -0.5 L A(9), B(9), C(9):
-0.5 L > Y .gtoreq. -1.5 L A(10), B(10), C(10): -1.5 L > Y
.gtoreq. -2.5 L A(11), B(11), C(11): -2.5 L > Y .gtoreq. -3.5 L
A(12), B(12), C(12): -3.5 L > Y .gtoreq. -4.5 L A(13), B(13),
C(13): -4.5 L > Y .gtoreq. -5.5 L A(14), B(14), C(14): -5.5 L
> Y .gtoreq. -6.5 L A(15), B(15), C(15): -6.5 L > Y .gtoreq.
-7.5 L
[0051] where L=209.4 .mu.m, and n=1, 2, . . . , 15.
[0052] Just as each circuit segment 21 has a unique coordinate,
each spherical segment 39 also has a unique absolute coordinate.
Since, in this case, there are 15 columns on original grid 20, and
thus a belt needs to be sliced by the great circles into 15
segments, the center of a spherical segment 39 is therefore set
apart from the adjacent segments by 24 degrees (360 degrees/15=24
degrees) with respect to the center of the sphere.
[0053] FIG. 11a shows a mask segment 31 on orbit Am with a mesh
system established for facilitating the mapping of a corresponding
circuit segment 21. With respect the coordinates, the locations of
four corner points are:
[0054] Point 50: Xa(n)=-107.551 .mu.m, Ya(n)=84.102 .mu.m
[0055] Point 52: Xa(n)=-107.551 .mu.m, Ya(n)=-84.102 .mu.m
[0056] Point 54: Xa(n)=99.609 .mu.m, Ya(n)=101.684 .mu.m
[0057] Point 56: Xa(n)=99.609 .mu.m, Ya(n)=-101.684 .mu.m
[0058] And the curved boundary lines or sides can be represented to
be:
[0059] Side 58:
(Xa(n)+94.969).sup.2/(198.925).sup.2+Ya.sup.2(n)/(489.074).sup.2=1
[0060] Side 60:
[(Xa(n)/cos(24.sup.0)-Ya(n)tan(24.sup.0)/tan(12.sup.0)].sup.2+Ya.sup.2(n)/-
sin.sup.2(12.sup.0)=500.sup.2
[0061] Side 62:
(Xa(n)+268.485).sup.2/(164.529).sup.2+Ya.sup.2(n)/(404.509).sup.2=1
[0062] Side 64:
[(Xa(n)/cos(24.sup.0)+Ya(n)tan(24.sup.0)/tan(12.sup.0)].sup.2+Ya.sup.2(n)/-
sin.sup.2(12.sup.0)=500.sup.2
[0063] whereas the number 500 .mu.m represents the radius of the
spherical shaped semiconductor device.
[0064] Similarly for mask segments on orbit Bm as shown in FIG.
11b, the boundary conditions are as follows:
3 Side 66, 68: .vertline.Xb(n).vertline. = 103.95 .mu.m Side 70,
71: .vertline.Yb(n).vertline. = 0.2079 [500.sup.2 -
Xb.sup.2(n)].sup.1/2 + 0.007456 .mu.m
[0065] With respect to FIG.11c, a mask segment on orbit Cm is
shown, and the corners are located at:
[0066] Point 72: Xc(n)=-99.609 .mu.m, Yc(n)=101.684 .mu.m
[0067] Point 74: Xc(n)=107.551 .mu.m, Yc(n)=84.102 .mu.m
[0068] Point 76: Xc(n)=107.551 .mu.m, Yc(n)=-84.102 .mu.m
[0069] Point 78: Xc(n)=-99.609 .mu.m, Yc(n)=-101.684 .mu.m
[0070] and the curved boundary lines or sides are at:
[0071] Side 80:
(Xc(n)-94.969).sup.2/(198.925).sup.2+Yc.sup.2(n)/(489.074).sup.2=1
[0072] Side 84:
(Xc(n)-268.485).sup.2/(164.529).sup.2+Yc.sup.2(n)/(404.509).sup.2=1
[0073] Side 82:
[Xc(n)/cos(24.sup.0)-Yc(n)tan(24.sup.0)/tan(12.sup.0)].sup.2+Yc.sup.2(n)/s-
in.sup.2(12.sup.0)=500.sup.2
[0074] Side 86:
[Xc(n)/cos(24.sup.0)+Yc(n)tan(24.sup.0)/tan(12.sup.0)].sup.2+Yc.sup.2(n)/s-
in.sup.2(12.sup.0)=500.sup.2
[0075] With the above formula and the four corner points, the
advanced computer should be able to draw the boundary lines of the
mask segments 31 on all the orbits.
[0076] Referring again to FIGS. 9a, 9b, and 9c, for a computer to
change the polygon shape of the circuit segments 21 to the
irregular mask segment 31, mathematical calculation must be
involved. Again, for purpose of illustration, the following
formulas are presented to reflect only one configuration of the
system. Specifically, in FIG. 9a, to convert the circuit segment
A(n) of the grid 20 to a mask segment 31 on orbit Am through
intermediate steps, the following formulas are used:
[0077] Step 1: From (X, Y) to (X1, Y1)
X1=0.9893X-3.971 (a1)
Y1=Y(0.0008019X+0.8872) (a2)
[0078] Step 2: From (X1, Y1) to (X2, Y2)
Y2=Y1 (a3)
[0079] when .vertline.Y1.vertline..ltoreq.84.102 .mu.m (i.e., for
points in the center area bound by the phantom lines 44 and 46
including the lines):
X2=[G(Y1)/207.16](X1+107.551)-107.551 (a4)
[0080] where
G(Y1)=12.582+198.925[1-Y1.sup.2/(489.074).sup.2].sup.1/2
[0081] when .vertline.Y1.vertline.>84.102 .mu.m (i.e., for the
points in the area above the phantom lines 44 or below line
46):
X2=H(Y1)(X1-J(Y1))/(99.609-J(Y1))+J(Y1) (a5)
[0082] where
H(Y1
)=1003.5142-11.7825.vertline.Y1.vertline.+198.925[1-Y1.sup.2/(489.074-
).sup.2].sup.1/2
J(Y1)=11.7825.vertline.Y1.vertline.-1098.4827
[0083] Step 3: (X2, Y2) to (Xa(n), Ya(n))
Xa(n)=X2 (a6)
[0084] when X2.ltoreq.99.609 .mu.m (i.e., for points left of or on
the phantom line 48):
Ya(n)=[K(X2)/N(X2)]Y2 (a7)
[0085] where
N(X2)=0.8487X2+93.230
K(X2)=[-b+(b.sup.2-4ac).sup.1/2]/(2a)
[0086] and
a=sin.sup.-2(12.sup.0)[1+cos.sup.2(12.sup.0)tan.sup.2(24.sup.0)]=27.5210
b=-2X2tan(24.sup.0)/[tan(12.sup.0)cos(24.sup.0)]=-4.58573X2
c=X2.sup.2/cos.sup.2(24.sup.0)-500.sup.2=1.19822X2.sup.2-250000
[0087] when X2>99.609 .mu.m (i.e., for the points right of the
phantom line 48):
Ya(n)=Y2 (a8)
[0088] For FIG. 9b, the mathematical representations for converting
the circuit segment B(n) to the mask segments Bm(n) are show
below:
Xb(n)=0.99284X (b1)
Yb(n)=(Y/104.7)[0.20791(500.sup.2-X.sup.2).sup.1/2+0.007456]
(b2)
[0089] For circuit segments C(n), similar to the conversion of
segments A(n) as shown in FIG. 9a, three steps are taken from
circuit segment (X, Y) to (Xc(n), Yc(n) on the flat mask:
[0090] Step 1: From (X, Y) to (X1, Y1)
X1=0.9893X+3.971 (c1)
Y1=Y(-0.0008019X+0.8872) (c2)
[0091] Step 2: From (X1, Y1) to (X2, Y2)
Y2=Y1 (c3)
[0092] when .vertline.Y1.vertline..ltoreq.84.102 .mu.m,
X2=[G(Y1)/207.16](X1-107.551)+107.551 (c4)
[0093] where
G(Y1)=12.582+198.925[1-Y1.sup.2/(489.074).sup.2].sup.1/2
[0094] when .vertline.Y1.vertline.>84.102 .mu.m,
X2=H(Y1)(X1+J(Y1))/(99.609-J(Y1))-J(Y1) (c5)
[0095] where
H(Y1)=1003.5142-11.7825.vertline.Y1.vertline.+198.925[1-Y1.sup.2/(489.074)-
.sup.2]{fraction (1/2)}
J(Y1)=11.7825.vertline.Y1.vertline.-1098.4827
[0096] Step 3: From (X2, Y2) to (Xc(n), Yc(n))
Xc(n)=X2 (c6)
[0097] when X2>-99.609 .mu.m,
Yc(n)=[K(X2)/N(X2)]Y2 (c7)
[0098] where
N(X2)=-0.8487X2+93.230
K(X2)=[-b+(b.sup.2-4ac).sup.1/2]/(2a)
[0099] and
a=sin.sup.-2(12.sup.0)[1+cos.sup.2(12.sup.0)tan.sup.2(24.sup.0)]=27.5210
b=2X2tan(24.sup.0)/[tan(12.sup.0)cos(24.sup.0)]=4.58573X2
c=X2.sup.2/cos.sup.2(24.sup.0)-500.sup.2=1.19822X2.sup.2-250000
[0100] when X2.ltoreq.-99.609 .mu.m
Ya(n)=Y2 (c8)
[0101] Using these relationships, the two-dimensional design can be
segmented and mapped onto a flat mask for three dimensional
projection. It is understood that several modifications, changes
and substitutions are intended in the foregoing disclosure and in
some instances some features of the invention will be employed
without a corresponding use of other features. Accordingly, it is
appropriate that the appended claims be construed broadly and in a
manner consistent with the scope of the invention.
* * * * *