U.S. patent application number 10/024007 was filed with the patent office on 2002-05-09 for method of making chip scale package.
Invention is credited to Lin, Chun Hung.
Application Number | 20020053745 10/024007 |
Document ID | / |
Family ID | 24446697 |
Filed Date | 2002-05-09 |
United States Patent
Application |
20020053745 |
Kind Code |
A1 |
Lin, Chun Hung |
May 9, 2002 |
Method of making chip scale package
Abstract
A method of making a chip scale package comprises the following
steps: providing a semiconductor chip having a plurality of metal
bumps formed on the active surface thereof; providing a metal plate
having a plurality of flip-chip pads formed on a surface thereof;
positioning the semiconductor chip on the surface of the metal
plate with the metal bumps on the chip aligned with the flip-chip
pads on the metal plate; connecting the metal bumps on the active
surface of the semiconductor chip to the flip-chip pads on the
surface of the metal plate; encapsulating the semiconductor chip
against a portion of the surface of the metal plate; removing the
metal plate while leaving the flip-chip pads intact; and forming a
plurality of solder balls on the flip-chip pads. Using the
technique of the present invention, it becomes possible that the
manufacture of a molded chip scale package can be relatively
simplified and economical, yet highly reliable.
Inventors: |
Lin, Chun Hung; (Kaohsiung,
TW) |
Correspondence
Address: |
REED SMITH HAZEL THOMAS LLP
Suite 1400
3110 Fairview Park Drive
Falls Church
VA
22042
US
|
Family ID: |
24446697 |
Appl. No.: |
10/024007 |
Filed: |
December 21, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10024007 |
Dec 21, 2001 |
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09610857 |
Jul 6, 2000 |
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Current U.S.
Class: |
257/778 ;
257/E23.021 |
Current CPC
Class: |
H01L 2924/01079
20130101; H01L 2924/14 20130101; H01L 2924/01013 20130101; H01L
2924/01005 20130101; H01L 2224/16 20130101; H01L 2924/30107
20130101; H01L 24/97 20130101; H01L 21/561 20130101; H01L
2924/01006 20130101; H01L 2224/023 20130101; H01L 2924/01022
20130101; H01L 24/05 20130101; H01L 2224/05568 20130101; H01L
2224/13099 20130101; H01L 2924/01046 20130101; H01L 24/13 20130101;
H01L 21/568 20130101; H01L 2224/05008 20130101; H01L 21/566
20130101; H01L 23/3114 20130101; H01L 2924/01029 20130101; H01L
2924/01042 20130101; H01L 2924/181 20130101; H01L 2924/01078
20130101; H01L 2224/13 20130101; H01L 2924/01024 20130101; H01L
24/10 20130101; H01L 2224/05569 20130101; H01L 2224/05001 20130101;
H01L 2224/05184 20130101; H01L 2224/05022 20130101; H01L 2224/97
20130101; H01L 2924/014 20130101; H01L 2924/01033 20130101; H01L
2224/97 20130101; H01L 2224/81 20130101; H01L 2224/13 20130101;
H01L 2924/00 20130101; H01L 2924/181 20130101; H01L 2924/00
20130101; H01L 2224/05647 20130101; H01L 2924/00014 20130101; H01L
2224/05655 20130101; H01L 2924/00014 20130101; H01L 2224/05669
20130101; H01L 2924/00014 20130101; H01L 2224/05124 20130101; H01L
2924/00014 20130101; H01L 2224/05166 20130101; H01L 2924/00014
20130101; H01L 2224/05171 20130101; H01L 2924/00014 20130101; H01L
2224/05184 20130101; H01L 2924/00014 20130101; H01L 2224/023
20130101; H01L 2924/0001 20130101 |
Class at
Publication: |
257/778 |
International
Class: |
H01L 029/40; H01L
023/52; H01L 023/48 |
Claims
What is claimed is:
1. A chip scale package comprising: a semiconductor chip having a
plurality of metal bumps formed on the active surface thereof, the
semiconductor chip and the metal bumps are encapsulated with a
package body such that each metal bump has at least a portion
exposed from the package body; a plurality of flip-chip pads having
opposing upper and lower surfaces, the upper surfaces of the
flip-chip pads are exposed from the solder mask.
2. The chip scale package as claimed in claim 1, further comprising
a plurality of solder balls mounted on the flip-chip pads.
3. The chip scale package as claimed in claim 1, wherein the
flip-chip pads are made of metal selected from the group consisted
of gold and palladium.
4. A chip scale package, wherein the chip scale package is formed
from a metal plate having a plurality of flip-chip pads formed on a
surface thereof, the semiconductor chip being positioned on the
surface of the metal plate with the metal bumps on the chip aligned
with the flip-chip pads on the metal plate; the metal bumps on the
active surface of the semiconductor chip being connected to the
flip-chip pads on the surface of the metal plate; the semiconductor
chip being encapsulated against a portion of the surface of the
metal plate; and the metal plate being removed so as to leave the
flip-chip pads intact.
5. A chip scale package, wherein the chip scale package is formed
from a solder mask on a surface of a metal plate with predetermined
areas on the surface of the metal plate exposed from the solder
mask; a metal coating on the exposed areas of the metal plate that
form a plurality of flip-chip pads on the surface of the metal
plate; the semiconductor chip being positioned on the surface of
the metal plate with the metal bumps on the chip aligned with the
flip-chip pads on the metal plate; the metal bumps on the active
surface of the semiconductor chip being connected to the flip-chip
pads on the surface of the metal plate; the semiconductor chip
being encapsulated against a portion of the surface of the metal
plate; and the metal plate being removed so as to leave the
flip-chip pads intact.
Description
BACKROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a method of making chip scale
package, and more specifically to a method of making a molded chip
scale package with a flip-chip configuration.
[0003] 2. Description of the Related Art
[0004] As electronic devices have become more smaller and thinner,
the velocity and the complexity of IC chip become more and more
higher. Accordingly, a need has arisen for higher package
efficiency. Demand for miniaturization is the primary catalyst
driving the usage of advanced packages such as chip scale packages
(CSP) and flip chips. Both of them greatly reduce the amount of
board real estate required when compared to the alternative ball
grid array (BGA) and thin small outline package (TSOP). Typically,
a CSP is 20 percent larger than the chip itself. The most obvious
advantage of CSP is the size of the package; that is, the package
is slightly larger than the chip. Another advantage of CSP is that
the package facilitates test and bum-in before assembly as an
alternative to known good die (KGD) testing. In addition, CSP can
combine many of the benefits of surface mount technology (SMT),
such as standardization, encapsulation, surface mount, and
reworkability, with the benefits of flip chip technology, such as
low inductance, high I/O count, and direct thermal path.
[0005] However, CSP has at least one disadvantage compared to
conventional BGA and TSOP, namely, high cost per unit. However,
this problem could be eliminated if chip-sized packages could be
mass produced more easily. Therefore, there is a need in the
semiconductor packaging industry for CSP using mass production
techniques at the wafer-level, as is illustrated in U.S. Pat. No.
5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.
[0006] Disclosed in the technical article by Baba et al. titled,
"Molded Chip Scale Package for High Pin Count," Proceedings of the
46th ECTC, Orlando, Fla., 1996, pp. 1251-1257, is a process for
making a CSP 100 (see FIG. 4) which is shown in greater detail in
FIG. 5. As shown in FIG. 1, the IC chip 10 has a plurality of
rerouted under bump metallurgy (UBM) 12 electrically connected to
bonding pads on its active surface. First, copper lands 22 and
inner solder bumps 24 are formed on a base frame 20 made of
ferroalloy. The copper lands 22 are formed by plating and the inner
solder bumps 24 are formed onto the copper lands 22 by stencil
printing. Then, the chip 10 is attached onto the inner solder bumps
24 of the base frame 20, using flip chip bonding technology. Second
as shown in FIG. 2, the bonded chip 10 and portions of the frame 20
are encapsulated with a package body 30 by a molding process
identical to that used in conventional molding of IC packages.
Thirds as shown in FIG. 3, the base frame 20 is separated from the
encapsulated chip 10 in a way that transfers the copper lands 22
and the inner solder bumps 24 from the base frame 20 to the chip
10. Finally, as shown in FIG. 4, solder balls 40 are attached to
the exposed surfaces of the transferred copper lands 22.
[0007] FIG. 5 shows in greater detail the chip 10 with an external
solder ball 40. The chip 10 has a bonding pad 12 formed on its
active surface. The bonding pad 12 and the external solder ball 40
are connected through wiring conductor pattern 50, UBM 12, inner
solder bump 24 and transferred copper land 22. The package body 30
is capable of providing stress relief in the solder joints due to
CTE mismatch between chip and substrate. The CSP shown in FIGS. 4
has advantages of compact package size, good electrical
performance, and high reliability. However, as can be appreciated
from the above prior art processes, the method of making CSP 100 is
rather complex and costly.
SUMMARY OF THE INVENTION
[0008] It is therefore an object of the present invention to
overcome, or at least reduce the problems and disadvantages
associated with the above-described technique for fabricating a
molded chip scale package.
[0009] It is a further objective of the present invention to
provide a simplified method which can be used to produce a molded
chip scale package.
[0010] The method of making a chip scale package in accordance with
the present invention comprising the following steps: (a) providing
a semiconductor chip having a plurality of metal bumps formed on
the active surface thereof; (b) providing a metal plate having a
plurality of flip-chip pads formed on a surface thereof; (c)
positioning the semiconductor chip on the surface of the metal
plate with the metal bumps on the chip aligned with the flip-chip
pads on the metal plate; (d) connecting the metal bumps on the
active surface of the semiconductor chip to the flip-chip pads on
the surface of the metal plate; (e) encapsulating the semiconductor
chip against a portion of the surface of the metal plate; (f)
removing the metal plate while leaving the flip-chip pads intact;
and (g) forming a plurality of solder balls on the flip-chip
pads.
[0011] Using the technique of the present invention, it becomes
possible that the manufacture of a molded chip scale package can be
relatively simplified and economical, yet highly reliable.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Other objects, advantages, and novel features of the
invention will become more apparent from the following detailed
description when taken in conjunction with the accompanying
drawings.
[0013] FIGS. 1-4 illustrate a conventional method of making a
molded chip scale package (CSP);
[0014] FIG. 5 is a detailed cross sectional view of the CSP shown
in FIG. 4; and
[0015] FIGS. 6-10 show a method of making a molded CSP according to
a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0016] FIGS. 6-10 disclose a method of making a molded CSP
according to a preferred embodiment of the present invention.
[0017] FIG. 6 shows a semiconductor chip 110 having a plurality of
metal bumps 112 formed on the active surface thereof and a metal
plate 120 having a plurality of flip-chip pads 122 formed on a
surface thereof.
[0018] Flip-chip bumping technology typically comprises (a) forming
an under bump metallurgy (UBM) on bonding pads of the chip, and (b)
forming metal bumps on the UBM. Typically, UBM is consisted of
three metal layers, including: (a) adhesion layer (formed of Ti, Cr
or TiW) for purposes of providing a good adhesion to Al pad and
passivation layer; (b) wetting layer (formed of Ni, Cu, Mo or Pt)
wherein that kind of metals provide a higher wetting power to
solder thereby allowing for proper wetting of solder during
solder-reflow process; (c) protective layer formed of Au for
purposes of preventing oxidation of the wetting layer thereby
maintaining good wetting ability of the wetting layer to solder.
Conventional ways to form a multi-layer under bump metallurgy (UBM)
34 mainly comprises chemical vapor deposition (CVD),
plasma-enhanced chemical vapor deposition (PECVD), or physical
vapor deposition (PVD) (sputtering or evaporation). Typically,
there are two kinds of metal compositions used to form the metal
bump. They includes (a) high melting point solder alloys such as
5Sn/95Pb or 3Sn/97Pb and (b) lower melting point solder alloys such
as 63Sn/37Pb or 40Sn/60Pb. The metal bumps 112 of the present
invention are preferably formed of the high melting point solder
alloys. Bumping process is typically accomplished by vapor
deposition, electroplating or printing. Recently, under cost
consideration, a technique called "low cost bumping technology" is
developed wherein the concepts of the technique comprise forming
the UBM by electroless nickel/copper plating and then flip-chip
bumping by printing. It could be understood that the UBM may be
directly formed on the bonding pad of the chip, and then the metal
bumps are formed on the UBM. Alternatively, when a single- or
multi-layer metallization is employed to route the center or
peripheral chip bonding pads to the desired package I/O pattern,
the UBM is formed on the new I/O pattern, and then the metal bumps
are formed on the UBM.
[0019] The metal plate 120 of the present invention may be formed
from the following steps. Firstly, a solder mask 124 such as
photoimagable solder mask or dry film solder mask is applied over
the surface of the metal plate 120, then imaged and developed.
Preferably, the solder mask 124 is formed with a thickness of about
4 to 6 mils. A photomask is used to image only certain area of the
solder mask 124 which, when developed, are removed to leave
predetermined areas exposed. Secondly, by using conventional
plating techniques, a metal coating is formed on the exposed areas
on the metal plate 120 thereby forming a plurality of flip-chip
pads 122 on the surface of the metal plate 120. Preferably, the
metal plate 120 is made of copper, and the metal coating is formed
from gold (or palladium).
[0020] Referring to FIG. 6, the semiconductor chips 110 are
positioned on the surface of the metal plate 120 with the metal
bumps 112 on the chip 110 aligned with the flip-chip pads 122 on
the metal plate 120.
[0021] Referring to FIG. 7, after placement of the semiconductor
chip 110 on the metal plate 120, both the chip 110 and the metal
plate 120 undergo a thermal operation to reflow the metal bumps 112
to the flip-chip pads 122 on the metal plate 120. In the soldering,
the solder mask 124 helps to prevent the bridging of fine-pitch
solder bumps 112. Upon reflowing, both physical and electrical
connection is made between the semiconductor chip 110 and the metal
plate 120. A common method for solder reflowing is to put the
object in a hot-air furnace or in an infrared heating reflow
furnace.
[0022] Referring to FIG. 8, the semiconductor chips 110 and
portions of metal plate 120 are encapsulated in package bodies 130
by a molding process identical to that used in conventional molding
of IC packages. This is accomplished by placing the semiconductor
chip 110 in a mold having cavities and thereafter pouring molding
compound into the mold to fill the mold cavities.
[0023] Finally, a separation step is performed to remove the metal
plate 120. As shown in FIG. 9, the separation step typically
comprises selectively etching the metal plate 120 with the
flip-chip pads 124 remaining intact by an etching agent.
[0024] Referring to FIG. 10, the solder balls 140 can be formed on
the exposed lower surfaces of flip-chip pads 122 by solder ball
placing technique or stencil printing process. The solder balls 140
act as external I/O electrodes of the chip scale package in
accordance with the present invention. When the CSP of the present
invention is installed on an external substrate, the package body
130 is capable of providing stress relief in the solder joints due
to CTE mismatch between chip and substrate.
[0025] The metal bumps 112 of the chip 110 are connected to the
external solder balls 140 through the flip-chip pads 122. It should
be understood that the metal bumps 122 may be directly disposed on
the bonding pads of the chip 110 (as shown in FIG. 10) through an
under bump metallurgy (UBM). Alternatively, the metal bumps 122 may
be connected to the center or peripheral chip bonding pads on a
chip through a single- or multi-layer metallization (not
shown).
[0026] The method of making a chip scale package of the present
invention allows the manufacture of a molded chip scale package to
be relatively simplified and economical, yet highly reliable.
[0027] Although the invention has been explained in relation to its
preferred embodiment, it is to be understood that many other
possible modifications and variations can be made without departing
from the spirit and scope of the invention as hereinafter
claimed.
* * * * *