U.S. patent application number 10/043466 was filed with the patent office on 2002-05-09 for semiconductor device having improved bias dependability and method of fabricating same.
Invention is credited to Yoshikawa, Koichi.
Application Number | 20020053707 10/043466 |
Document ID | / |
Family ID | 18481097 |
Filed Date | 2002-05-09 |
United States Patent
Application |
20020053707 |
Kind Code |
A1 |
Yoshikawa, Koichi |
May 9, 2002 |
Semiconductor device having improved bias dependability and method
of fabricating same
Abstract
On a semiconductor substrate is formed an insulating layer
having a gate insulating region, which is coated with a first
polysilicon layer having a first portion and a second portion which
contacts the gate insulating region. The first portion of the first
polysilicon layer is then doped with an impurity such as
phosphorous. The first polysilicon layer is coated with a second
insulating layer on which is formed a second polysilicon layer. A
first selective etching process is provided so that a capacitive
insulating layer and an upper polysilicon electrode are
successively formed on the first portion of the first polysilicon
layer and the second portion of the first polysilicon layer is
exposed. A second selective etching process is performed so that
the first and second portions of the first polysilicon layer define
a lower polysilicon electrode and a gate electrode, respectively.
As a result, there is produced a semiconductor device having a
lower polysilicon electrode doped with an impurity of conductivity
type identical to conductivity type of the polysilicon gate
electrode.
Inventors: |
Yoshikawa, Koichi; (Tokyo,
JP) |
Correspondence
Address: |
ROSENMAN & COLIN LLP
575 MADISON AVENUE
NEW YORK
NY
10022-2585
US
|
Family ID: |
18481097 |
Appl. No.: |
10/043466 |
Filed: |
January 11, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10043466 |
Jan 11, 2002 |
|
|
|
09746691 |
Dec 21, 2000 |
|
|
|
Current U.S.
Class: |
257/379 ;
257/381; 257/532; 257/E21.008; 257/E27.016; 438/200; 438/210;
438/957 |
Current CPC
Class: |
H01L 27/0629 20130101;
H01L 28/40 20130101 |
Class at
Publication: |
257/379 ;
438/200; 438/210; 257/381; 257/532; 438/957 |
International
Class: |
H01L 029/94; H01L
031/062; H01L 021/8238 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 22, 1999 |
JP |
11-364147 |
Claims
What is claimed is:
1. A semiconductor device comprising: a semiconductor substrate; an
insulating layer on said substrate, said insulating layer having a
gate insulating region; a lower polysilicon electrode on said
insulating layer; a capacitive insulating layer on said lower
polysilicon electrode; an upper polysilicon electrode on said
capacitive insulating layer; and a polysilicon gate electrode on
said gate insulating region, the gate electrode and said lower
polysilicon electrode having equal thickness, said lower
polysilicon electrode being doped with an impurity of conductivity
type identical to conductivity type of said polysilicon gate
electrode.
2. The semiconductor device of claim 1, wherein said lower
polysilicon electrode has a larger area than said upper polysilicon
electrode.
3. The semiconductor device of claim 1, wherein said upper
polysilicon electrode is doped with an impurity of conductivity
type identical to conductivity type of said upper polysilicon
electrode.
4. The semiconductor device of claim 1, wherein said lower and
upper polysilicon electrodes are doped with equal impurity
dose.
5. The semiconductor device of claim 3, wherein said impurity dose
is 1.times.10.sup.15/cm.sup.3 to 1.times.10.sup.16/cm.sup.3.
6. The semiconductor device of claim 1, wherein said capacitive
insulating layer has a thickness of 20 to 50 nanometers.
7. The semiconductor device of claim 1, wherein said lower
polysilicon electrode has a thickness of 100 to 250 nanometers and
said upper polysilicon electrode has a thickness of 100 to 200
nanometers.
8. A method of fabricating a semiconductor device, comprising the
steps of: a) forming a first insulating layer with a gate
insulating region on a semiconductor substrate; b) forming a first
polysilicon layer on said first insulating layer and said gate
insulating region, said first polysilicon layer having a first
portion spaced from a second portion which contacts said gate
insulating region; c) doping an impurity into said first portion of
said first polysilicon layer, said impurity having a conductivity
type equal to conductivity type of said first polysilicon; d)
forming a second insulating layer on said first polysilicon layer;
e) forming a second polysilicon layer on said second insulating
layer; f) performing a first selective etching process so that a
capacitive insulating layer and an upper polysilicon electrode are
successively formed on said first portion of the first polysilicon
layer, and said second portion of the first polysilicon layer is
exposed; and g) performing a second selective etching process so
that said first and second portions of the first polysilicon layer
define a lower polysilicon electrode and a gate electrode,
respectively.
9. The method of claim 8, further comprising the step of doping
said second polysilicon layer with an impurity of conductivity type
identical to conductivity type of the second polysilicon layer.
10. The method of claim 8, wherein step (b) is continued until said
first polysilicon layer attains a thickness of 100 to 250
nanometers, and step (e) is continued until said second polysilicon
layer attains a thickness of 100 to 200 nanometers.
11. The method of claim 8, wherein step (c) is continued until said
first polysilicon layer attains an impurity dose of
1.times.10.sup.15/cm.sup.3 to 1.times.10.sup.16/cm.sup.3.
12. The method of claim 9, wherein said second polysilicon layer is
doped until an impurity dose of 1.times.10.sup.15/cm.sup.2 to
1.times.10.sup.16/cm.sup.2 is attained.
13. The method of claim 8, wherein step (d) is continued until said
second insulating layer attains a thickness of 20 to 50 nanometers.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to semiconductor
devices, and more specifically to an analog semiconductor devices
having upper and lower polysilicon electrodes and a method of
fabricating the semiconductor device.
[0003] 2. Description of the Related Art
[0004] Analog metal-oxide-semiconductor transistors are composed of
a gate formed on an oxide layer, and a source and a drain each
being formed of upper and lower polysilicon electrodes and a
capacitive element sandwiched therebetween. This capacitive element
is required that a deviation from the specified capacitance value
must be maintained in as small a range as possible under varying
operating voltages. The lower polysilicon electrode and the gate
are usually fabricated simultaneously. However, in the prior art
transistor, the lower polysilicon electrode has no sufficient level
of impurity dose to provide desired bias dependability. Thus there
is a need to improve the bias dependability of a semiconductor
device.
SUMMARY OF THE INVENTION
[0005] It is therefore an object of the present invention to
provide a semiconductor device with a lower polysilicon electrode
having an impurity dose that is sufficient to obtain desired bias
dependability and a method of fabricating the semiconductor
device.
[0006] According to one aspect of the present invention, there is
provided a semiconductor device comprising a semiconductor
substrate, an insulating layer on the substrate, the insulating
layer having a gate insulating region, a lower polysilicon
electrode on the insulating layer, a capacitive insulating layer on
the lower polysilicon electrode, an upper polysilicon electrode on
the capacitive insulating layer, and a polysilicon gate electrode
on the gate insulating region, the gate electrode being of equal
thickness to the lower polysilicon electrode. The lower polysilicon
electrode is doped with an impurity of conductivity type identical
to conductivity type of the polysilicon gate electrode.
[0007] According to a further aspect, the present invention
provides a method of fabricating a semiconductor device, comprising
the steps of (a) forming a first insulating layer with a gate
insulating region on a semiconductor substrate, (b) forming a first
polysilicon layer on the first insulating layer and the gate
insulating region, the first polysilicon layer having a first
portion spaced from a second portion which contacts the gate
insulating region, (c) doping an impurity into the first portion of
the first polysilicon layer, the impurity having a conductivity
type equal to conductivity type of the first polysilicon, (d)
forming a second insulating layer on the first polysilicon layer,
(e) forming a second polysilicon layer on the second insulating
layer, (f) performing a first selective etching process so that a
capacitive insulating layer and an upper polysilicon electrode are
successively formed on the first portion of the first polysilicon
layer and the second portion of the first polysilicon layer is
exposed, and (g) performing a second selective etching process so
that the first and second portions of the first polysilicon layer
define a lower polysilicon electrode and a gate electrode,
respectively.
BRIEF DESCRIPTION OF THE DRAWIGNS
[0008] The present invention will be described in detail further
with reference to the following drawings, in which:
[0009] FIGS. 1 to 8 are cross-sectional views of a semiconductor de
vice of successive stages of the fabrication process of the present
invention, wherein FIG. 1 illustrates the formation of a first
insulating layer and a gate insulation layer on a semiconductor
substrate and the deposition of a first polysilicon layer on the
device, FIG. 2 illustrates a first impurity doping process on a
selected portion of the first polysilicon layer;
[0010] FIG. 3 illustrates the deposition of a second insulating
layer on the first polysilicon layer;
[0011] FIG. 4 illustrates the deposition of a second polysilicon
layer and a second impurity doping process on the second
polysilicon layer;
[0012] FIGS. 5 and 6 illustrate a first etching process on a
selected portion of the second polysilicon layer and the underlying
second insulating layer; and
[0013] FIGS. 7 and 8 illustrate a second etching process.
DETAILED DESCRIPTION
[0014] Referring to FIGS. 1 to 8, a fabrication process of a
semiconductor device according to the present invention is
illustrated.
[0015] In FIG. 1, a field oxide layer 2 is formed on a
semiconductor substrate 1 as a device separator to a thickness of
200 to 500 nanometers. After forming a gate oxide layer 3, the
device is coated with a polysilicon layer 4 with a thickness of 100
to 250 nanometers. A lower electrode and a gate will be formed from
this polysilicon layer.
[0016] In FIG. 2, photoresist 5 is used to provide ion implantation
of phosphorous, whereby a polysilicon region selected for the lower
electrode is doped with the impurity of the same conductivity type
as the conductivity type of a polysilicon region to be selected as
a gate electrode on the gate oxide layer 3. If these polysilicon
regions are of the N-type conductivity, the doping is continued
until an impurity dose of 1.times.10.sup.15/cm.sup.3 to
1.times.10.sup.16/cm.sup.3 is attained. A highly doped polysilicon
region 7 is thus formed. Note that phosphorous is of the same
conductivity type as the conductivity type of a region above the
gate oxide layer 3.
[0017] After removing the photoresist 5, an oxide layer 8 is formed
on the device to a thickness of 20 to 50 nanometers, as shown in
FIG. 3.
[0018] In FIG. 4, a polysilicon layer 14 of thickness 100 to 200
nanometers is grown on the oxide layer 8 and the polysilicon layer
14 is then doped with phosphorous in an ion implantation process.
If the polysilicon layer 14 is of the N-type conductivity, the
doping is continued until an impurity dose of 1.times.10.sup.15
/cm.sup.3 to 1.times.10.sup.16/cm.sup.3 is reached.
[0019] In FIG. 5, the polysilicon layer 14 and oxide layer 8 are
selectively etched by using a photoresist 15. As a result, a
capacitive oxide layer 18 is formed on the highly doped polysilicon
region 7 and a doped polysilicon layer 24 on the capacitive layer
18, as shown in FIG. 6.
[0020] In FIG. 7, the polysilicon layer 4 is selectively etched by
using photoresists 25 and 26 so that the lower polysilicon
electrode 10 and the gate 11 are formed as shown in FIG. 8.
[0021] The bias dependability of the transistor of this invention
is improved to 0.01%/volts to 0.03%/volts, as opposed to the
dependability value of 0.3%/volts to 0.5%/volts of the prior art
transistor in which the lower polysilicon electrode is not
ion-injected with phosphorous.
* * * * *