U.S. patent application number 09/726460 was filed with the patent office on 2002-05-02 for method of fabricating gate.
Invention is credited to Chang, Ching-Yu.
Application Number | 20020052098 09/726460 |
Document ID | / |
Family ID | 21661302 |
Filed Date | 2002-05-02 |
United States Patent
Application |
20020052098 |
Kind Code |
A1 |
Chang, Ching-Yu |
May 2, 2002 |
Method of fabricating gate
Abstract
A method of fabricating a gate. A gate dielectric layer is
formed, and a lower portion of a floating gate is formed
encompassed by a first dielectric layer. Second dielectric layers
with different etching rates are formed to cover the upper portion
of the floating gate and the first dielectric layer. Using an
etching mask, an opening is formed within the second dielectric
layer to expose the floating gate and a portion of the second
dielectric layers by performing an anisotropic etching process.
Using the same etching mask, the second dielectric layers exposed
within the opening is further etched by performing an isotropic
etching process. Due to the different etching rates, a dielectric
layer with an uneven and enlarged surface is formed. A conformal
conductive layer is formed on the exposed lower portion of the
floating gate and the exposed second dielectric layers as an upper
portion of the floating gate. A conformal third dielectric layer is
formed on the conformal conductive layer, followed by forming a
control gate on the third dielectric layer.
Inventors: |
Chang, Ching-Yu; (Yilan
Hsien, TW) |
Correspondence
Address: |
J C Patents Inc
4 Venture
Suite 250
Irvine
CA
92618
US
|
Family ID: |
21661302 |
Appl. No.: |
09/726460 |
Filed: |
November 30, 2000 |
Current U.S.
Class: |
438/585 ;
257/E21.209; 257/E21.578; 438/637; 438/640; 438/666; 438/734 |
Current CPC
Class: |
H01L 21/76804 20130101;
H01L 29/40114 20190801 |
Class at
Publication: |
438/585 ;
438/734; 438/637; 438/640; 438/666 |
International
Class: |
H01L 021/336; H01L
021/3205; H01L 021/4763; H01L 021/302; H01L 021/461; H01L
021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 25, 2000 |
TW |
89119720 |
Claims
What is claimed is:
1. A method of fabricating a gate over a substrate which comprising
a device structure, the device structure including a source/drain
region, a gate dielectric layer, a first gate conductive layer, and
a first dielectric layer encompassing the first gate conductive
layer, the method comprising: forming a plurality of second
dielectric layers on the first dielectric layer and the first gate
conductive layer; forming a first etching mask on a topmost second
dielectric layer, the etching mask comprising a first opening
expose a portion of the topmost second dielectric layer; performing
an anisotropic etching step to form a second opening that exposes
the first gate conductive layer performing an isotropic etching
step on the second dielectric layers exposed within the second
opening with the etching mask remaining on the topmost second
dielectric layer, so that a third opening having an uneven surface
since the second dielectric layers have different etching rates
from each other is formed; removing the first etching mask.
2. The method according to claim 1, wherein the step of performing
the isotropic etching step comprising forming the third opening
with a stair-like profile.
3. The method according to claim 1, wherein the step of forming the
second dielectric layers comprises forming the second dielectric
layers with materials including at least one of the oxide, silicon
nitride, doped oxide, doped silicon nitride, borosilicate glass
(BSG), borophosphosilicate glass (BPSG), phosphosilicate glass
(PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass
or organic silicide containing silicon and oxide
4. The method according to claim 1, wherein the step of forming the
second dielectric layers includes a forming each of the second
dielectric layers with a certain density to result in different
isotropic etching rates from each other.
5. The method according to claim 1, wherein the step of performing
the isotropic etching includes a step of controlling the dopant
concentration of the second dielectric layers to result in
different etching rates.
6. The method according to claim 1, wherein the step of performing
the isotropic etching includes a chemical dry etching process, a
chemical wet etching process, or a chemical vapor etching
process.
7. The method according to claim 6, wherein the step of chemical
wet etching process comprises a step of using one of a mixture of
hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric
acid as an etchant.
8. The method according to claim 1, further comprising the
following steps: forming a conformal conductive layer covering a
bottom surface and a sidewall of the third opening, including the
second dielectric layers and the first gate conductor layer exposed
by the third opening; patterning the first conductive layer to
expose the second dielectric layers out of the third opening;
forming a conformal third dielectric layer on the first conductive
layer as a gate dielectric layer; and forming a second conductive
layer on the third dielectric layer.
9. The method according to claim 1, wherein the step of forming the
third dielectric layer comprises forming a silicon nitride layer, a
silicon oxide layer, a composite layer of oxide/nitride/oxide, a
lead zirconium titanate layer or a tantalum oxide layer.
10. The method according to claim 1, wherein the step of forming
the second conductive layer comprises a step of forming one of a
polysilicon layer and a tungsten layer.
11. A method of forming a dielectric layer, the method comprising:
providing a substrate, the substrate comprising a device structure;
forming a plurality of dielectric layers on the substrate; forming
an etching mask on a topmost layer among the dielectric layers;
performing an anisotropic etching step on the dielectric layers
until the device structure is exposed; performing an isotropic
etching step on the dielectric layers, wherein the dielectric
layers have different isotropic etching rates; and removing the
etching mask layer.
12. The method according to claim 11, wherein the step of
performing the isotropic etching step includes a step of forming an
opening with a stair-like profile within the dielectric layers.
13. The method according to claim 11, wherein the step of forming
the dielectric layers with materials including at least one of the
oxide, silicon nitride, doped oxide, doped silicon nitride,
borosilicate glass (BSG), borophosphosilicate glass (BPSG),
phosphosilicate glass (PSG), boro-oxide, phospho-oxide,
borophospho-oxide, spin-on-glass or organic silicide containing
silicon and oxide
14. The method according to claim 11, wherein the step of forming
the dielectric layers comprises a step of forming the dielectric
layers with different densities to result in the different
isotropic etching rates.
15. The method according to claim 11, wherein the step of forming
the dielectric layer includes a step of forming the dielectric
layers with different dopant concentrations to result in the
different isotropic etching rates.
16. The method according to claim 11, wherein the step of
performing the isotropic etching includes a chemical dry etching
process, a chemical wet etching process, or a chemical vapor
etching process.
17. The method according to claim 16, wherein the step of chemical
wet etching process comprises a step of using one of a mixture of
hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric
acid as an etchant.
18. A method for fabricating a capacitor, comprising: providing a
substrate comprising a device region thereon; forming a plurality
of dielectric layers with different etching rates on the substrate;
performing an ansotropic etching process on the dielectric layers
using an etching mask formed on the dielectric layers until
sidewalls of the dielectric layers and the device region is
exposed; performing an isotropic etching process on the exposed
sidewalls of the dielectric layer using the same etching mask used
for the anisotropic etching process; forming a first conductive
layer on the sidewalls of the dielectric layers, the first
conductive layer being conformal to the surface profile of the
sidewalls; forming a capacitor dielectric layer on the first
conductive layer, the capacitor dielectric layer being conformal to
the first conductive layer; and forming a second conductive layer
on the capacitor dielectric layer.
19. The method according to claim 18, wherein the step of
performing the isotropic etching process includes a step of etching
the exposed sidewalls of the dielectric layers to have a stair-like
profile.
20. The method according to claim 18, wherein the step of forming
the dielectric layers with materials including at least one of the
oxide, silicon nitride, doped oxide, doped silicon nitride,
borosilicate glass (BSG), borophosphosilicate glass (BPSG),
phosphosilicate glass (PSG), boro-oxide, phospho-oxide,
borophospho-oxide, spin-on-glass or organic silicide containing
silicon and oxide.
21. The method according to claim 18, wherein the step of forming
the dielectric layers comprises a step of forming the dielectric
layers with different densities to result in the different
isotropic etching rates.
22. The method according to claim 18, wherein the step of forming
the dielectric layer includes a step of forming the dielectric
layers with different dopant concentrations to result in the
different isotropic etching rates.
23. The method according to claim 18, wherein the step of
performing the isotropic etching includes a chemical dry etching
process, a chemical wet etching process, or a chemical vapor
etching process.
24. The method according to claim 23, wherein the step of chemical
wet etching process comprises a step of using one of a mixture of
hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric
acid as an etchant.
25. A gate structure, formed over a substrate comprising a
source/drain region, the gate structure comprises: a gate
dielectric layer, on the substrate; a first gate conductive layer,
on the gate dielectric layer; a first dielectric layer,
encompassing the first gate conductive layer; a plurality of second
dielectric layers, with an opening exposing a portion of the first
dielectric layer and the first gate conductive layer, the opening
having a sidewall with a stair-like profile; a second gate
conductive layer, on a surface of the opening and conformal to the
stair-like profile; and a third dielectric layer, on and conformal
to the second gate conductive layer.
26. The gate structure according to claim 25, comprising further a
third gate conductive layer on the third dielectric layer.
27. The gate structure according to claim 25, wherein the second
dielectric layer comprises one of the oxide, silicon nitride, doped
oxide, doped silicon nitride, borosilicate glass (BSG),
borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),
boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or
organic silicide containing silicon and oxide.
28. The gate structure according to claim 25, wherein the second
dielectric layers have different densities from each other.
29. The gate structure according to claim 25, wherein the second
dielectric layers have different dopant concentration from each
other.
30. The gate structure according to claim 25, wherein the second
dielectric layer comprises one of silicon nitride layer, silicon
oxide layer, an oxide/nitride/oxide layer, a lead zirconium
titanate layer, a bismuth strontium titanate layer and a tantalum
oxide layer.
31. The gate structure according to claim 25, wherein the second
gate conductive layer and the third gate conductive layer comprise
one of a polysilicon layer and a tungsten silicide layer.
32. A dielectric structure, formed over a substrate comprising a
device region, the dielectric structure comprises: a plurality of
dielectric layers, with an opening exposing the device region,
wherein the opening has a slanting sidewall with a stair-like
profile.
33. The dielectric structure according to claim 32, wherein the
dielectric layers comprises one of the oxide, silicon nitride,
doped oxide, doped silicon nitride, borosilicate glass (BSG),
borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),
boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or
organic silicide containing silicon and oxide.
34. The dielectric structure according to claim 32, wherein the
dielectric layers have different densities from each other.
35. The dielectric structure according to claim 32, wherein the
dielectric layers have different dopant concentrations from each
other.
36. A bottom electrode over a substrate, the substrate having a
device region thereon, the bottom electrode comprising: a plurality
of dielectric layers, on the substrate and having an opening with a
slanting stair-like sidewall, wherein the device region of the
substrate is exposed; and a bottom electrode, formed along a
surface profile of the opening.
37. The bottom electrode according to claim 36, wherein the
dielectric layer comprises one of oxide, silicon nitride, doped
oxide, doped silicon nitride, borosilicate glass (BSG),
borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),
boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or
organic silicide containing silicon and oxide.
38. The bottom electrode according to claim 36, wherein the
dielectric layers have different densities from each other.
39. The bottom electrode according to claim 36, wherein the
dielectric layers have different dopant concentrations from each
other.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 89119720, filed Sep. 25, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates in general to a fabrication method and
a structure of a gate. More particularly, this invention relates to
a method to increasing the effective surface of the dielectric
layer between a floating gate and a control gate.
[0004] 2. Description of the Related Art
[0005] Stacked-gate non-volatile memory devices such as erasable
programmable read only memory (EPROM), electrically erasable
programmable read only memory (EEPROM) and flash memory, have
attracted great attention and research due to excellent data
storage properties without the additional applying electric
field.
[0006] The current-voltage (I-V) characteristics of the
stacked-gate non-volatile memory devices can be derived by the I-V
characteristics of the conventional metal-oxide semiconductor (MOS)
device and the capacitive coupling effect. Normally, the higher the
capacitive coupling effects a device has, the lower operatioin
voltage is required.
[0007] FIG. 1 shows a structure of a conventional stacked-gate
non-volatile flash memory after forming and patterning conductive
layers 26 and 50. The conductive layers 26 and 50 construct a
floating gate. A dielectric layer 24 is formed as the gate
dielectric layer between the substrate and the floating gate. In
FIG. 1B, a dielectric layer 52 is formed on the floating gate, and
a control gate is formed on the dielectric layer 52. The control
gate comprises a conductive layer 54. Both FIGS. 1A and 1B have a
gate 58 and a non-gate region 60. The conductive layers 26 and 50
in the non-gate region 60 are removed while patterning the
dielectric layer 52 and the conductive layer 54.
[0008] FIG. 2 shows a cross sectional view along the cutting line
II-II as shown in FIG. 1A and 1B. In FIG. 2, a gate is formed on a
substrate comprising a semiconductor substrate 20, a source region
22 and a drain region 23. The gate comprises the gate dielectric
layer 24, the conductive layers 26 and 50, the dielectric layer 52
and the conductive layer 54.
[0009] The conventional stacked-gate non-volatile flash memory
comprises four junction capacitors. They are C.sub.FG between the
floating gate (the conductive layers 26 and 50) and the control
gate (the conductive layer 54), C.sub.B between the floating gate
and substrate 20, C.sub.S between the floating gate and the source
region 22, and C.sub.D between the floating gate and the drain
region 23.
[0010] The capacitive coupling ratio can be represented by: 1
Capacitive coupling ratio = C F G C F G + C B + C S + C D
[0011] From the above equation, when the junction capacitor
C.sub.FG increases, the capacitive coupling ratio increases.
[0012] The method for increasing the junction capacitance C.sub.FG
includes increasing the effective surface of the dielectric layer
between the floating gate and the control gate, reducing the
thickness of the dielectric layer and increasing the dielectric
constant (k) of the dielectric layer.
[0013] The dielectric layer between the floating gate and the
control gate requires a sufficient thickness to prevent the
electrons within the floating gate from tunneling to the control
gate during operation to cause device failure.
[0014] The increase of the dielectric constant involves the
replacement of fabrication equipment and a further advance
fabrication technique, so that it is difficult to achieve.
[0015] Therefore, to increase the effective surface of the
dielectric layer betweent eh floating gate and the control gate
becomes a trend for increasing the capacitive coupling ratio.
[0016] In FIG. 2, in the conventional stacked-gate non-volatile
memory, the dielectric layer 30 encircles the conductive layer 26.
That is, the conductive layer 26 is formed in an opening 44 of the
dielectric layer 30, while the surface level of the dielectric
layer 26 is higher than the surface level of the conductive layer
26. Therefore, the upper portion of the opening 44 is not filled
with the conductive layer 26. Instead, the upper portion of the
opening 44 is filled with the conformal conductive layer 50. Being
conformal to the dielectric layer 30 with the recess of the upper
portion of the opening 44, the conductive layer 50 has a recess to
result in an additional effective surface of the dielectric layer
52 formed subsequently. However, thus formed, the vertical
thickness of the dielectric layer 52 is increased.
[0017] Referring to FIGS. 1A, 1B and 2, when the dielectric layer
52 and the conductive layer 54 are patterned, the dielectric layer
52, the conductive layer 54, the conductive layers 50 and 26 in the
non-gate region are removed. As the conductive layer 50 has a
recess, the vertical thickness of the dielectric layer 52 is far
larger than the lateral thickness to cause great difficulty in
etching, or even cause the dielectric layer residue. As a result,
though the effective surface of the dielectric layer is increased,
it is difficult to remove the dielectric layer 52 in the non-gate
region 60. To remove the dielectric layer 52 completely, the depth
of the recess has to be reduced. In this case, the effective
surface is reduced.
[0018] The signal storage of the dynamic random access memory is
performed by selectively charging or discharging the capacitors on
the semiconductor surface. The reading or writing operation is
executed by injecting or ejecting charges from the storage
capacitor connected to a transfer field effective transistor.
[0019] The capacitor is thus a heart of a dynamic random access
memory. When the surface of the memory cell is reduced, the
capacitance is reduced to seriously affect the stack density of the
memory. As a consequence, the read-out performance is degraded, the
occurrence of soft errors is increased, and the power consumption
during low voltage operation is increased. Increasing the surface
area of the dielectric layer between the bottom and top electrode
becomes one effective method to resolve the above problems.
However, additional photomasks are required for achieving such
goal, the fabrication cost is thus increased.
SUMMARY OF THE INVENTION
[0020] The invention provides a fabrication method and structure of
a gate to increase the effective surface between the floating gate
and the control gate of the gate. In addition, the vertical etching
thickness of the dielectric layer is reduced.
[0021] In the method of fabricating a gate, a gate dielectric layer
is formed, and a lower portion of a floating gate is formed
encompassed by a first dielectric layer. Second dielectric layers
with different etching rates are formed to cover the upper portion
of the floating gate and the first dielectric layer. Using an
etching mask, an opening is formed within the second dielectric
layer to expose the floating gate and a portion of the second
dielectric layers by performing an anisotropic etching process.
Using the same etching mask, the second dielectric layers exposed
within the opening is further etched by performing an isotropic
etching process. Due to the different etching rates, a dielectric
layer with an uneven and enlarged surface is formed. A conformal
conductive layer is formed on the exposed lower portion of the
floating gate and the exposed second dielectric layers as an upper
portion of the floating gate. A conformal third dielectric layer is
formed on the conformal conductive layer, followed by forming a
control gate on the third dielectric layer.
[0022] In the above method, as the anisotropic and isotropic
etching processes are performed using the same etching mask, the
total number of photomasks is thus reduced. In addition, due to the
different etching rates of the second dielectric layers, the
opening with stair-like profile is formed. That is, the second
dielectric layers exposed in the opening have a stair-like profile,
therefore, the conformal conductive layer and the conformal third
dielectric layer also have the stair-like profile. The surface area
is thus greatly increase to enhance the performance of the device.
In addition, the stair-like profile provides a larger surface area
without introducing a deeper vertical etching depth. The problems
in etching the dielectric layer are thus resolved.
[0023] By applying the above to the fabrication process of a
capacitor, that is, to form a capacitor dielectric layer with the
stair-like profile using the above method, the capacitance of the
capacitor can be greatly increased. The first conductive layer
itself, or the combination of the first conductive layer and the
conformal conductive layer can be used as a bottom electrode. The
third dielectric layer can be used as the capacitor dielectric
layer, and the control gate can be used as the top electrode.
[0024] Both the foregoing general description and the following
detailed description are exemplary and explanatory only and are not
restrictive of the invention, as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1A shows a layout of a conventional stacked-gate
non-volatile flash memory after forming the floating gate;
[0026] FIG. 1B shows the layout of the gate of the stacked-gate
non-volatile flash memory as shown in FIG. 1A;
[0027] FIG. 2 shows a cross sectional view along the cutting line
II-II as shown in FIG. 1;
[0028] FIG. 3A shows a layout of a stacked-gate memory provided by
the invention after the floating gate is patterned;
[0029] FIG. 3B shows a layout of the gate of the stacked-gate
memory as shown in FIG. 3A;
[0030] FIG. 4A to FIG. 4F are cross sectional views along the
cutting line IV-IV in FIG. 3A and FIG. 3B; and
[0031] FIG. 5A to FIG. 5F shows the application of the method
provided by the invention to a dynamic random access memory.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0032] First Embodiment
[0033] In FIG. 3A, a stacked gate non-volatile flash memory is
formed after conductive layers 126 and 150 are formed to construct
a floating gate. A gate dielectric layer 124 is formed between the
floating gate and a substrate. In FIG. 3B, a dielectric layer 152
is formed between the floating gate and a control gate. The
conductive layer 154 is formed as the control gate. The structure
in FIG. 3A and FIG. 3B comprises the gate region 158 and a non-gate
region 160. The conductive layers 126 and 150 in the non-gate
region 160 are removed while patterning the dielectric layer 152
and the conductive layer 154. FIG. 4A to FIG. 4F are cross
sectional views along the cutting line IV-IV in FIG. 3A and FIG.
3B.
[0034] In FIG. 4A, a semiconductor substrate 120 is provided. A
source region 122, a drain region 123, a gate dielectric layer 124,
a conductive layer 126 and a dielectric layer 130 encompassing the
conductive layer 126 are formed the semiconductor substrate 120.
Dielectric layer 140 comprising the layers 132, 134, 136 and 138
are formed over the substrate 120. Each of the dielectric layers
132, 134, 136 and 138 has an etching rate different from other
dielectric layers. The material for forming the dielectric layers
132, 134, 136 and 138 comprises oxide, silicon nitride, doped
oxide, doped silicon nitride, borosilicate glass (BSG),
borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),
boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or
organic silicide containing silicon and oxide. The densities and
dopant concentrations of each of the dielectric layers 132, 134,
136 and 138 can be adjusted to be different from each other to
result in different etching rates, especially for the isotropic
etching step. The thickness of these dielectric layers 132, 134,
136 and 138 can be different or identical. An etching mask 142 is
formed on the topmost dielectric layer 138. The etching mask 142
layer comprises an opening 145 that exposes a portion of the
dielectric layer 138. The layout of the opening 145 is shown as the
dielectric layer opening 144 in FIG. 3A.
[0035] Referring to FIG. 4B, an anisotropic etching process is
performed on the dielectric layer 140 to form an opening 146
exposing the underlying conductive layer 126. That is, a top
surface of the conductive layer is exposed at a bottom of the
opening 146.
[0036] Referring to FIG. 4C, an isotropic etching process is
performed on the dielectric layer 140 exposed within the opening
146. As the etching rates of the dielectric layers 132, 134, 136
and 138 are different, an opening 147 is resulted as shown in FIG.
4C and FIG. 4D. The mask 142 is removed. In this embodiment, the
etching rates of the dielectric layer 140 are gradually decreases
from the topmost dielectric layer 138 to the bottom most dielectric
layer 132. Therefore, the resulting opening has a stair-like
profile. The isotropic etching step includes chemical dry etch,
chemical wet etch and chemical vapor etch. A mixture of hydrogen
fluoride and ammonium fluoride, hydrogen fluoride, nitric acid and
phosphoric acid can be used for performing the chemical wet
etching. Since the anisotropic and isotropic etching steps are
performed using the same mask 142, therefore, the total number of
photomask is reduced.
[0037] In FIG. 4D, the mask layer 142 is removed, and the result
opening is denoted as 148. The stair-like dielectric layaer 140
thus has an increased effective surface. The opening 148 comprises
two slanting sidewalls. The slanting sidewalls can further be
divided into small sections of the respective dielectric layers
132, 134, 136 and 138. Each section of the slanting sidewalls has a
thickness thinner than the overall thickness of the dielectric
layer 140.
[0038] In FIG. 4E, a conductive layer 150 is formed on the slanting
sidewalls and the conductive layer 126 exposed in the bottom of the
opening 148. Preferably, the conductive layer 126 is formed to be
conformal to the slanting sidewalls. The conductive layer 126 and
the conductive layer 150 thus construct the floating gate.
[0039] A dielectric layer 152 between the floating gate and a
control gate is then formed to cover at least the conductive layer
150 and the dielectric layer 138, and a conductive layer 154 is
formed to cover at least this dielectric layer. Preferably, the
dielectric layer 152 is formed along the surface profile of the
conductive layer 150, that is the surface profile of the opening
148. That is, the dielectric layer 152 is conformal to the etched
dielectric layer 140. Referring to FIGS. 3A, 3B and 4F, the
conductive layer 154 and the dielectric layer 152 are patterned.
The patterned conductive layer 154 is the control gate. The
material for forming the dielectric layer 152 includes silicon
nitride, silicon oxide, oxide/nitride/oxide (ONO), a lead zirconium
titanate, bismuth strontium titanate and tantalum oxide. The
conductive layers 150 and 154 include polysilicon and tungsten
silicide.
[0040] Referring to FIG. 3A, FIG. 3B and FIG. 4F, the conductive
layer 154, the dielectric layer 152, the conductive layer 150, and
the conductive layer 126 in the non-gate region 160 are removed
while patterning the conductive layer 154 and the dielectric layer
152. As a result, the dielectric layer 152 between the control gate
and the floating gate has stair-like profile with an enlarged
effective surface. The stair-like profile does not result in
difficulty in vertical etching. Therefore, the effective surface of
the dielectric layer is enlarged without increasing the thickness
thereof.
[0041] Second Embodiment
[0042] FIG. 5A to FIG. 5F illustrate a second embodiment of the
invention that provides a method for fabricating a gate of a
capacitor of a dynamic random access memory. In FIG. 5A, a
dielectric layer 240 comprising a stack of dielectric layers 232,
234, 236, 238, is formed on a substrate 220 on which a device
region 224, for example, a source/drain region, is formed. The
material for forming the dielectric layers 132, 134, 136 and 138
comprises oxide, silicon nitride, doped oxide, doped silicon
nitride, borosilicate glass (BSG), borophosphosilicate glass
(BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide,
borophospho-oxide, spin-on-glass or organic silicide containing
silicon and oxide. The densities and dopant concentrations of each
of the dielectric layers 232, 234, 236 and 238 are different from
each other. The thickness of these dielectric layers 232, 234, 236
and 238 can be different or identical. An etching mask 242 is
formed on the topmost dielectric layer 138. The etching mask 242
layer comprises an opening 245 that exposes a portion of the
dielectric layer 238 aligned over the device region 224.
[0043] In FIG. 5B, an isotropic etching step is performed to remove
the dielectric layer 240, so that an opening 246 is formed to
expose the device region 224 of the substrate 224.
[0044] In FIG. 5C, an isotropic etching step is performed on the
dielectric layer 240 exposed within the opening 246, while the
etching mask 242 remains on the topmost dielectric layer 238. Being
further etched, the opening 246 is enlarged and denoted as 247 as
shown in FIG. 5C. The isotropic etching step includes chemical dry
etch, chemical wet etch and chemical vapor etch. A mixture of
hydrogen fluoride and ammonium fluoride, hydrogen fluoride, nitric
acid and phosphoric acid can be used for performing the chemical
wet etching. Since the anisotropic and isotropic etching steps are
performed using the same mask 242, therefore, the total number of
photomask is reduced.
[0045] As the etching rate for the dielectric layers 232, 234, 236
and 238 is different from each other. Consequently, after the
isotropic etching step, the etched portion of each of the
dielectric layers 232, 234, 236 and 238 is uneven. In this
embodiment, the etching rate gradually decreases from the topmost
dielectric layer 238 to the bottommost dielectric layer 232. In
FIG. 5D, the etching mask 242 is removed. As shown in the figure,
the opening 248 has a stair-like profile with two slanting
sidewalls. Each slanting sidewall can further be divided into four
small slopes.
[0046] In FIG. 5E, a conductive layer 250 is formed along the
surface profile of the opening 248. That is, the conformal
conductive layer 250 is formed on the dielectric layer 240 and the
device region 224 exposed within the opening 248. In FIG. 5F, a
dielectric layer 252 conformal to the conductive layer 250 is
formed on the conductive layer 250. A conductive layer 254 is
further formed on the dielectric layer 252. The material for
forming the dielectric layer 252 includes silicon nitride, silicon
oxide, oxide/nitride/oxide (ONO), a lead zirconium titanate,
bismuth strontium titanate and tantalum oxide. The conductive
layers 250 and 254 include polysilicon and tungsten silicide. As
the conductive layer 250 is conformal to the surface profile of the
opening 248 (the dielectric layer 240), and the dielectric layer
252 is conformal to the conductive layer 250, the dielectric layer
252 is thus formed with a stair-like surface profile. Consequently,
the effective surface of the dielectric layer 252 is enlarged and
the capacitance is greatly increased.
[0047] The invention provides at least the following
advantages:
[0048] (1) As the anisotropic and isotropic etching steps for
forming the opening within the dielectric layer use the same
etching mask, the total number of the photomasks used in this
method is reduced.
[0049] (2) The opening is formed with a stair-like profile that has
a greatly enlarged surface area to enable the dielectric layer
formed subsequently to have an increased effective surface for the
capacitor.
[0050] (3) While forming a gate in the opening, the dielectric
layer between the floating gate and the control gate has an
increases surface without resulting the vertical etching
thickness.
[0051] (4) As the effective surface of the dielectric layer between
the control gate and the floating gate, or between the top and
bottom electrode of a capacitor, is increased, the performance of
the device is greatly enhanced.
[0052] Other embodiments of the invention will appear to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein. It is intended that the
specification and examples to be considered as exemplary only, with
a true scope and spirit of the invention being indicated by the
following claims.
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