U.S. patent application number 09/835582 was filed with the patent office on 2002-05-02 for semiconductor module.
This patent application is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Matsumoto, Hideo.
Application Number | 20020050633 09/835582 |
Document ID | / |
Family ID | 18808673 |
Filed Date | 2002-05-02 |
United States Patent
Application |
20020050633 |
Kind Code |
A1 |
Matsumoto, Hideo |
May 2, 2002 |
SEMICONDUCTOR MODULE
Abstract
Providing a semiconductor module comprising a plurality of
semiconductor elements, in which wiring lengths of the
semiconductor elements juxtaposed to each other are approximately
the same. A semiconductor module comprising a lower layer substrate
and an upper layer substrate, in which a first and a second
electrode pads formed in a front surface of the lower layer
substrate are connected with a first and a second wires by a first
and a second bridge wires disposed in a back surface of the upper
layer substrate.
Inventors: |
Matsumoto, Hideo; (Tokyo,
JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Assignee: |
Mitsubishi Denki Kabushiki
Kaisha
2-3, Marunouchi 2-chome Chiyoda-ku
Tokyo
JP
|
Family ID: |
18808673 |
Appl. No.: |
09/835582 |
Filed: |
April 17, 2001 |
Current U.S.
Class: |
257/685 ;
257/691; 257/701; 257/704; 257/725; 257/784; 257/E25.015;
257/E25.016 |
Current CPC
Class: |
H01L 2224/49175
20130101; H01L 2224/49111 20130101; H01L 2924/13055 20130101; H01L
2224/49175 20130101; H01L 2924/00014 20130101; H01L 2224/451
20130101; H01L 2924/1305 20130101; H01L 2924/01005 20130101; H01L
2924/01029 20130101; H01L 2224/49111 20130101; H01L 2924/01058
20130101; H01L 2924/01068 20130101; H01L 2224/48137 20130101; H01L
2924/00014 20130101; H01L 2224/48091 20130101; H01L 24/45 20130101;
H01L 23/64 20130101; H01L 2924/1305 20130101; H01L 2924/181
20130101; H01L 2924/181 20130101; H01L 2224/49111 20130101; H01L
2224/73265 20130101; H01L 2924/30105 20130101; H01L 25/071
20130101; H01L 2224/48227 20130101; H01L 2224/4917 20130101; H01L
2924/19107 20130101; H01L 2224/32225 20130101; H01L 25/072
20130101; H01L 2924/3011 20130101; H01L 24/49 20130101; H01L 24/48
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2224/48227 20130101; H01L 2224/48137
20130101; H01L 2224/48137 20130101; H01L 2924/00014 20130101; H01L
2924/00 20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2224/48227 20130101; H01L 2924/00014
20130101; H01L 2224/32225 20130101; H01L 2224/05599 20130101; H01L
2924/00012 20130101; H01L 2224/49175 20130101; H01L 2924/01006
20130101; H01L 2224/48139 20130101; H01L 2224/451 20130101; H01L
2224/48091 20130101; H01L 2224/73265 20130101; H01L 2924/01039
20130101; H01L 2924/014 20130101 |
Class at
Publication: |
257/685 ;
257/691; 257/701; 257/704; 257/725; 257/784 |
International
Class: |
H01L 023/02 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 31, 2000 |
JP |
2000-332471 |
Claims
What is claimed is:
1. A semiconductor module in which at least two semiconductor
elements arranged along a certain direction, and at least two
electrode pad regions arranged along a direction approximately
perpendicular to said certain direction, are respectively connected
in parallel to each other, characterized in comprising: a) a base
plate; b) a lower layer substrate comprising: a first insulation
substrate in approximately rectangular shape with the back surface
fixed on said base plate; a first and a second electrode pads in
approximately identical shapes disposed on a front surface of said
first insulation substrate along one side of said first insulation
substrate so as to be juxtaposed to each other in this order from a
corner portion of said one side; and a first and a second wires
which are juxtaposed to each other along other side of said first
insulation substrate approximately perpendicular to said one side
and including said corner portion of said one side, said second
wire extending by the side of said first and said second electrode
pads, and said first wire extending by the side of said first
electrode pad with said second wire interposed; c) an upper layer
substrate disposed on said lower layer substrate, comprising: a
second insulation substrate in approximately rectangular shape; and
a first bridge wire connecting said first wire with said first
electrode pad and a second bridge wire connecting said second wire
with said second electrode pad, which are formed in a back surface
of said second insulation substrate; d) a first semiconductor
element electrically connected with said first wire and a second
semiconductor element electrically connected with said second wire,
which are formed in a front surface of said second insulation
substrate; and e) a cap disposed on said base plate so as to cover
said lower layer substrate, said upper layer substrate, and said
first and said second semiconductor elements.
2. The semiconductor module according to claim 1 further comprising
a solder resist layer coating a front surface of said lower layer
substrate, wherein said first bridge wire and both of said first
wire and said first electrode pad are connected with each other by
solder layers buried in holes formed in said solder resist layer,
while said second bridge wire and both of said second wire and said
second electrode pad are connected with each other by solder layers
buried in holes formed in said solder resist layer.
3. The semiconductor module according to claim 1, wherein a surface
area of said lower layer substrate is larger than a surface area of
said upper layer substrate, and said first and said second wires
and said first and said second electrode pads extend beyond said
upper layer substrate covering said lower layer substrate.
4. The semiconductor module according to claim 1, wherein said
first and said second semiconductor elements and said first and
said second wires are connected with each other by bonding wires,
and said first and said second electrode pads and an external
electrode are connected with each other by bonding wires.
5. The semiconductor module according to claim 1, wherein said
semiconductor elements are formed by combinations of insulated gate
bipolar transistors and free wheel diodes.
6. The semiconductor module according to claim 1, wherein a gel
material is injected so as to bury said lower layer substrate, said
upper layer substrate, and said first and said second semiconductor
elements.
7. A semiconductor module in which at least two semiconductor
elements juxtaposed to each other along a certain direction, and an
electrode pad region arranged along a direction approximately
perpendicular to said certain direction, are connected with each
other, comprising: a) a base plate; b) a lower layer substrate
comprising: a first insulation substrate in approximately
rectangular shape with the back surface fixed on said base plate;
and a lower layer wiring conductor in approximately rectangular
shape formed in a front surface of said first insulation substrate,
wherein said lower layer wiring conductor has a slit cut toward
inside from one of the corner portions or the near, an area of said
lower layer wiring conductor along one side adjacent to said corner
portion is a connection area with said semiconductor elements, and
an area of said lower layer wiring conductor along other side
adjacent to said corner portion is said electrode pad region; c) an
upper layer substrate disposed on said lower layer substrate,
comprising: a second insulation substrate in approximately
rectangular shape; and an upper layer wiring conductor in
approximately rectangular shape formed in a back surface of said
second insulation substrate and connected with said lower layer
wiring conductor via a solder layer, wherein said upper layer
wiring conductor has a slit in a portion overlapping said slit of
said lower layer wiring conductor in the approximately identical
shape; d) a first and a second semiconductor elements electrically
connected with said connection area of said lower layer wiring
conductor, and formed in a front surface of said second insulation
substrate; and e) a cap disposed on said base plate so as to cover
said lower layer substrate, said upper layer substrate, and said
first and said second semiconductor elements.
8. The semiconductor module according to claim 7, wherein a surface
area of said lower layer substrate is larger than a surface area of
said upper layer substrate, and said connection area and said
electrode pad region extend beyond said upper layer substrate
covering said lower layer substrate.
9. The semiconductor module according to claim 7, wherein said
first and said second semiconductor elements and said connection
area are connected with each other by bonding wires, and said
electrode pad region and an external electrode are connected with
each other by a bonding wire.
10. The semiconductor module according to claim 7, wherein said
semiconductor elements are formed by combinations of insulated gate
bipolar transistors and free wheel diodes.
11. The semiconductor module according to claim 7, wherein a gel
material is injected so as to bury said lower layer substrate, said
upper layer substrate, and said first and said second semiconductor
elements.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor module, and
more particularly, a semiconductor module comprising a plurality of
semiconductor elements connected in parallel to each other.
[0002] FIG. 7A is a plan view of a conventional semiconductor
module (a lid portion is not shown), and FIG. 7B is a cross
sectional view along lines IV-IV in FIG. 7B.
[0003] As shown in FIGS. 7A and 7B, in the conventional
semiconductor module generally denoted at 200, an insulation
substrate 71 is placed on a base plate 1. In a front surface of the
insulation substrate 71, a gate wire pattern 14, a collector wire
pattern 72, and an emitter wire pattern 73 are formed. On the
collector wire pattern 72, a plurality of insulated gate bipolar
transistors 31 (hereinafter referred to as "IGBTs") and free wheel
diodes 32 (hereinafter referred to as "diodes") are disposed.
Collectors of the IGBTs 31 and cathodes of the diodes 32 are
connected with the collector wire pattern 72.
[0004] As shown in FIG. 7A, the emitter wire pattern 73 is formed
in the shape of the letter "L" along two sides of the collector
wire pattern 72. Meanwhile, the gate wire pattern 14 is formed
along other one side of the collector wire pattern 72. This is for
the ease of work at a bonding step for connecting the respective
wire patterns with the IGBTs 31 and the like.
[0005] A back surface pattern 74 is formed in a back surface of the
insulation substrate 71, and fixed on the base plate 1 by a solder
layer 2.
[0006] The IGBTs 31 and the diodes 32 are connected respectively
with the gate wire pattern 14 and the emitter wire pattern 73 by
bonding wires 35 and 34. Further, the gate wire pattern 14, the
emitter wire pattern 73 and the collector wire pattern 72 are
connected respectively with gate electrodes 41, collector
electrodes 42 and emitter electrodes 43 by bonding wires 36, 37 and
38.
[0007] A case portion 6 is formed on the base plate 1 so as to
surround the insulation substrate 71. After wire bonding of the
IGBTs 31 and the like, a gel material 7 for sealing is injected
inside the case portion 6, and a lid portion 8 is put on.
[0008] In the semiconductor module 200 with the conventional
structure, since wiring distances from the emitter electrodes 43 to
the diodes 32 arranged in parallel to each other are different from
each other, loads (such as impedance, capacitance) of the wires are
different from each other among the diodes 32. Hence, even when the
semiconductor module is applied with a constant voltage, for
example, voltages applied to the diodes 32 arranged in parallel to
each other are different from each other, which may destroy some of
the diodes. This also applies to the IGBTs 31.
[0009] In addition, to allow the semiconductor module to carry a
large current, it is necessary that a cross section of the wire
patterns has a large size. In contradiction to this, if the wire
patterns are thick, there is a problem that the insulation
substrate 71 cracks due to a difference in expansion coefficient
between the insulation substrate 71 of a ceramic material and the
wire pattern 73 of metal. Further, if the width of the wire pattern
73 is large, there is a problem that it is difficult to complete
the semiconductor module in a small size.
SUMMARY OF THE INVENTION
[0010] In view of this, a first object of the present invention is
to provide a semiconductor module in which wiring lengths of
semiconductor elements arranged in parallel to each other are
approximately the same.
[0011] A second object of the present invention is to provide a
semiconductor module in which a cross section of wire patterns has
a large size without increasing a module size.
[0012] The present invention is directed to a semiconductor module
in which at least two semiconductor elements arranged along a
certain direction, and at least two electrode pad regions arranged
along a direction approximately perpendicular to said certain
direction, are respectively connected in parallel to each other,
characterized in comprising:
[0013] a) a base plate;
[0014] b) a lower layer substrate comprising: a first insulation
substrate in approximately rectangular shape with the back surface
fixed on said base plate; a first and a second electrode pads in
approximately identical shapes disposed on a front surface of said
first insulation substrate along one side of said first insulation
substrate so as to be juxtaposed to each other in this order from a
corner portion of said one side; and first and second wires which
are juxtaposed to each other along other side of said first
insulation substrate approximately perpendicular to said one side
and including said corner portion of said one side, said second
wire extending by the side of said first and said second electrode
pads, and said first wire extending by the side of said first
electrode pad with said second wire interposed;
[0015] c) an upper layer substrate disposed on said lower layer
substrate, comprising: a second insulation substrate in
approximately rectangular shape; and a first bridge wire connecting
said first wire with said first electrode pad and a second bridge
wire connecting said second wire with said second electrode pad,
which are formed in a back surface of said second insulation
substrate;
[0016] d) a first semiconductor element electrically connected with
said first wire and a second semiconductor element electrically
connected with said second wire, which are formed in a front
surface of said second insulation substrate; and
[0017] e) a cap disposed on said base plate so as to cover said
lower layer substrate, said upper layer substrate, and said first
and said second semiconductor elements.
[0018] In this semiconductor module, wiring lengths from the
semiconductor elements to emitter electrodes are approximately
uniform between the semiconductor elements arranged in parallel to
each other.
[0019] This allows achieving approximately the same loads, such as
impedances, between the wires arranged in parallel to each
other.
[0020] As a result, it is possible to prevent overload-induced
malfunction of some semiconductor elements occurring in a
conventional semiconductor module, and hence, to improve the
reliability of the semiconductor module.
[0021] Since a semiconductor module herein described comprises two
semiconductor elements, a semiconductor module comprising three or
more semiconductor elements is also within the scope of the present
invention. Further, the cap portion is formed by a case portion and
a lid portion.
[0022] The present invention is also directed to a semiconductor
module further comprising a solder resist layer coating a front
surface of said lower layer substrate, characterized in that said
first bridge wire and both of said first wire and said first
electrode pad are connected with each other by solder layers buried
in holes formed in said solder resist layer, while said second
bridge wire and both of said second wire and said second electrode
pad are connected with each other by solder layers buried in holes
formed in said solder resist layer.
[0023] Use of the solder resist layer makes it easy to use a
structure in which wire layers intersect each other.
[0024] A surface area of said lower layer substrate is preferably
larger than a surface area of said upper layer substrate, and said
first and said second wires and said first and said second
electrode pads extend preferably beyond said upper layer substrate
covering said lower layer substrate.
[0025] With this structure, it is easy to perform wire bonding.
[0026] The first and said second semiconductor elements and said
first and said second wires may be connected with each other by
bonding wires and said first and said second electrode pads and an
external electrode may be connected with each other by bonding
wires.
[0027] The present invention is directed further to a semiconductor
module in which at least two semiconductor elements juxtaposed to
each other along a certain direction, and an electrode pad region
arranged along a direction approximately perpendicular to said
certain direction, are connected with each other, characterized in
comprising:
[0028] a) a base plate;
[0029] b) a lower layer substrate comprising: a first insulation
substrate in approximately rectangular shape with the back surface
fixed on said base plate; and a lower layer wiring conductor in
approximately rectangular shape formed in a front surface of said
first insulation substrate, wherein said lower layer wiring
conductor has a slit cut toward inside from one of the corner
portions or the near, an area of said lower layer wiring conductor
along one side adjacent to said corner portion is a connection area
with said semiconductor elements, and an area of said lower layer
wiring conductor along other side adjacent to said corner portion
is said electrode pad region;
[0030] c) an upper layer substrate disposed on said lower layer
substrate, comprising: a second insulation substrate in
approximately rectangular shape; and an upper layer wiring
conductor in approximately rectangular shape formed in a back
surface of said second insulation substrate and connected with said
lower layer wiring conductor via a solder layer, wherein said upper
layer wiring conductor has a slit in a portion overlapping said
slit of said lower layer wiring conductor in the approximately
identical shape;
[0031] d) a first and a second semiconductor elements electrically
connected with said connection area of said lower layer wiring
conductor, which are formed in a front surface of said second
insulation substrate; and
[0032] e) a cap disposed on said base plate so as to cover said
lower layer substrate, said upper layer substrate, and said first
and said second semiconductor elements.
[0033] In this semiconductor module, variations in wiring length
between the semiconductor elements and emitter electrodes are
small, which in turn reduces variations in load such as
impedance.
[0034] As a result, it is possible to prevent overload-induced
malfunction of some semiconductor elements occurring in a
conventional semiconductor module, and hence, to improve the
reliability of the semiconductor module.
[0035] Further, since a cross section of the wire patterns has a
large size, impedance is small, and therefore, characteristics of
the semiconductor module improve.
[0036] It is preferable that a surface area of said lower layer
substrate is larger than a surface area of said upper layer
substrate, and said connection area and said electrode pad region
extend beyond said upper layer substrate covering said lower layer
substrate.
[0037] With this structure, it is easy to perform wire bonding.
[0038] The first and said second semiconductor elements and said
connection area may be connected with each other by bonding wires,
and said electrode pad region and an external electrode may be
connected with each other by a bonding wire.
[0039] The semiconductor elements may be formed by combinations of
insulated gate bipolar transistors and free wheel diodes.
[0040] Further, a gel material may be injected so as to bury said
lower layer substrate, said upper layer substrate, and said first
and said second semiconductor elements.
[0041] This allows to fix the semiconductor elements, and hence, to
improve the reliability of the semiconductor module.
[0042] As described clearly above, the wiring lengths of the
semiconductor elements juxtaposed to each other are approximately
uniform in the semiconductor module according to the present
invention, and therefore, the reliability of the semiconductor
module improves.
[0043] Also, in the semiconductor module according to the present
invention, the cross section area of the wire portions increases,
and therefore, impedance and the like decreases and the
capabilities of the semiconductor module improve.
BRIEF DESCRIPTION OF THE DRAWINGS
[0044] FIGS. 1A and 1B show the semiconductor module according to
the first embodiment of the present invention.
[0045] FIG. 2 shows the front surface of the lower layer substrate
in the semiconductor module according to the first embodiment of
the present invention.
[0046] FIG. 3 shows the back surface of the upper layer substrate
in the semiconductor module according to the first embodiment of
the present invention.
[0047] FIG. 4 shows the semiconductor module according to the
second embodiment of the present invention.
[0048] FIG. 5 shows the front surface of the lower layer substrate
in the semiconductor module according to the second embodiment of
the present invention.
[0049] FIG. 6 shows the back surface of the upper layer substrate
in the semiconductor module according to the second embodiment of
the present invention.
[0050] FIGS. 7A and 7B show a conventional semiconductor
module.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0051] First Embodiment
[0052] FIGS. 1A and 1B show a semiconductor module according to a
first embodiment. FIG. 1A is a plan view (a lid portion is not
shown) of the semiconductor module according to the first
embodiment, and FIG. B is a cross sectional view along lines I-I in
FIG. 1A.
[0053] As shown in FIGS. 1A and 1B, in the semiconductor module
according to the first embodiment generally denoted at 100, a lower
layer substrate 10 is placed on a base plate 1. The lower layer
substrate 10 comprises a first insulation substrate 11. The first
insulation substrate 11 is formed by a ceramic material such as
AIN. In a front surface of the first insulation substrate 11, a
gate wire pattern 14, emitter wire patterns 12 and emitter
electrode pads 13 are formed. These wire patterns are of copper,
for instance.
[0054] FIG. 2 shows a front surface of the lower layer substrate
10. Along an x-direction of the first insulation substrate 11, the
emitter wire patterns 12 are juxtaposed to each other. Further,
along a y-direction of the first insulation substrate 11, the
emitter electrode pads 13 in approximately the same shapes are
juxtaposed to each other.
[0055] The emitter wire patterns 12 have approximately the same
widths (x-direction) but increasingly longer lengths (y-direction)
with a distance toward the emitter electrode pads 13.
[0056] Meanwhile, in a bottom end portion of the first insulation
substrate 11, the gate wire pattern 14 is disposed along the
x-direction.
[0057] A solder resist layer 15 is formed at an area seating an
upper layer substrate 20 in the front surface of the first
insulation substrate 11. The solder resist layer 15 is formed by an
insulation material such as an epoxy-based insulation material.
[0058] Opening portions 16 and 17 are formed at predetermined
positions of the solder resist layer 15. The emitter wire patterns
12 are exposed in the opening portions 16. The emitter electrode
pads 13 are exposed in the opening portions 17.
[0059] Further, a back surface pattern 18 of a metallic layer is
formed in a back surface of the first insulation substrate 11. The
back surface pattern 18 is fixed on a front surface of the base
plate 1 by a solder layer 2.
[0060] The upper layer substrate 20 is placed on the lower layer
substrate 10. Bridge wire patterns 22 are disposed in a back
surface of the upper layer substrate 20.
[0061] FIG. 3 shows the back surface of the upper layer substrate
20. The upper layer substrate 20 comprises a second insulation
substrate 21. The bridge wire patterns 22 are juxtaposed to each
other along a y-direction of the second insulation substrate
21.
[0062] A solder resist layer 25 is disposed in a back surface of
the second insulation substrate 21. Opening portions 26 and 27 are
formed in the solder resist layer 25. The bridge wire patterns 22
are exposed within the opening portions 26 and 27. Also, the
opening portions 26 and 27 are formed so as to be located over the
opening portions 16 and 17 formed in the lower layer substrate 10
when the upper layer substrate 20 is placed on the lower layer
substrate 10.
[0063] The emitter wire patterns 12 and the emitter electrode pads
13 of the lower layer substrate 10 and the bridge wire patterns 22
of the upper layer substrate 20 are electrically connected with
each other by solder layers 3 and 4 which are buried in the opening
portions 16, 17, 26 and 27.
[0064] On the other hand, a collector wire pattern 28 is disposed
in a front surface of the second insulation substrate 21.
[0065] Combinations of IGBTs (insulated gate bipolar transistors)
31 and diodes (free wheel diodes) 32 are arranged next to each
other along an x-direction on the collector wire pattern 28. The
IGBTs 31 and the diodes 32 are connected with the collector wire
pattern 28 by a solder layer 5. This electrically connects
collector electrodes (not shown) of the IGBTs 31 and cathodes (not
shown) of the diodes with the collector wire pattern 28.
[0066] Emitter electrodes (not shown) of the IGBTs 31 and anodes
(not shown) of the diodes are connected by bonding wires 33.
Further, the anodes of the diodes are connected with the emitter
wire patterns 12 formed on the lower layer substrate 10, by bonding
wires 34.
[0067] In addition, gate electrodes (not shown) of the IGBTs 31 are
connected with the gate wire pattern 14 by bonding wires 35. The
gate wire pattern 14 is connected with gate electrodes 41 by
bonding wires 36.
[0068] Meanwhile, the collector wire pattern 28 is connected with
the collector electrodes 42 by bonding wires 37. Also, the emitter
electrode pads 13 are connected with the emitter electrodes 43 by
bonding wires 38.
[0069] A case portion 6 is formed on the base plate 1 so as to
surround the lower layer substrate 10 and the like. After wire
bonding of the IGBTs 31 and the like, a gel material 7 for sealing
is injected inside the case portion 6, and a lid portion 8 is put
on.
[0070] As the lid portion 8 is fit with the case portion 6, the
lower layer substrate 10 and the like are sealed off within a cap
portion (not shown) formed by the case portion 6 and the lid
portion 8.
[0071] Thus, in the semiconductor module 100 according to the first
embodiment, the emitters of the IGBTs 31 and the anodes of the
diodes 32 are connected respectively with the emitter electrodes 43
via the emitter wire patterns 12, the solder layer 3, the bridge
wire patterns 22, the solder layer 4, and the emitter electrode
pads 13.
[0072] In this case, as shown in FIGS. 2 and 3, the emitter wire
pattern 12 shortest in the y-direction is connected with the bridge
wire pattern 22 longest in the x-direction. Meanwhile, the emitter
wire pattern 12 longest in the y-direction is connected with the
bridge wire pattern 22 shortest in the x-direction.
[0073] This allows that wiring lengths from the IGBTs 31 and the
diodes 32 to the emitter electrodes 43 are approximately uniform
among the IGBTs 31 arranged side to side.
[0074] As a result, loads such as impedance from the IGBTs 31 and
the diodes 32 to the emitter electrodes 43 are approximately
uniform among the wires juxtaposed to each other. Hence, it is
possible to prevent overload-induced malfunction of some
semiconductor elements occurring in a conventional semiconductor
module, and hence, to improve the reliability of the semiconductor
module.
[0075] Second Embodiment
[0076] FIG. 4 is a top surface view of a semiconductor module 101
according to a second embodiment.
[0077] In the semiconductor module 101, a wire pattern 55 formed in
a front surface of a lower layer substrate 50 and a wire pattern 61
formed in a back surface of an upper layer substrate 60 are
different from the semiconductor module 100 according to the first
embodiment. Other elements in the structure are the same as in the
semiconductor module 100, and therefore, are denoted at the same
reference symbols as those used for the first embodiment.
[0078] FIG. 5 shows a front surface of the lower layer substrate
50. The lower layer substrate 50 comprises a first insulation
substrate 51 of AIN, for example. A lower layer wiring conductor 52
of copper, for instance, in approximately rectangular shape is
disposed on the first insulation substrate 51. Also, the gate wire
pattern 14 extending along the x-direction is disposed in a bottom
end portion of the first insulation substrate 51.
[0079] In the lower layer wiring conductor 52, a slit 53 is cut
toward inside from a corner portion. Areas adjacent the slit 53 are
a connection area 55 and an electrode pad area 56.
[0080] FIG. 6 shows a back surface of the upper layer substrate 60.
The upper layer substrate 60 comprises a second insulation
substrate 61 of AIN, for example. An upper layer wiring conductor
62 of copper, for instance, in approximately rectangular shape is
disposed on the second insulation substrate 61.
[0081] In the upper layer wiring conductor 62, a slit 63 is cut
toward inside from a corner portion.
[0082] As shown in FIG. 4, when the upper layer substrate 60 is
placed on the lower layer substrate 50, the slit 63 overlaps the
slit 53. The lower layer wiring conductor 52 and the upper layer
wiring conductor 62 are electrically connected by a solder layer
(not shown).
[0083] The diodes 32 are connected with the connection area 55 by
the bonding wires 34. The electrode pad area 56 is connected with
the emitter electrodes 43 by the bonding wires 38. Other wires are
similar to those in the first embodiment.
[0084] The case portion 6 is formed on the base plate 1 so as to
surround the lower layer substrate 50 and the like. After wire
bonding of the IGBTs 31 and the like, a gel material for sealing
(not shown) is injected inside the case portion 6, and a lid
portion (not shown) is put on.
[0085] Thus, in the semiconductor module 101 according to the
second embodiment, the slits 53 and 63 are formed in the lower
layer wiring conductor 52 and the upper layer wiring conductor 62.
Hence, wiring lengths to the electrode pad area 56 from the diodes
connected with the connection area 55 in the vicinity of the slits
53 and 63 are longer than where the slits 53 and 63 are not formed.
This reduces differences in the wiring lengths from the diodes 32
connected with the connection area 55 in the vicinity of the slits
53 and 63 (the right-hand side to the area 55 in FIG. 5) and from
the diodes 32 connected with the connection area 55 far away from
the slits 53 and 63 (the left-hand side to the area 55 in FIG. 5).
As a result, as in the first embodiment, it is possible to reduce
variations in loads such as impedance measured from the IGBTs 31
and the diodes 32 to the emitter electrodes 43 among the elements
arranged in parallel to each other. This makes it possible to
prevent overload-induced malfunction of some semiconductor elements
occurring in the conventional semiconductor module 200, and hence,
to improve the reliability of the semiconductor module.
[0086] Further, in the semiconductor module 101, the wire portions
from the connection area 55 to the electrode pad area are formed by
the lower layer wiring conductor 52, the upper layer wiring
conductor 62 and the solder layers fixing the portions between the
sames. This increases a cross section area of the wire portions,
and decreases impedance.
[0087] While the slits 53 and 63 are cut toward inside from the
corner portions of the lower layer wiring conductor 52 and the
upper layer wiring conductor 62 in the second embodiment, the slits
may be formed except for in the corner portions. Further, the
shapes and the lengths of the slits may be changed depending on the
number of the semiconductor elements and the like.
* * * * *