U.S. patent application number 09/340498 was filed with the patent office on 2002-04-25 for method and apparatus for selecting a separate functional space in a low pin count memory device.
Invention is credited to POISNER, DAVID I..
Application Number | 20020049880 09/340498 |
Document ID | / |
Family ID | 23333622 |
Filed Date | 2002-04-25 |
United States Patent
Application |
20020049880 |
Kind Code |
A1 |
POISNER, DAVID I. |
April 25, 2002 |
METHOD AND APPARATUS FOR SELECTING A SEPARATE FUNCTIONAL SPACE IN A
LOW PIN COUNT MEMORY DEVICE
Abstract
The present invention is an apparatus and method for selecting
one of a first and a second storage element in response to a
control signal issued by a processor in a low pin count device. The
apparatus comprises a decoder to receive the control signal and an
address signal having a select bit indicative of one of the first
and the second storage elements. The decoder generates a select
signal to access one of the first and the second storage elements
based on the select bit.
Inventors: |
POISNER, DAVID I.; (FOLSOM,
CA) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR AND ZAFMAN LLP
12400 WILSHIRE BOULEVARD 7TH FLOOR
LOS ANGELES
CA
90025
|
Family ID: |
23333622 |
Appl. No.: |
09/340498 |
Filed: |
June 30, 1999 |
Current U.S.
Class: |
711/1 ; 711/170;
711/209 |
Current CPC
Class: |
G06F 12/06 20130101 |
Class at
Publication: |
711/1 ; 711/170;
711/209 |
International
Class: |
G06F 012/00 |
Claims
What is claimed is:
1. An apparatus for selecting one of a first and a second storage
elements in response to a signal issued by a processor in a low pin
count device, comprising: a decoder to receive an address signal
having a select bit indicative of one of the first and the second
storage elements, the decoder to generate a select signal to access
one of the first and the second storage elements based on the
select bit.
2. The apparatus of claim 1, wherein the first storage element is a
memory element and the second storage element is a register
element.
3. The apparatus of claim 2, wherein the select bit has a first
value representative of an access to or from the memory element,
and a second value representative of an access to or from the
register element.
4. The apparatus of claim 3, wherein the access is a read
operation.
5. The apparatus of claim 3, wherein the access is a write
operation.
6. The apparatus of claim 1, wherein the decoder also receives a
control signal having a value indicating that the access is a read
operation.
7. The apparatus of claim 6, wherein the control signal having a
value indicating that the access is a write operation.
8. A method for selecting one of a first and a second storage
elements, in response to a signal issued by a processor in a low
pin count device, comprising: (a) receiving an address signal
having a select bit indicative of one of the first and the second
storage elements; (b) generating a select signal to access one of
the first and the second storage elements based on the select bit;
and (c) accessing one of the first and the second storage
elements.
9. The method of claim 8, wherein in (a), the first storage element
is a memory element and the second storage element is a register
element.
10. The method of claim 9, wherein in (a), the select bit has a
first value representative of an access to or from the memory
element, and a second value representative of an access to or from
the register element.
11. The method of claim 10, wherein in (a) the access is a read
operation.
12. The method of claim 10, wherein in (a) the access is a write
operation.
13. The method of claim 8, further comprising: receiving a control
signal having a value indicating that the access is a read
operation.
14. The method of claim 8, further comprising: receiving a control
signal having a value indicating that the access is a write
operation.
15. A system for selecting one of a first and a second storage
elements in a processor-based system, in response to a signal
issued by a processor in a low pin count device, the system
comprising: a memory for storing instruction sequences by which the
processor-based system is processed, the memory having a first and
a second storage elements; a processor coupled to said memory, the
processor executes the stored instruction sequences; wherein the
stored instruction sequences cause the processor to: (a) receive an
address signal having a select bit indicative of one of the first
and the second storage elements; (b) generate a select signal to
access one of the first and the second storage elements based on
the select bit; and (c) access one of the first and the second
storage elements.
16. The system of claim 15, wherein the first storage element is a
memory element and the second storage element is a register
element.
17. The system of claim 16, wherein the select bit has a first
value representative of an access to or from the memory element,
and a second value representative of an access to or from the
register element.
18. The system of claim 17, wherein the access is a read
operation.
19. The system of claim 17, wherein the access is a write
operation.
20. The system of claim 15, wherein the stored instruction
sequences further cause the processor to receive a control signal
having a value indicating that the access is a read operation.
21. The system of claim 15, wherein the stored instruction
sequences further cause the processor to receive a control signal
having a value indicating that the access is a write operation.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to memory in
processor-based or microcontroller-based systems, and more
particularly, to an apparatus and method of selecting functional
space in a low pin count memory device.
[0003] 2. Description of the Related Art
[0004] In processor-based systems such as computers, an address
space may correspond to several functional spaces. To allow the
processor to access these functional spaces, extra signals or
signal lines are used. For example, a dedicated pin is typically
provided on a chip so as to access a separate functional space in a
memory component, such as register space. Such a separate
functional space in the memory component is typically mapped to the
same address space as the main memory, i.e., to memory space. This
mapping scheme presents several problems, the most significant of
which is the resulting error created when an access to the main
memory is mapped to that intended for the register space. The
implementation of a dedicated pin for accessing one of several
functional spaces is particularly problematic in Low Pin Count
(LPC) (refer to
http://developer.intel.com/design/chipsets/industry/lpc.sub.--100.pdf)
memory devices, as a minimal number of pins are implemented in
these devices so as to reduce the requirements for space, cost and
testing procedures.
[0005] Accordingly, there is a need in the technology for an
apparatus and method for overcoming the aforementioned problem. In
particular, there is a need for an apparatus and method for
allocating functional space in an LPC memory device so as to
overcome the aforementioned problem.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a system block diagram of an exemplary LPC
processor system in which the apparatus and method of the present
invention is used.
[0007] FIG. 2 illustrates a detailed schematic diagram of the
memory module 14 in which the present invention is implemented.
[0008] FIG. 3A is a logic diagram illustrating the principles of
the present invention.
[0009] FIG. 3B is a logic diagram illustrating an alternate
embodiment of the present invention.
[0010] FIG. 4 is a flow chart illustrating one embodiment of the
process flow of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED INVENTION
[0011] The present invention utilizes a memory configuration bit
located in an address to indicate the use of either of the memory
space or the register space in a low pin count (LPC) memory device,
for the associated operation. In one embodiment, the memory select
bit is located adjacent the most significant address bit in the
address.
[0012] The present embodiment is described in reference to a
processor system 10. FIG. 1 illustrates an exemplary LPC processor
system 10 which implements the processes of the present invention.
The processor system 10 comprises a processor 12 (such as a central
processing unit) and a memory module 14. The memory module 14
includes a standard memory location 14a, a register location 14b
and a memory decoder 14c. In one embodiment, the memory module 14
is a main memory that may be implemented by a random access memory
(RAM) or a flash memory or a combination thereof. The processor 12
and memory module 14 are coupled to a system bus 16. In one
alternate embodiment, the memory module 14 is coupled to an I/O bus
20. The processor system 10 may also include various I/O and
peripheral modules (MISC I/O #1, #2, . . . #N) which are coupled
along the I/O bus 20 that is in turn coupled to the system bus 16
via a bus bridge 22. Examples of the peripheral modules include a
console, a printer and a mouse. In one embodiment, the processor 12
includes any one of the x86, Pentium.TM., Pentium II.TM. and
Pentium Pro.TM. microprocessors as marketed by Intel Corporation.
It is understood by one of ordinary skill in the technology that
the present invention can be implemented in any processor-based
system.
[0013] FIG. 2 illustrates a detailed schematic diagram of the
memory module 14 in which the present invention is implemented. As
shown, an address 50 issued by the processor 12 in an LPC device,
is A bits long, where in one embodiment, A comprises bits A1-A21
and bits A22-A32. In one embodiment, bits A1-A21 are the address
bits, with A1 being the least significant address bit, A21 being
the most significant address bit and A22-A32 being additional
information-bearing bits. In the embodiment as implemented in an
LPC device, flash memory in the firmware hub is typically divided
into two zones: the first for storing Basic Input/Output System
(BIOS) code and data, and the second, typically referred to as
feature, is an alias to the memory space, such as memory element
14a. The second zone provides a predetermined portion of register
space, such as register element 14b.
[0014] In one embodiment, the present invention utilizes bit A22 as
a memory select bit, to indicate if a corresponding operation is
intended for the memory space or element 14a or the register space
or element 14b. As described in the present embodiment, the memory
select bit (e.g., A22) is located adjacent to the most significant
address bit (e.g., A21). However, it is understood that in
alternate embodiments, the memory configuration bit may be located
in any of the additional information-bearing bits (e.g.,
A22-A32).). It is understood that in alternate embodiments, A may
comprise any predetermined number of bits sufficient for address
identification.
[0015] In addition, a control signal 52 issued by the processor
includes at least two bits, one of which may be used to indicate if
the corresponding cycle is a read operation while another bit may
be used to indicate if the corresponding cycle is a write operation
(see FIG. 3A). In alternate embodiments, a single bit in the
control signal 52 may be used to indicate if the corresponding
cycle is a read or write operation (see FIG. 3B). The address 50
and the control signal are both forwarded to the memory decoder 14c
which decodes the address 50 and determines if the cycle if the
operation associated with the address is intended to access the
memory location 14a or the register location 14b, and if the cycle
is a read or a write operation.
[0016] FIG. 3A is a logic diagram illustrating the principles of
the present invention. In this embodiment, separate bits in the
control signal 52 are used to indicate if the operation associated
with the address is a read or a write operation. For discussion
purposes, the associated bits will hereinafter be referred to as
the read and the write bits. When the read bit is true (or 1), it
indicates that the associated operation involves a read operation.
When the write bit is true (or 1), it indicates that the associated
operation involves a write operation. However, it is understood
that a single bit may be used to represent the read/write operation
status, as shown in FIG. 3B.
[0017] As shown in FIG. 3A, when the read and write are both zero,
there is no associated cycle or operation, regardless of the state
of the memory configuration bit (e.g., A22). When the read bit is
false (or 0) and the write bit is true (or 1), then the associated
operation is a write to the register location 14c if the memory
configuration bit is false (or 0). When the read bit is false (or
0) and the write bit is true (or 1), then the associated operation
is a write to the memory location 14b if the memory configuration
bit is true (or 1).
[0018] When the read bit is true (or 1) and the write bit is false
(or 0), then the associated operation is a read from the register
location 14c if the memory configuration bit is false (or 0). When
the read bit is true (or 1) and the write bit is false (or 0), then
the associated operation is a read from the memory location 14b if
the memory configuration bit is true (or 1).
[0019] Finally, when the read and write are both true (or 1), the
associated operation is invalid, regardless of the state of the
memory configuration bit (e.g., A22).
[0020] FIG. 3B is a logic diagram illustrating an alternate
embodiment of the present invention. In this embodiment, a single
bit in the control signal 52 is utilized to represent the
read/write status associated with an address. As shown, when the
read/write bit is false (or 0), the associated operation is a write
operation. Conversely, when the read/write bit is true (or 1), the
associated operation is a read operation.
[0021] In addition, if the read/write bit is false (or 0), and the
memory configuration bit is 0, then the associated operation is a
write to the register location 14b. If the read/write bit is false
(or 0), and the memory configuration bit is 1, then the associated
operation is a write to the memory location 14a.
[0022] If the read/write bit is true (or 1), and the memory
configuration bit is 0, then the associated operation is a read
from the register location 14b. If the read/write bit is true (or
1), and the memory configuration bit is 1, then the associated
operation is a read from the memory location 14a.
[0023] In an alternate embodiment, the address 50 (see FIG. 2) may
include information representative of whether access associated
with the address 50 is a READ or a WRITE operation. In this
embodiment, the decoder, such as memory decoder 14c will decode the
address signal to determine the type of access associated with the
address 50, prior to performing the process of the invention. FIG.
4 is a flow chart illustrating one embodiment of the process flow
of the present invention. Beginning from a start state, the process
100 proceeds to process block, where it receives the address signal
110. It then advances to decision block 115, where it determines if
the corresponding access is a READ operation. If so, the process
100 proceeds to decision block 120, where it determines if the
memory select bit is true or a "1". If so, the process proceeds to
perform a read operation from the associated memory location, such
as memory element 14a (process block 125). If, at decision block
120, it is determined that the memory select bit is not true, or a
"0", the process 100 proceeds to process block 130, where it
proceeds to perform a READ operation from the corresponding
register location, such as memory element 14b.
[0024] If, at decision block 115, it was determined that the
corresponding access is not a READ operation, but is instead a
WRITE operation, the process 100 proceeds to decision block 135,
where it determines if the memory select bit is true or a "1". If
so, the process 100 proceeds to process block 140, where it
performs a WRITE operation to the corresponding memory location,
such as memory element 14a. If, at decision block 135, it was
determined that the memory select bit is not true, or a "0", the
process 100 proceeds to process block 145, where it proceeds to
perform a WRITE operation to the corresponding register location,
such as memory element 14b. After performing each process 125, 130,
140 or 145, the process 100 terminates.
[0025] Through the use of the present invention, an apparatus and
method for selecting at least one of two separate functional spaces
in a memory component is provided. In particular, the present
invention facilitates selection of at least two separate functional
spaces in a memory component without the need to add additional
pins to a chip. The use of the present invention also prevents
mapping of accesses to a register space to the same address space
as the main memory.
[0026] Although the present invention has been described in terms
of certain preferred embodiments, other embodiments apparent to
those of ordinary skill in the art are also within the scope of
this invention. Accordingly, the scope of the invention is intended
to be defined only by the claims which follow.
* * * * *
References