U.S. patent application number 08/976148 was filed with the patent office on 2002-04-18 for sequence control circuit.
Invention is credited to INAGAKI, TORU.
Application Number | 20020046372 08/976148 |
Document ID | / |
Family ID | 18074756 |
Filed Date | 2002-04-18 |
United States Patent
Application |
20020046372 |
Kind Code |
A1 |
INAGAKI, TORU |
April 18, 2002 |
SEQUENCE CONTROL CIRCUIT
Abstract
A sequence control circuit provided in such as a test pattern
generator of a memory test apparatus, and made capable of
designating a plurality of branches according to a plurality of
branch conditions in describing a test pattern program. This
sequence control circuit comprises a plurality of branch address
registers for storing different branch addresses, respectively, and
a logic operation circuit receiving a plurality of flags for
detecting combinations of flag values. A program counter controller
selects a certain branch address according to a combination of flag
values detected in the logic operation circuit and arranges to load
the branch address stored in the selected branch address register
to a program counter.
Inventors: |
INAGAKI, TORU; (TOKYO,
JP) |
Correspondence
Address: |
KNOBBE MARTENS OLSON & BEAR LLP
620 NEWPORT CENTER DRIVE
SIXTEENTH FLOOR
NEWPORT BEACH
CA
92660
US
|
Family ID: |
18074756 |
Appl. No.: |
08/976148 |
Filed: |
November 21, 1997 |
Current U.S.
Class: |
714/718 ;
365/201; 714/E11.169 |
Current CPC
Class: |
G05B 19/042 20130101;
G05B 2219/23428 20130101; G06F 11/27 20130101 |
Class at
Publication: |
714/718 ;
365/201 |
International
Class: |
G11C 029/00; G11C
007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 27, 1996 |
JP |
316229/1996 |
Claims
What is claimed is:
1. A sequence control circuit comprising: an instruction memory for
storing each of instructions of a program; a plurality of branch
address registers each for storing a branch address; a logic
operation circuit for detecting a combination of flag values by
receiving a plurality of flags; a program counter for outputting an
address to the instruction memory; and a program counter controller
for controlling the program counter according to a control word
read from the instruction memory and for selecting one of the
branch address register corresponding to a combination of the flag
values; wherein the branch address stored in the branch address
register selected by the program counter controller is loaded into
the program counter.
2. The sequence control circuit according to claim 1, further
comprising an index register and an index counter for controlling
loop instructions.
3. The sequence control circuit according to claim 1, wherein the
program is a test program and the sequence control circuit is
provided in a test pattern generator of a memory test apparatus for
performing a test of a semiconductor memory device.
4. The sequence control circuit according to claim 2, wherein the
program is the test program and the sequence control circuit is
provided in the test pattern generator of the memory test apparatus
for performing the test of the semiconductor memory device.
5. The sequence control circuit according to claim 3, wherein the
instruction memory comprises a sequence control instruction area
for storing an operation code part of sequence control instructions
and an operand storing area for storing an operand corresponding to
the operation code part, and the operation code part stored in the
sequence control instruction area is supplied to the program
counter controller as the control word.
6. The sequence control circuit according to claim 4, wherein the
instruction memory comprises a sequence control instruction area
for storing an operation code part of sequence control instructions
and an operand storing area for storing an operand corresponding to
the operation code part, the operation code part stored in said
sequence control instruction area is supplied to the program
counter controller as the control word, and address information
read from the operand storing area is supplied to the index
register.
7. A sequence control circuit provided in a test pattern generator
of a memory test apparatus which performs a test of a semiconductor
memory device, said sequence control circuit having a program
counter, comprising: a detecting means for detecting a combination
of a plurality of branch conditions; a switching means for
switching an address to be loaded into the program counter
according to a detection result of the detecting means.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a sequence control circuit,
in particular to a sequence control circuit to be preferably used
in a test pattern generator of a semiconductor memory test
apparatus.
[0003] 2. Description of the Prior Art
[0004] A memory test apparatus is used for testing a semiconductor
memory device. The memory test apparatus gives an address, data and
a control signal to a memory under test (MUT) based on a
predetermined test program, that is, a pattern program, and
discriminates PASS/FAIL of the MUT by judging whether or not the
data then read from the MUT agree with the expectation data at a
predetermined timing. When address signals, test data signals and
control signals are supplied to the MUT, the expectation data is
considered to mean the data to be outputted from the normal MUT
corresponding to a combination of the above address signals, test
data signals and control signals.
[0005] FIG. 1 is a block diagram showing a basic whole structure of
a conventional memory test apparatus which has been used. The
memory test apparatus 1 performs a test of MUT 2 and comprises: a
timing generator 5 for generating a reference clock; a test pattern
generator 6 for generating address signals, test data signals and
control signals to be given to the MUT 2 by receiving the reference
clock; a waveform shaper 7 for receiving the respective signals
from the test pattern generator 6 and applying these signals to the
MUT 2 after shaping them into waveforms required for the test; and
a logic comparator 8 for receiving the data read from the MUT 2 and
judging PASS/FAIL of the expectation data.
[0006] The test pattern generator 6 produces expectation data in
addition to the address signals, test data signals and control
signals. The expectation data is supplied to the logic comparator 8
from the test pattern generator 6. The logic comparator 8 compares
the expectation data with a data read from MUT 2, performs quality
judgment of the MUT according to match/mismatch of the data and
outputs the result as a PASS/FAIL signal to the test pattern
generator 6. Further, when the logic comparator 8 compares the
output data of the MUT 2 with the expectation data in a specific
cycle of test cycles and detects the agreement between the two, the
logic comparator 8 outputs a match flag MFLG to the test pattern
generator 6. Here, a series of an address, test data and a control
signal to be given to the MUT 2 is called as a test pattern.
[0007] Now, the test pattern generator 6 has an address generator
11, a test data generator 12 and a control signal generator 13
which generates the address signals, the test data and the control
signals to be given to the MUT 2, respectively, and further has a
sequence control circuit 10 which controls the address generator
11, the test data generator 12 and the control signal generator
13.
[0008] FIG. 2 is a block diagram showing an example of an internal
structure of a conventional sequence control circuit.
[0009] The sequence control circuit comprises: an instruction
memory 121 for storing a test program consisting of a series of
instructions for generating a test pattern; a program counter (PC)
122 for designating an address of the instruction memory 121; a
stack register 123 for temporary saving of addresses; a program
counter controller 124 for controlling the program counter 122 and
the stack register 123; a starting address register (STA) 125 for
storing an initial value of the program counter 122; a branch
address register (BAR) 126 for storing an address of a branch
designated by branch instructions; an index register 127; an index
work register 128; and an index counter 129. The index register
127, the index work register 128 and the index counter 129 are all
for controlling loop instructions.
[0010] Every one of instructions to be stored in the instruction
memory 121 is composed of an operation code part, that is, an
operation code part of a sequence control instruction, and an
operand corresponding to each instruction code. Corresponding to
these instructions, the. instruction memory 121 has a pair of a
sequence control instruction area for storing the operation code
part and an operand storing area for storing the operand. In case
of a sequence control circuit of this type, there is an operand of
a type which expresses a designated branch address or loop
conditions in a test program or of a type which describes a
parameter for generating an address, test data and a control signal
to be given to the MUT 2. Accordingly, this sequence control
circuit has, in addition to the above sequence control instruction
area, an address operation area, a data operation area and a
control signal generation instruction area provided in a memory
area of each address of instruction memory 121. The address
operation area, the data operation area and the control signal
generation instruction area are provided in the operand storing
area.
[0011] When the instruction memory 121 is accessed by the address
outputted from the program counter 122, instructions for address
generation, test data generation and control signal generation are
read from the address operation area, the data operation area and
the control signal generation instruction area and then supplied to
the address generator 11 (FIG. 1), the test data generator 12 (FIG.
1) and the control signal generator 13 (FIG. 1), respectively.
Thus, the address generator 11, the test data generator 12 and the
control signal generator 13 generate an address, test data and a
control signal for the MUT 2, respectively.
[0012] The program counter controller 124 receives an operation
code part of sequence control instructions from the instruction
memory 121, a match flag MFLG from the logic comparator 8 (FIG. 1)
and an output of the index counter 129. Based on the result
obtained by decoding the instruction stored in the instruction
memory 121, on the match flag MFLG, and on an output from the index
counter 129, the program counter controller 124 controls the
program counter 122 and the stack register 123. In the concrete,
the program counter controller 124 handles a content of the program
counter 122, that is, the value showing an address to be read next
in the instruction memory 121, through increment, decrement or hold
operation, and loads the value to the program counter 122. For
loading the above value to the program counter 122, the program
counter controller 124 arranges corresponding to the instructions
read out so that any one of (i) an operand of instructions for a
present address of the instruction memory 121, (ii) a content of
the starting address register 125, (iii) a content of the branch
address register 126, and (iv) a content of the stack register 123
is set to the program counter 122 as the value.
[0013] An address read from the operand storing area of the
instruction memory 121 is also supplied to the index register 127.
The index counter 129 controls loop instructions by using this
index register 127 and the index work register 128 which serves as
a work register, and when the counter value coincides with a
specific value, outputs the value to the program counter controller
124 thereby controlling the program counter 122.
[0014] Now in recent years, a semiconductor memory called a flash
memory has been developed and manufactured. The flash memory has a
merit that it is a non-volatile memory and hence it can hold memory
data without particular power supply from outside and can rewrite
data stored in the memory in a state as it mounted on a printed
wiring substrate. Characteristics of the operation of the flash
memory are summarized in the following six items.
[0015] (1) operation mode setting by command input,
[0016] (2) automatic write,
[0017] (3) automatic erase (chip erase/block erase),
[0018] (4) detection of data write completion/erase completion,
[0019] (5) block protection function,
[0020] (6) device code.
[0021] Therefore, it is possible to set automatic erasing activity
to be performed by a chip unit or a block unit in the flash memory
by command input. However, with the flash memory, erasable number
of times for the block unit is limited within a certain value while
having a probability of breaking down a device due to excess
erasing. Therefore, it is necessary to detect the state which
informs of write completion/erase completion. In a test pattern for
performing a flash memory test, according to a detection result,
which is a flag, with reference to a write completion/erase
completion state, it switches the branch address of the program
counter in the sequence control circuit.
[0022] As described above, when the flash memory test is performed,
it is required to switch the branch address in the sequence control
circuit corresponding to the state of a flag. In the conventional
sequence control circuit described above, it is possible to switch
the branch address by an indication of one flag. However, when the
branch address is switched according to a combination of a
plurality of flag values detected from the flash memory, for
example, when the branch address of the pattern program is switched
according to contents of both flags, one flag showing execution or
termination of automatic algorithm and the other flag showing time
limit over, with the conventional sequence control circuit
described above, it is impossible to describe switching of the
branch address like this only with one statement in the test
program.
SUMMARY OF THE INVENTION
[0023] A first object of the present invention is to provide a
sequence control circuit which can designate in a program
description a plurality of branches depending on plural branch
conditions, thereby enabling a user to describe the program
easily.
[0024] A second object of the present invention is to provide a
sequence control circuit which can designate in a test pattern
program description of a semiconductor memory a plurality of
branches depending on plural branch conditions, thereby enabling a
user to describe the pattern program easily and to reduce the test
time. In the concrete, the second object of the present invention
is to provide, when contents of signals outputted from a device
under test is applied as a branch condition, a sequence control
circuit which allows to designate a plurality of branches according
to a combination of plural branch conditions.
[0025] The first object of the present invention is achieved by a
sequence control circuit which has a program counter and in which
circuit an address to be loaded to the program counter can be
switched depending on the result of detection made for combinations
of a plurality of branch conditions.
[0026] The second object of the present invention is achieved by a
sequence control circuit provided in a test pattern generator of a
memory test apparatus for performing a test of a semiconductor
memory device, the sequence control circuit comprising an
instruction memory for storing each of the instructions of the test
program, a plurality of branch address registers each for storing a
branch address, a logic operation circuit for receiving a plurality
of flags and detecting a combination of flag values, a program
counter for outputting an address to the instruction memory, a
program counter controller for controlling the program counter
according to a control word read from the instruction memory and
selecting one of the branch address registers corresponding to a
combination of the flag values, wherein the branch address stored
in the branch address register selected by the program counter
controller is loaded in the program counter.
[0027] In other words, in the sequence control circuit of the
present invention, according to the detection result of a
combination of a plurality of flags which represent branch
conditions, the address to be loaded into the program counter is
switched. Therefore, by employing the sequence control circuit in
the pattern generator of the memory test apparatus for performing
the semiconductor memory test, a complicated test pattern can
easily be produced through a relatively simple modification of the
circuit.
[0028] When a time-out occurs during block erasing operation in a
flash memory test, the flash memory has been considered defective
as it is in the test according to the conventional test pattern,
however, in this case, the memory is good and usable in the blocks
other than the block showing the time-out. Therefore, it is only
necessary to jump to any other block to continue the test without
merely discarding the useful memory as defective. According to the
sequence control circuit of the present invention, it is
particularly easy to generate the test pattern in these cases.
[0029] The above and other objects, features, and advantages of the
present invention will become apparent from the following
description based on the accompanying drawings which illustrate an
example of a preferred embodiment of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is a block diagram showing a structure of a memory
test apparatus of a common type;
[0031] FIG. 2 is a block diagram showing a structure of a
conventional sequence control circuit; and
[0032] FIG. 3 is a block diagram showing a structure of a sequence
control circuit of a preferable embodiment of the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0033] A sequence control circuit shown in FIG. 3 is used, in the
same manner as a conventional sequence control circuit shown in
FIG. 2, as the sequence control circuit 10 provided in the test
pattern generator 6 of memory test apparatus 1 as shown in FIG. 1.
However, the memory test apparatus in this embodiment is different
from that of FIG. 1, in that a plurality of flags are inputted in
the test pattern generator 6 from the logic comparator 8.
[0034] The sequence control circuit of the present embodiment shown
in FIG. 3 comprises: an instruction memory 21 for storing a test
program consisting of a series of instructions for generating a
test pattern; a program counter (PC) 22 for designating an address
of instruction memory 21; a stack register 23 for temporary saving
of addresses; a program counter controller 24 for controlling the
program counter 22 and the stack register 23; a starting address
register (STA) 25 for storing an initial value of the program
counter 22; a plurality of branch address registers (BARS) 26.sub.1
to 26.sub.n each for storing the address of the branch designated
by branch instructions; an index register 27; an index work
register 28; an index counter 29 and a logic operation circuit 30.
The logic operation circuit 30 receives a plurality of flags (two
flags FLG1, FLG2 are shown in the example illustrated) for decoding
these plurality of flags. A branch address can be set to each of
the branch address registers 26.sub.1 to 26.sub.n,
independently.
[0035] The instruction memory 21 has a same structure and same
function as those of the instruction memory 121 in the conventional
sequence control circuit shown in FIG. 2 and has a pair of sequence
control instruction areas for storing an operation code part and an
operand storing area for storing an operand.
[0036] The program counter controller 24 receives an operation code
part of sequence control instructions from the instruction memory
21, an output from the logic operation circuit 30 and an output of
the index counter 29. The program counter controller 24 controls
the program counter 22 and the stack register 23 based on the
result obtained by decoding the instructions stored in instruction
memory 21 and based on the outputs from the logic operation circuit
30 and the index counter 29. In the concrete, the program counter
controller 24 handles a content of the program counter 22, that is,
the value showing an address to be read next in the instruction
memory 21, through the increment, decrement or hold operation and
loads the value into the program counter 22. For loading the above
value to program counter 22, the program counter controller 24
arranges according to the instructions read out so that any one of
(i) an operand of the instruction for a present address of the
instruction memory 21, (ii) a content of the starting address
register 25, (iii) contents of the branch address registers
26.sub.1 to 26.sub.n, and (iv) a content of the stack register 23
is set to the program counter 22 as the value.
[0037] An address read from the operand storing area of the
instruction memory 21 is also supplied to the index register 27.
The index counter 29 controls loop instructions by using this index
register 27 and the index work register 28 which serves as a work
register, and when the counter value coincides with a specific
value, outputs the value to the program counter controller 24
thereby controlling the program counter 22.
[0038] As a result, when compared with the conventional sequence
control circuit shown in FIG. 2, the sequence control circuit shown
in FIG. 3 according to the present invention has a plurality of
branch address registers 26.sub.1 to 26.sub.n and the logic
operation circuit 30 for decoding a plurality of inputted flags.
Accordingly the sequence control circuit shown in FIG. 3 differs
from that shown in FIG. 2 in that output data of the logic
operation circuit 30 are input, instead of flags, directly to the
program counter controller 24.
[0039] In this sequence control circuit, a plurality of branch
address registers 26.sub.1 to 26.sub.n are provided and
combinations of respective values of a plurality of flags are
detected by the logic operation circuit 30. It is arranged such
that an address stored in a certain branch address register is to
be loaded to the program counter 22 according to the detected
combination of the flag values. Of course, in some case according
to a type of detected combination, an address in the branch address
register is not loaded, but instead, increment or decrement
operation is performed with reference to the current value of the
program counter 22. In other words, in this sequence control
circuit, it is arranged such that an address to be loaded to the
program counter 22 can be selected from a plurality of branch
addresses by using a plurality of flags.
[0040] Now, the present embodiment will be described in more detail
by comparing the operation of the conventional sequence control
circuit shown in FIG. 2, into which only one flag is inputted, with
the operation of the present embodiment.
[0041] In case of the conventional sequence control circuit shown
in FIG. 2, at most one branch address corresponds to the content of
one flag FLG1 (here, a match flag MFLG corresponds to flag FLG1).
In this case, the process in which the flag is detected and a
program counter value changes correspondingly is shown as follows.
Here, "(FLG1)" represents the value of flag FLG1, "PC" represents a
program counter, "(PC)" shows the present value of the program
counter, "m" shows a branch address stored in the branch address
register, ".fwdarw." represents load, that is, the value to the
left of this mark is stored in an item on the right side of this
mark.
If (FLG1)=0, then m.fwdarw.PC (1)
If (FLG1)=1, then (PC)+1.fwdarw.PC (2)
[0042] Equation (1) shows that if flag FLG1 value is "1", then an
branch address is loaded to the program counter, that is, a
conditional branch takes place, equation (2) shows that a value of
a program counter is handled by the increment operation, that is,
the program is executed without having any branch. Namely, in this
case, it can not finish a loop until the flag value reaches "1". By
arranging this flag detection branch instructions and index loop
instructions in a combination, it becomes possible to describe a
pattern in which, if a write termination flag is not detected after
a writing loop of predetermined cycles is completed in a flash
memory test, it will be judged as FAIL.
[0043] While, in case of the present embodiment, it is possible to
generate, for example, branches as follows corresponding to the
combination of values of two flags FLG1, FLG2. "(FLG2)" represents
the value of flag FLG2, and marks m, n, k show branch addresses set
in the respective different branch address register.
If (FLG1)=0 and (FLG2)=0, then m.fwdarw.PC (3)
If (FLG1)=1 and (FLG2)=0, then (PC)+1.fwdarw.PC (4)
If (FLG1)=0 and (FLG2)=1, then n.fwdarw.PC (5)
If (FLG1)=1 and (FLG2)=1, then k.fwdarw.PC (6)
[0044] In this way in case of the present embodiment, with
combination of two flags FLG1 and FLG2, there are three kinds of
branch addresses (equations (3), (5), (6)) which can be set, while
having one case of no branch address (equation (4)), thus realizing
designation of a plurality of branch addresses by using a plurality
of flags.
[0045] By using the sequence control circuit of the present
embodiment and by allocating flags, one flag showing execution or
termination of automatic algorithm and the other flag showing a
time-over, to the above two flags FLG1, FLG2, respectively, it
becomes possible to simply describe a test pattern with one
statement in the test program, the test pattern which allows to
change a branch according to the value of two flags, but so far a
complicated description has been required to prepare the test
pattern.
[0046] The present invention has been described above with an
example which uses two flags, however, the case with flags of three
or more can be realized in the same way as described above.
[0047] It is to be understood, however, that although the
characteristics and advantages of the present invention have been
set forth in the foregoing description, the disclosure is
illustrative only, and changes may be made in the arrangement of
the parts within the scope of the appended claims.
* * * * *