U.S. patent application number 09/961145 was filed with the patent office on 2002-03-28 for computer video output testing.
Invention is credited to Perez, Raphael.
Application Number | 20020036631 09/961145 |
Document ID | / |
Family ID | 8235546 |
Filed Date | 2002-03-28 |
United States Patent
Application |
20020036631 |
Kind Code |
A1 |
Perez, Raphael |
March 28, 2002 |
Computer video output testing
Abstract
A system is described for testing the video output of a computer
of the type in which a video output connector is provided with a
data channel, such as a DDC channel, permitting data to be
transmitted from a monitor connected to the video output connector
to the computer. The system comprises test apparatus having a
connector for connection to the video output connector of a
computer under test, the test apparatus comprising means to measure
parameters of test video signals received through the connector and
means to generate a result signal from the measured parameters for
transmission to the computer under test over the data channel.
Software executing on the computer under test to generate the test
video signals and to receive and process the result signal received
over the data channel.
Inventors: |
Perez, Raphael; (Grenoble,
FR) |
Correspondence
Address: |
HEWLETT-PACKARD COMPANY
Intellectual Property Administration
P.O. Box 272400
Fort Collins
CO
80527-2400
US
|
Family ID: |
8235546 |
Appl. No.: |
09/961145 |
Filed: |
September 21, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09961145 |
Sep 21, 2001 |
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09274917 |
Mar 23, 1999 |
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6323828 |
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Current U.S.
Class: |
345/204 ;
348/E17.005 |
Current CPC
Class: |
G09G 5/006 20130101;
G09G 2370/047 20130101; G09G 3/006 20130101; H04N 17/04
20130101 |
Class at
Publication: |
345/204 |
International
Class: |
G09G 005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 29, 1998 |
EP |
98402731.8 |
Claims
1. A system for testing the video output of a computer of the type
in which a video output connector is provided with a data channel
permitting data to be transmitted from a monitor connected to the
video output connector to the computer, the system comprising: test
apparatus having a connector for connection to the video output
connector of a computer under test, the test apparatus comprising
means to measure parameters of test video signals received through
the connector and means to generate a result signal from the
measured parameters for transmission to the computer under test
over the Display data channel; and software for execution on the
computer under test to generate the test video signals and to
receive and process the result signal received over the data
channel.
2. A system as claimed in claim 1 wherein the test apparatus is
arranged to derive power for its operational components from the
video output connector.
3. A system as claimed in claim 1 wherein the test apparatus has a
video output connector and an operating mode in which signals from
the connector are passed transparently to the video output
connector.
4. A system as claimed in claim 3 wherein the test appratus
comprises a switch for switching from a mode in which signals from
the connector are passed transparently to the video output
connector to a mode in which signals received from the connector
are processed within the test apparatus, the switch being
responsive to a signal received via the connector to switch between
the modes.
5. A system as claimed in claim 4 wherein the signal is a
predefined number of read commands being received by the test
apparatus within a predefined time.
6. A system as claimed in claim 1 wherein at least some of the
parameters measured are voltages.
7. A system as claimed in claim 1 wherein at least some of the
parameters measured are frequencies.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to video output testing,
particularly in personal computers.
BACKGROUND OF THE INVENTION
[0002] Generally personal computers must pass a number of
manufacturing tests after the system is built to ensure their
quality.
[0003] One aspect that must be tested is the video output. At
present, the video output is usually tested by having a human
engineer connect a monitor to the system unit and inspect by eye an
image generated by the system under test and displayed on the
monitor. The efficiency of this method is low and suffers from
being somewhat subjective in that each engineer has their own
judgement and vision. Thus the testing can be inconsistent and
inaccurate.
[0004] Various automatic systems have been proposed to try and
improve this situation, but these have certain drawbacks and are
not thought to have been widely adopted.
[0005] For instance U.S. Pat. No. 4,894,718 describes a video
signal testing system in which a cyclic redundancy check circuit is
connected to a expansion slot of the computer and the video output.
A value measured from a video signal is compared with a fixed value
to justify the correctness of the signals without the use of the
human eye. This system suffers from the disadvantage that since the
unit is connected to an expansion slot of the computer under test,
the test must either be carried out before the unit is fully
assembled, or the unit must be dismantled in order to effect the
test.
[0006] U.S. Pat. No. 5,537,145 discloses a system in which the
image displayed on the monitor is measured by an optical testing
unit and the result fed back to the system via an I/O subsystem. As
well as suffering from the disadvantages set out above of having to
connect to an expansion slot in the computer, this system also
suffers from an inability to distinguish between problems related
to the monitor itself and the circuitry within the computer under
test which generates the video signals.
[0007] This invention is directed to overcoming the problems of the
prior art by providing a simple and relatively cheap arrangement
for testing the video output of a computer.
SUMMARY OF THE INVENTION
[0008] In brief, this is achieved by a system for testing the video
output of a computer of the type in which a video output connector
includes a data channel permitting data to be transmitted from a
monitor connected to the video output connector to the computer,
the system comprising test apparatus having a connector for
connection to the video output connector of a computer under test;
the test apparatus comprising means to measure parameters of test
video signals received through the connector and means to generate
a result signal from the measured parameters for transmission to
the computer under test over the data channel; and software for
execution on the computer under test to generate the test video
signals and to receive and process the result signal received over
the data channel.
[0009] The invention makes use of the fact that the video output
connector of a modern computer is provided with a data display
channel. The VESA Display Data Channel (DDC) standards define a
communications channel between a computer display and a host
system. The channel is generally used to carry configuration
information to allow optimum use of the display and may also carry
display control information. In addition, it may be used as a data
channel for Access.bus peripherals connected to the host via the
display.
[0010] In at least a preferred implementation of the invention this
Display Data Channel is used as a means to feedback measured test
information from the video signal for processing by software
running on the system under test. Of course application of this
invention to other similar systems is not excluded. Only a very
simple piece of extra hardware is required which simply plugs into
the video output connector of a unit under test and does not
require any additional connection to the computer. The tests can
therefore be carried out on the final assembled computer
product.
[0011] In a preferred embodiment, the test apparatus is arranged to
derive power for its operational components from the video output
connector, thereby obviating the need for separate power
supply.
[0012] The test apparatus can have a video output connector and an
operating mode in which signals from the connector are passed
transparently to the video output connector. This enables a monitor
to be connected to the unit which can be useful in monitoring the
test process.
[0013] A switch can be provided for switching from a mode in which
signals from the connector are passed transparently to the video
output connector to a mode in which signals received from the
connector are processed within the test apparatus, the switch being
responsive to a signal received via the connector to switch between
the modes. In the preferred embodiment, this signal is a predefined
number of EDID read commands being received by the test apparatus
within a predefined time.
[0014] The relatively low cost of the unit has the consequence that
many of the units is use simultaneously at a plurality of final
assembly stations as are typically used in modern personal computer
final assembly. Units can also be used for off-site maintenance and
testing of units in the field.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] A system embodying the invention will now be described, by
way of non-limiting example, with reference to the accompanying
diagrammatic drawings, in which:
[0016] FIG. 1 shows a system for testing the video output of a
computer;
[0017] FIG. 2 is a schematic diagram showing the test unit of the
system of FIG. 1.
[0018] FIG. 3 is a timing diagram showing the operation of the test
unit of the system of FIG. 1.
BEST MODE OF CARRYING OUT THE INVENTION
[0019] FIG. 1 shows a system for testing the video output of a
personal computer having a standard VGA video output. As shown in
FIG. 1, a test unit 100 is connected to the VGA output connector of
a personal computer system unit 110 under test, hereinafter
referred as the unit under test (UUT). As will be described in more
detail below, test unit 100 measures voltage and timing parameters
of test video signals generated by software executing on UUT 110
and received through the VGA connector and generates a result
signal from the measured parameters. The result signal is
transmitted to UUT 110 over the DDC (Display data channel) within
the VGA connector. Suitable software executing on UUT 110 receives,
processes and stores the result signals received over the DDC data
channel.
[0020] In a preferred embodiment, test unit 110 itself has a VGA
output to which display monitor 120 is connected, although this is
not essential. Also in the preferred embodiment, the whole process
can be carried out as part of a larger test sequence which is
supervised by a test controller 130. Another way is to use the test
unit in a stand-alone process (ie without test controller 130). In
this case UUT can send the test result itself to a printer or its
monitor or any other external device.
[0021] FIG. 2 is a schematic diagram showing the functional
elements of test unit 100 and UUT 110. Dashed line 200 represents
the standard VGA connection between UUT 110 and the test unit 100.
The standard VGA connection between test unit 100 and display
monitor 120 is represented at 210. Test unit 100 comprises a switch
220 that functions to pass the VGA signals received by test unit
100 either directly to display monitor 120 or for analysis by the
test unit. When test unit 100 is not enabled the VGA signals are
passed in a transparent manner to VGA output 210 to enable monitor
120 to operate normally.
[0022] Selector/multiplexor 230 selects the VGA lines (when so
switched by switch 220) for test and includes an analog to digital
converter for measuring the analog colour signals.
[0023] The measurements are analysed and temporarily stored in
analyser block 240. Analyser block 240 includes a suitably arranged
microprocessor with associated ROM and RAM memory as well as other
logic--in this embodiment implemented by a Field Programmable Gate
array (FPGA).
[0024] Output block 250 arranges the results in EDID data block so
that they are available to UUT 110 via DDC data channel 260.
[0025] Test unit 100 also includes output LEDs 255 to indicate
status to an operator and a power supply supervisor unit 290 which
takes power for the unit from the +5V line in the VGA connector,
thereby obviating the need for a separate power supply within the
unit.
[0026] In FIG. 2 the function of the test software that runs on UUT
110 is represented at 270. There are five main functions:
[0027] 1. The generation to the video signals to be tested,
including configuration of conventional display parameters such as
video resolution, number of colours, refresh rate and luminance
level;
[0028] 2. The establishment of the communication protocol between
test unit 100 and UUT 110 and
[0029] 3. The processing of the results received from test unit
100;
[0030] 4. The management of the I2C protocol used by the DDC;
[0031] 5. Devalidation of test unit 100.
[0032] The basic test process is as follows. An operator plugs the
test unit 100 in the VGA output of UUT 110 and powers on UUT
110.
[0033] The software running on UUT 110 then generates a test
pattern which is displayed on display monitor 120. In response to a
predefined signal received from UUT 110 and detected within switch
220 of test unit 100, the switch then shuts off the VGA signals to
display monitor 120 and launches a series of measurements of the
video signal received through the unit under test. The measurements
are downloaded from test unit 100 as they are completed. Each
measurement is checked against predefined tolerances for the
parameter concerned by the software running on UUT 110 and the
result (PASS or FAIL) is transmitted to test controller 130 in the
form of a DOS error. A report file is stored on UUT 110 for
subsequent fault diagnosis if required.
[0034] This general process is shown in the timing diagram of FIG.
3. In the preferred embodiment, the signal which is used to launch
the test process is the receipt of 10 closely spaced EDID read
signals within a predefined time period t1. These signals are shown
at 300. Upon detection of this signal, switch 220 switches to
direct the VGA signals to selector/multiplexor 230. This transition
is indicated at 310.
[0035] Each separate measurement is initiated by a further read
EDID signal sent by the UUT 110--these signals are indicated at
320. The results of the measurements are retrieved by interleaved
read EDID signals indicated at 330. Once all the measurements are
complete, switch 220 redirects the VGA signals back to monitor
120.
[0036] As is well known, the VGA video output comprises 5 signals:
three analog colour signals (red, green, blue) and two
synchronisation signals. In addition there is a +5V power line. The
luminance of the screen is directly proportional to the amplitude
of the RGB signals. The synchronisation signals guarantee the
stability and the form of the image.
[0037] The DDC bus is a bus based on the well-known I2C protocol
and comprises two signal lines denoted SDA which carries DDC data
and SCL which carries a clock signal.
[0038] The analog RGB signals have voltages within the range OV to
0.7V, 0.7V corresponding to the maximum intensity. The Vsynch and
Hsynch signals are TTL signals whose frequency can vary between 60
Hz and 100 Hz according to the video card within the PC.
[0039] The measurements performed by test unit 100 are as
follows:
[0040] Red, Green, Blue signals--Test unit 100 makes the range
measurement in the useful part of video line between the beginning
and the end of the video line. Range measurements are performed for
a cluster of 128 lines from the beginning of the field. The test
pattern and the synchronization of the measurements and the
generation of the test pattern are arranged so as to enable each
discrete voltage level of the RGB signals to be measured and
recorded.
[0041] I2C/SDA signal--This signal, the data line of the I2C/DDC
bus, is "or wired" and TTL level. For this signal the low level and
high level voltages are measured by the test unit 100 when SDA
signal is driven by UUT 110. Test unit 100 performs only one
measurement per test sequence.
[0042] Signal I2C/SCL--This signal, the clock of I2C/DDC bus, is
TTL level and driven by the UUT. Low level and high level voltages
are measured when the SCL signal is driven by the UUT. Only one
measurement is performed per test sequence.
[0043] Signal I2C/+5V--This is the DC power source delivered by the
UUT to test unit 100. Test unit 100 performs only one measure of
level voltage per test sequence. If the voltage is under 4.7V, no
measurement can be performed because the test unit 100 will be in
RESET state and not running.
[0044] Signal Vsync--This signal, the video frame vertical
synchronization, is TTL level and driven by UUT. Low level and high
level voltages are measured by the test unit 100. Only one
measurement is performed per test sequence. This signal can have
positive or negative logic level depending on the video format. A
time measurement is performed between two consecutive falling edges
of the VSync signal.
[0045] Signal Hsync--This signal, video frame horizontal
synchronization, is TTL level and driven by UUT 110. Low level and
high level voltages are measured by the test unit 100 and only one
measurement is performed per test sequence. The scale of the result
is mV. This signal can have positive or negative logic level
depending on the video format. The cycle time is also measured
between two consecutive falling edges of the Hsync signal. To have
an accurate cycle time, test unit 100 measures 128 consecutive
Hsync cycles.
[0046] LEDs 255 indicate the power and testing states as
follows:
[0047] A Red LED indicates power as follows:
1 switched off +5V power from VGA IN is off; switched on +5V power
from VGA IN is on;
[0048] A Yellow LED only works if the Red LED is on and indicates
the state of test unit 100 as follows:
2 switched off test unit 100 is waiting because +5V power < 4.7
V or autotest fault; switched on test unit 100 is running but not
enabled fast flashed on test unit 100 is running and enabled -
testing is in progress
[0049] The data stream from test unit 100 to UUT 110 uses the
Extended Data Information Display (EDID) block of the DCC protocol.
This stream contains each measured parameter as shown below
3 Data Address Format Unit mnemonic Data description 0 Char 0x00
Header 1 to 6 Char 0xFF Header 0 Char 0x00 Header 8 unsigned
ID_PRODUCT Identifier of test short unit 100 0x4EC8 10 unsigned
SERIAL_NB Serial number of test short unit 100 12 unsigned VERSION
data stream Version- short Revision 14 unsigned mV HS_LOW_V
Horizontal short Synchronization Low level Voltage 16 unsigned mV
HS_HIGH_V Horizontal short Synchronization High level Voltage 18
unsigned mV VS_LOW_V Vertical short Synchronization Low level
Voltage 20 unsigned mV VS_HIGH_V Vertical short Synchronization
High level Voltage 22 unsigned mV SDA_LOW_V Data DDC/I2C signal
short Low level Voltage 24 unsigned mV SDA_HIGH_V Data DDC/I2C
signal short High level Voltage 26 unsigned mV SCL_LOW_V Clock
DDC/I2C signal short Low level Voltage 28 unsigned mV SCL_HIGH_V
Clock DDC/I2C signal short High level Voltage 30 unsigned mV VCC_V
VCC power supply short Voltage 32 unsigned .mu.s VS_P Vertical
short Synchronization period 34 unsigned ns HS_P Horizontal short
Synchronization period (total for 128 line) 36 boolean VS_HS_POL
Bit 1 -> Vertical Synchronization Polarity Bit 2 ->
Horizontal Synchronization Polarity Polarity : 0 = NEG, 1 = POS 40
BLOCK 0 beginning of block0 40 unsigned mV RED_LEVEL Red level
voltage short 42 unsigned mV GREEN_LEVEL Green level voltage short
44 unsigned mV BLUE_LEVEL Blue level voltage short 46-51 BLOCK 1 as
block0 52-57 BLOCK 2 as block0 58-63 BLOCK 3 as block0 64-69 BLOCK
4 as block0 70-75 BLOCK 5 as block0 76-81 BLOCK 6 as block0 82-87
BLOCK 7 as block0 88-93 BLOCK 8 as block0 94-99 BLOCK 9 as block0
127 CHECKSUM
[0050] The operations the data analysis part of the program is as
follows:
[0051] Configuration values are read from a configuration file
svh.ini.
[0052] Measured parameters are read from the block EDID.
[0053] Each measured parameter is compared with the configuration
values.
[0054] The results are written in a report.
[0055] a DOS error code is returned.
[0056] The svh.ini file contains the maximum and the minimum value
for each parameter in a suitable format as well a flag which can be
set to indicate that that parameter should or should not be
tested.
[0057] It will be appreciated that many variations are possible
within the scope of the attached claims. For example, test unit 100
may be integrated as part of the monitor or within a personal
computer to provide a self-test functionality. Many variations of
the parameters measured are possible and these may be analysed in
different ways.
* * * * *