U.S. patent application number 09/319898 was filed with the patent office on 2002-03-28 for ic testing method and ic testing device using the same.
Invention is credited to HASHIMOTO, YOSHIHIRO.
Application Number | 20020036513 09/319898 |
Document ID | / |
Family ID | 27179153 |
Filed Date | 2002-03-28 |
United States Patent
Application |
20020036513 |
Kind Code |
A1 |
HASHIMOTO, YOSHIHIRO |
March 28, 2002 |
IC TESTING METHOD AND IC TESTING DEVICE USING THE SAME
Abstract
In an IC testing apparatus which executes a function test and a
d.c. test, a resistor having a high resistance is connected to the
output side of a d.c. tester such that the connection of the
resistor allows a function test to operate normally if the d.c.
tester is left connected to the function tester, thus allowing the
d.c. test to be interrupted into the execution of the function test
to enable a concurrent execution of the function test and the d.c.
test, whereby a control which takes time such as changing switches
in the d.c. tester is executed during the function test, thus
preventing the changing time interval of the switches from being
added to a time interval required for the test to thereby reduce
the testing time interval.
Inventors: |
HASHIMOTO, YOSHIHIRO;
(URAWA-SHI, JP) |
Correspondence
Address: |
GALLAGHER & LATHROP
601 CALIFORNIA ST
SUITE 1111
SAN FRANCISCO
CA
94108
US
|
Family ID: |
27179153 |
Appl. No.: |
09/319898 |
Filed: |
June 14, 1999 |
PCT Filed: |
November 20, 1997 |
PCT NO: |
PCT/JP97/04228 |
Current U.S.
Class: |
324/750.01 |
Current CPC
Class: |
G01R 31/31917 20130101;
G01R 31/3004 20130101 |
Class at
Publication: |
324/765 |
International
Class: |
G01R 031/26 |
Claims
What is claimed is:
1. In an IC testing apparatus comprising a function tester for
performing a function test of an IC under test by applying a test
pattern signal to each terminal of the IC under test from a driver,
a status of an output terminal of which can be set in a high
impedance mode, and a d.c. tester for measuring a current passing
through each terminal of the IC under test under a condition that a
given voltage is applied to each terminal on the IC under test; an
IC testing method comprising connecting a sensing point of the d.c.
tester to a terminal of the IC under test through a resistor during
an execution of the function test of the IC under test by the
function tester, controlling the driver of the function tester to
be in a high impedance mode under the condition that an output
voltage from the d.c. tester is set up at a given voltage,
measuring a leak current passing through a terminal of the IC under
test by the d.c. tester, thus executing the measurement of the leak
current as one d.c. test item during the execution of the function
test.
2. An IC testing apparatus comprising A. a function tester for
executing a function test of an IC under test by applying a test
pattern signal to each terminal on the IC under test from a driver,
a status at an output terminal of which can be set up in a high
impedance mode; B. a d.c. tester for measuring a leak current
passing through each terminal of the IC under test under a
condition that a given voltage is applied to each terminal of the
IC under test; C. a resistor connected between a sensing point of
the d.c. tester and a terminal on the IC under test; D. first
control means for causing a given voltage to be delivered to the
sensing point on the d.c. tester during the execution of the
function test by the function tester; E. second control means for
controlling the output terminal of the driver of the function
tester to its high impedance condition at the time when the control
operation by the first control means is completed; and F. current
measuring means for causing the d.c. tester to execute an operation
of measuring a leak current passing through a terminal of the IC
under test under the condition that the output terminal of the
driver is controlled to its high impedance mode.
3. An IC testing apparatus according to claim 2 in which the d.c.
tester comprises an operational amplifier having a non-inverting
input terminal, to which a given voltage is applied, and delivering
an output voltage at its output terminal, the output voltage being
delivered to a sensing point through a current detecting resistor,
with the voltage at the sensing point being fed back to an
inverting input terminal, and current measuring means for measuring
a voltage developed across the current detecting resistor to
measure the value of a leak current passing through a terminal on
the IC under test, the sensing point being connected to a terminal
on the IC under test through a resistor.
4. An IC testing apparatus according to claim 2 in which the d.c.
tester comprises an operational amplifier having a non-inverting
input terminal and an inverting input terminal, a current detecting
resistor having one end connected to the output terminal of the
operational amplifier and the other end connected to a current
output terminal, a first switch for applying a voltage delivered at
the current output terminal to a voltage detecting terminal, a
protective resistor connected between the current output terminal
and the voltage detecting terminal, a feedback circuit for feeding
the voltage at the voltage detecting terminal back to the inverting
input terminal of the operational amplifier, a series circuit
including a second switch and a resistor for applying a voltage at
the voltage detecting terminal to a terminal on the IC under test
through a sensing point, a third switch connected between the
current output terminal and the sensing point, and a current
measuring means for measuring a voltage developed across the
current detecting resistor to measure a current passing through a
terminal on the IC under test, in a mode during the functional test
in which the leak current passing through a terminal on the IC
under test is measured, the first switch and the second switch
being turned on so that an impedance of the d.c. tester as viewed
from the function tester appears to be a high impedance due to the
resistor, while in a d.c. test mode during which a non-function
test takes place, the first switch is turned off, and the second
switch and the third switch are turned on, the current output
terminal being directly connected to the sensing point and to a
terminal on the IC under test.
Description
[0001] 1. Technical Field
[0002] The present invention relates to an IC testing method which
enables a function test and a leak test for entries of a d.c. test
to be performed in a brief time interval when conducting a function
test and a d.c. test for a semiconductor device such as a memory
formed by a semiconductor integrated circuit, and to an IC testing
apparatus which employs the method.
[0003] 2. Background Art
[0004] Heretofore, an IC testing apparatus which tests a
semiconductor device such as a memory performs a function test
which determines whether or not the function of the semiconductor
device is normally operating and a d.c. test which determines
whether or not respective terminals of the semiconductor device
exhibit predetermined d.c. characteristics, and determines an IC
which proved to be normal in the both tests to be an acceptable
product.
[0005] FIG. 3 shows a schematic arrangement of an IC testing
apparatus. In this Figure, character TES designates the entire IC
testing apparatus. The IC testing apparatus TES is internally
categorized into a main controller MAIN, a function tester 100 and
a d.c. tester 200.
[0006] The main controller MAIN comprises a computer system, and
controls the function tester 100 and the d.c. tester 200 through a
bus line BUS. The function tester 100 comprises a pattern generator
102, a timing generator 104 and function test units 106A, 106B , .
. . ,106N.
[0007] The function test units 106A-106N are associated with
respective terminals of an IC under test 300 so that switches
S.sub.11-S.sub.1ncan be turned on and off to have the function test
units 106A-106N connected with or disconnected from the respective
terminals of the IC under test 300.
[0008] Thus the function test takes place by controlling the
switches S.sub.11-S.sub.1n to their on conditions to have the
function test units 106A-106N connected to the respective terminals
of the IC under test 300 for applying test pattern signals to the
respective terminals of the IC under test 300 to carry out the
function test.
[0009] On the other hand, one or more of the d.c. tester 200 is
provided for the terminals of the IC under test 300 (in the example
shown in FIG. 3, the provision of the single d.c. tester 200 is
shown), and is arranged such that change-over switches
S.sub.21-S.sub.2n are sequentially controlled to be on one at each
time to have the d.c. tester 200 connected to sequential one of the
terminals on the IC under test 300, thus sequentially testing the
d.c. characteristic of the specific terminals. Incidentally, 400
designates a controller which controls these switches
S.sub.11-S.sub.1n and S.sub.21-S.sub.2n.
[0010] FIG. 4 shows an internal arrangement of one of the function
test units, 106A, and the summary of the function test will be
described. The function test unit 106A (the remaining function test
units are similarly arranged) comprises a waveform formatter 11, a
driver 12, a voltage comparator 13, a logical comparator 14 and a
fault analysis memory 15.
[0011] The waveform formatter 11 receives test pattern data applied
from the pattern generator 102 and produces a test pattern signal
having an actual waveform. The timing generator 104 supplies a
timing signal which defines the rise timing and the fall timing of
the test pattern signal to the waveform formatter 11.
[0012] The test pattern signal delivered from the waveform
formatter 11 is shaped by the driver 12 into a waveform of an
amplitude having a given logical value, which is fed through the
switch S.sub.11 to a given terminal on the IC under test 300 to
store data in the IC under test 300. If this terminal is an I/O
terminal (a combined input and output terminal), each terminal on
the IC under test 300 is controlled into an input mode when
inputting the test pattern signal, and is switched to an output
mode at the time when a write operation is completed. Content
stored in the IC under test 300 is read out at the timing of
switching into the output mode, and is fed through the voltage
comparator 13 to the logical comparator 14. Incidentally, when the
voltage comparator 13 reads data delivered from the IC under test
300, the output terminal of the driver 12 is set up in its high
impedance mode.
[0013] The voltage comparator 13 determines by comparison whether
the logic of the signal read out from the IC under test 300
maintains a normal voltage value. Thus, it is determined whether or
not L logic and H logic satisfies, for example, 0.8 volt or lower
and 2.4 volt or higher, respectively, and for a signal having a
voltage of a normal logic value, such logic value is input to the
logical comparator 14.
[0014] An expected value is input to the logical comparator 14 from
the pattern generator 102, and is compared against the logic value
which is input from the voltage camparator 13, thus detecting the
occurrence of any non-coincidence. In the event a non-coincidence
occurs, it is assumed that there exists a fault in a memory cell at
an address where a write-in took place, the fault is stored in the
fault analysis memory 15 at this address, and subsequent to the
completion of the test, the number of faulty cells is counted by
reading out the fault analysis memory 15 to determine whether or
not a salvaging is possible.
[0015] FIG. 5 shows an example of the arrangement of the d.c.
tester 200. The arrangement shown is one which is used when the
d.c. tester 200 operates in a voltage applied current measuring
mode. Applied to a non-inverting input terminal of an operational
amplifier 16 is a voltage V.sub.L or V.sub.H having a logic value
which is to be applied to a terminal on the IC under test 300 from
a DA converter 17.
[0016] A current detecting resistor R1 is connected between the
output terminal of the operational amplifier 16 and a current
output terminal T.sub.I, a switch S.sub.a2 is connected between the
current output terminal T.sub.I and a sensing point SEN, a
protective resistor R3 is connected between the current output
terminal T.sub.I and a voltage detecting terminal T.sub.V, and the
voltage detecting terminal T.sub.V is connected to the sensing
point SEN through a switch S.sub.a1. The sensing point SEN is
connected through a change-over switch S.sub.21 to a terminal on
the IC under test 300. An inverting input terminal of the
operational amplifier 16 is connected to the voltage detecting
terminal T.sub.V.
[0017] Incidentally, a switch Sb connected in shunt with the
current detecting resistor R1 represents a range change-over switch
which changes the current measuring range. By controlling the
switch S.sub.b on, a resistor R2 of a smaller resistance or
allowing a measurement of a high current (a current in the output
mode of the IC under test 300) is connected in circuit, thus
changing over to a high current measuring range.
[0018] With this arrangement of the d.c. tester 200, the voltage
V.sub.L or V.sub.H applied to the non-inverting input terminal of
the operational amplifier 16 from the DA converter 17 is applied to
a terminal on the IC under test 300 by controlling the switches
S.sub.a1,S.sub.a2 and the change-over switch S.sub.21 to on
conditions.
[0019] Specifically, since the operational amplifier 16 operates to
make voltages at the non-inverting and the inverting input terminal
equal to each other, if V.sub.L, for example, is applied to the
non-inverting input terminal of the operational amplifier 16, the
output voltage is controlled so that the voltage at the inverting
input terminal (equal to the voltage at the voltage detecting
terminal T.sub.V) also assumes V.sub.L. Accordingly, the voltage
V.sub.L or V.sub.H is applied to a terminal on the IC under test
300.
[0020] In the d.c. test mode, each terminal P.sub.i of the IC under
test 300 is set up in its input mode shown in FIG. 6. By measuring
a current which passes through the current detecting resistor R1
under the condition that V.sub.L(a voltage providing an L logic) or
V.sub.H(a voltage providing an H logic) is applied to the terminal
P.sub.i, respective leak currents I.sub.Rek1 and I.sub.Rek2 of
active elements Q.sub.1 and Q.sub.2 connected to the terminal
P.sub.i can be measured. 18 represents a subtractor circuit which
derives a voltage developed across the current detecting resistor
R1, and 19 represents an AD converter which applies an AD
conversion to the voltage obtained by the subtraction circuit 8 to
deliver a digital value.
[0021] When measuring the leak currents I.sub.Rek1, I.sub.Rek2
mentioned above, the change-over switch S.sub.b is turned off, thus
measuring a voltage developed across the current detecting resistor
R1 having a relatively high resistance on the order of 100 k.OMEGA.
and measuring the leak currents I.sub.Rek1 and I.sub.Rek2 passing
through each input terminal of the IC under test 300. Incidentally,
the protective resistor R3 is formed by a resistor having a
relatively small resistance (on the order of several 10's .OMEGA.),
thus securing a closed feedback loop to the inverting input
terminal of the operational amplifier 16 if the switches S.sub.a1
and S.sub.a2 are simultaneously controlled to be off during the
actual operation, the resistor thus protecting the operational
amplifier 16 so that an operation which causes the operational
amplifier 16 to saturate cannot occur.
[0022] From the foregoing, the summary of the function test and the
d.c. test in the IC testing apparatus could have been understood.
It is to be noted that heretofore, the function test and the d.c.
test mentioned above have been performed at totally different
timings, that is to say, after one of the tests is performed, the
other test is performed. In particular, in the d.c. test, it is
necessary to provide a control which changes the change-over
switches S.sub.21, S.sub.22 . . . S.sub.2n and a control which
changes the switches S.sub.11-S.sub.1n shown in FIG. 3. This manner
will be described with reference to FIG. 7.
[0023] When performing the function test, the function test is
performed under the condition that the switches S.sub.a1, S.sub.a2
and the change-over switches S.sub.21-S.sub.2n shown in FIG. 3 are
all changed to off conditions to disconnect the d.c. tester 200
from the terminals on the IC under test 300 while the switches
S.sub.11-S.sub.1n are all controlled to on conditions. Thus,
because the output impedance of the d.c. tester 200 is relatively
low on the order of several .OMEGA.'s, if the d.c. tester 200 is
electrically connected as a load on the function tester 100 during
the function test, an inconvenience is caused that the waveform of
a test pattern signal which is fed from the function tester 100 to
the IC under test 300 is degraded, preventing the function test
from being performed in a normal manner.
[0024] For this reason, the function test is performed by
controlling all of the change-over switches S.sub.21-S.sub.2n and
the switches S.sub.a1, S.sub.a2 to off conditions or controlling so
that the d.c. tester 200 is not connected to any terminal on the IC
under test 300.
[0025] On the other hand, when performing the d.c. test, switches
S.sub.11-S.sub.1n are all initially controlled to on conditions,
connecting the function test units 106A-106N to all the terminals
on the IC under test 300. Under this condition, an initializing
pattern for conducting the d.c. test is applied to the IC under
test 300.
[0026] Specifically, if a terminal which is subject to the d.c.
test is an I/O terminal, an initializing pattern (see FIG. 7C)
which sets up an input mode as the mode for the terminal is input
from the function tester 100. After the input mode is set up at the
terminal which is subject to the d.c. test, that terminal exercises
a control which disconnects the function test units 106A-106N from
all the terminals on the IC under test 300.
[0027] Under this condition, the change-over switch S.sub.21, is
controlled to be on for performing the d.c. test. The d.c. test
measures the leak currents I.sub.Rek1 and I.sub.Rek2 (see FIG. 6)
passing through the terminal under the condition that respective
logic values of either H logic or L logic are applied to the
terminals on the IC under test 300. If the leak current values are
equal to or less than values which are previously predetermined,
acceptability is determined, while if they are equal to or greater
than the values, fault is determined.
[0028] In this manner, the d.c. test is performed for each
terminal, and hence there is required, for each terminal tested, a
sum interval of T.sub.pi (see FIG. 7D) of an interval T.sub.SW1
during which the switches S.sub.11-S.sub.1n are controlled on and
off in order to apply the initializing pattern and an interval
T.sub.SW2 during which the change-over switches S.sub.21-S.sub.2a
are controlled in a switching manner. The interval T.sub.SW1 for
applying the initializing pattern and the interval T.sub.SW2 for
switchingly controlling the change-over switches S.sub.21-S.sub.2n
correspond to a time interval (several ms) for changing the
switches (relays), and if the interval T.sub.IM (FIG. 7E) for
measuring the current is short, the added interval T.sub.pi is
relatively long. Accordingly, if a switching control of the
switches S.sub.11-S.sub.1n and the change-over switches
S.sub.21-S.sub.2n is executed for every terminal, there results an
inconvenience that the d.c. test requires an increased length of
time. This stands in the way to the testing of quantities of
IC's.
[0029] It is an object of the invention to propose an IC testing
method capable of testing quantities of IC's in a brief interval by
reducing the testing interval of an IC, and an IC testing apparatus
which utilizes the testing method.
DISCLOSURE OF THE INVENTION
[0030] The invention is characterized by an arrangement which
allows the d.c. tester to be maintained connected to a terminal on
an IC under test even during the function test, which is enabled by
connecting d.c. tester to a terminal on the IC under test through a
resistor, the sophistication being such that the connection of the
resistor prevents the d.c. tester from presenting a significant
load as viewed from the function tester.
[0031] With this arrangement, there is proposed an IC testing
method which permits the d.c. test to be executed by controlling
the output terminal of a driver of the function tester in a high
impedance mode even during the function test, thus dispensing with
the need for a switch control to disconnect the function tester
during the time the d.c. test is being executed and thus allowing
an execution of a leak test among a d.c. test item during the
interval for the functions test.
[0032] Thus, with the IC testing method according to the invention,
the leak test for a d.c. test item is completed at the same time
with the end of the function test, thus eliminating the need for a
special time interval to conduct the leak test. Consequently, there
is obtained an advantage that the length of time required for the
test can be significantly reduced.
[0033] In addition, the present invention proposes an IC testing
apparatus which utilizes the IC testing method mentioned above.
[0034] An IC testing apparatus according to the invention comprises
a function tester for executing the function test of an IC under
test by applying a test pattern signal to each terminal on the IC
under test from a driver which is capable of setting up a status of
an output terminal thereof in a high impedance mode;
[0035] a d.c. tester for measuring a leak current passing through
each terminal on an IC under test under a condition that a given
voltage is applied to each terminal on the IC under test;
[0036] a resistor connected between the sensing point of the d.c.
tester and the terminal on the IC under test;
[0037] first control means for causing a given voltage to be
delivered to the sensing point of the d.c. tester during the
execution of the function test by the function tester;
[0038] second control means for controlling the output terminal of
the driver of the function tester in a high impedance mode at the
time a control operation by the first control means is
completed;
[0039] and current measuring means for measuring a leak current
passing through a terminal of the IC under test under a condition
that the output terminal of the driver is controlled in a high
impedance mode.
[0040] With the IC testing apparatus according to the invention,
there is no need to disconnect the function tester and the d.c.
tester from each other not only during the execution of the
function test, but also during the execution of d.c. test.
Accordingly, the d.c. test can be executed during the execution of
the function test without a need for the time to change the
switch.
[0041] As a consequence, if the d.c. test is executed during the
execution of the function test, the d.c. test is dispersed in a
compound form in the function test, and there is obtained an
advantage that a length of time for the compounded test cannot be
significantly longer than the length of time required for the
inherent function test, thus allowing the function test and a leak
test to be completed within a brief interval.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] FIG. 1 is a block diagram of one embodiment of an IC testing
apparatus which adopts an IC testing method according to the
invention;
[0043] FIG. 2 shows timing charts illustrating the IC testing
method according to the invention;
[0044] FIG. 3 is a block diagram schematically illustrating a
conventional IC testing apparatus;
[0045] FIG. 4 is a block diagram showing an arrangement of a
function tester used in the IC testing apparatus shown in FIG.
3;
[0046] FIG. 5 is a circuit diagram illustrating the arrangement of
a d.c. tester used in the IC testing apparatus shown in FIG. 3;
[0047] FIG. 6 is a circuit diagram illustrating a situation of a
terminal on the IC under test when executing a leak test for d.c.
test item;
[0048] FIG. 7 shows timing charts illustrating the manner of a
conventional d.c. test.
BEST MODE OF CARRYING OUT THE INVENTION
[0049] For a more detailed description of the invention, it will be
described with reference to the attached drawings.
[0050] FIG. 1 shows an embodiment of an IC testing apparatus which
tests an IC under test 300 according to an IC testing method which
is proposed by the present invention. In this Figure, 100
represents a function tester and 200 a d.c. tester, generally in
the similar manner as described above in connection with FIG. 3.
When conducting a function test, all of switches S.sub.11-S.sub.1n
are controlled to be on, thus connecting all the function testing
units 106A-106N to the respective terminals of IC under test 300
for purpose of execution.
[0051] The d.c. tester 200 sequentially controls one of the
change-over switches S.sub.21-S.sub.2n to be on, selectively
connecting the d.c. tester 200 to each terminal of the IC under
test 300 to conduct a d.c. test of each terminal alone.
Incidentally, although a plurality of d.c. testers 200 are provided
in actuality to provide an arrangement in which the d.c. test can
be completed within a brief interval by reducing the number of
terminals undertaken by each tester, the present description
assumes that the d.c. tester 200 is implemented as a single d.c.
tester 200.
[0052] The IC testing apparatus according to the invention is
characterized in that in the d.c. tester 200, a resistor R4 is
connected in series with a switch S.sub.2 between the voltage
detecting terminal T.sub.V and the sensing point SEN.
[0053] Specifically, in the d.c. tester 200, a protective resistor
R3 connected between a current output terminal T.sub.I and a
voltage detecting terminal T.sub.V is shunted by a first switch S1,
while the second switch S2 and the resistor R4 are connected in
series with the voltage detecting terminal T.sub.V and sensing
point SEN. In addition, a third switch S.sub.3 is connected between
the current output terminal T.sub.I, and the sensing point SEN.
[0054] When executing the function test, the first switch S1 and
the second switch S2 are turned on while the third switch S3 is
turned off. Under this condition, the resistor R4 is connected in
series between the sensing point SEN and the current output
terminal T.sub.I and the voltage detecting terminal T.sub.V.
Accordingly, an impedance of the d.c. tester 200 as viewed from the
function test unit which is connected to the d.c. tester 200 can be
regarded as the resistance of the resistor R4. By choosing a
resistance of the resistor R4 to be about 10 k.OMEGA., the
impedance of the d.c. tester 200 as viewed from the function test
units 106A-106N can be regarded as about 10 k.OMEGA..
[0055] A signal transmission line which connects between each of
the function test units 106A-106N and an IC under test 300 is
generally matched to a characteristic impedance of 50 .OMEGA..
Accordingly, if a load of 10 k.OMEGA. (d.c. tester 200) were
connected to each output of the function test units 106A-106N,
there can be no significant variation in the line impedance, and
the waveform of a test pattern signal which is fed from the
function testing units 106A-106N to the IC under test 300 cannot be
disturbed by the connection of the d.c. tester 200. In other words,
if the d.c. tester 200 is maintained connected to somewhere on the
IC under test 300 during the function test, the waveform of a test
pattern signal applied to the terminal which is connected to the
d.c. tester 200 cannot be disturbed, allowing the function test to
be normally executed.
[0056] It will be understood from the foregoing description that
the function test can be executed while maintaining the d.c. tester
200 connected to the function test units.
[0057] In addition, the present invention proposes a method of
executing a d.c. test (leak test) during the execution of the
function test while maintaining the function test units 106A-106N
connected to the respective terminals on the IC under test 300.
[0058] Thus, there is proposed a method of measuring a leak current
which passes through a terminal on the IC under test 300 without
controlling the switches S.sub.11-S.sub.1n to be off. The method
comprises controlling an output status of a driver 12 of the
function test unit connected to the terminal, the leak current
through which is to be measured by the d.c. tester 200, in a high
impedance mode at the timing a given voltage (a voltage providing
an H logic or L logic) is applied to such terminal and measuring a
leak current passing through the terminal on the IC under test 300
by means of d.c. tester under the condition that the driver 12 is
controlled to be in its high impedance mode.
[0059] At this end, during the execution of the function test, a
main controller MAIN provides a command signal which causes the
d.c. tester 200 to produce a given voltage (either H logic or H
logic). Specifically, it applies a digital value for producing a
given voltage to a DA converter 17. The DA converter 17 effects a
DA conversion of the digital value to deliver a voltage V.sub.L or
V.sub.H, which is applied to a non-inverting of an operational
amplifier 16 which constitutes the d.c. tester 200.
[0060] The operational amplifier 16 operates in a manner such that
a voltage at the voltage detecting terminal T.sub.V is equal to the
voltage applied to the non-inverting input terminal. As a
consequence, there is produced a voltage at the voltage detecting
terminal T.sub.V which is equal to the V.sub.L or V.sub.H applied
from the DA converter 17, and this voltage is applied to the
sensing point SEN through the second switch S2 and the resistor R4,
and is then fed to a terminal on IC under test 300 through some one
of the change-over switches S.sub.21-S.sub.2n.
[0061] During the execution of the function test, the switches
S.sub.11-S.sub.1n and the switches S1, S2, S4 are all turned on.
The timing to execute d.c. leak test may be determined, for
example, as follows: A d.c. test timing (a time interval allocated
to such timing is a length of time required to test a single
terminal) as shown in FIG. 2A is previously set up in a function
test program of a test program which is read into the main
controller MAIN, and a control signal HIP which controls all the
drivers 12 for respective function test units 106A-106N or driver
12 connected to the terminal which is subject to the d.c. test to
be in a high impedance mode (see FIG. 2D) is produced at the timing
of the d.c. test, thus controlling the driver 12 to be in its high
impedance condition while applying a voltage generating command to
the d.c. tester so as to control the d.c. tester 200 to generate a
given voltage for measuring the leak current under the condition
that such voltage is applied.
[0062] Incidentally, for the timing for the function test to be
interrupted by the d.c. test, a timing may be chosen which may
occur immediately after a test pattern signal is written into an IC
under test 300 to allow the d.c. test to be directly executed since
the individual terminals on the IC under test 300 are set up in an
input mode when the write operation takes place.
[0063] After the leak test is executed with respect to a single
terminal, the function test is resumed. During the execution of the
function test, the change-over switches S.sub.21-S.sub.2n are
changed (see FIG. 2E), thus connecting the d.c. tester 200 to
another terminal. A d.c. test timing is provided at any timing
position subsequent to the completion of such connection for
execution of the leak test of a next terminal.
[0064] When change-over switches S.sub.21-S.sub.2n are changed
during the execution of the function test in this manner, the time
interval required for the leak test which is inserted into the
execution of the function test can be limited to be very short, and
if the function test and the d.c. test are executed concurrently,
the overall required time cannot be significantly longer than the
length of time required for the function test alone.
[0065] Incidentally, a current measuring circuit of the d.c. tester
200 will be briefly described. In the present embodiment, a
resistor R1 having a high resistance (on the order of 100 k.OMEGA.)
for measuring a minimal current (leak current) and a resistor R2
having a small resistance (on the order of 100 .OMEGA.) for
measuring a high current (an output current from the IC under test)
are connected in series, thus omitting the range changing switch
S.sub.b shown in FIG. 5. Specifically, the minimal current
measuring resistor R1 is shunted by diodes D1 and D2. For
measurement of high currents, these diodes D1 and D2 are turned on,
allowing the high current to be bypassed by diodes D1 or D2, and
under this condition, a voltage developed across the resistor R2 is
detected by the subtraction circuit 18B, and fed through switch S5
to the AD converter 19 for AD conversion therein to be input to the
main controller MAIN, for example.
[0066] On the other hand, when measuring a minimal current, only a
voltage on the order of several tens of mV can be developed across
the resistor R1. Accordingly, the diodes D1 and D2 are maintained
off. Thus, by measuring a voltage developed across the resistor R1,
a leak current passing through a terminal on an IC under test 300
can be measured. Specifically, a voltage developed across the
register R1 is picked out by the subtraction circuit 18A, and is
then fed through the switch S4 to the AD converter 19 for the AD
conversion therein, to be input to the main controller MAIN where
it is compared against a reference value if it is acceptable or
faulty.
[0067] Incidentally, in a high current measuring mode in which a
current which occurs in an output mode of the IC under test 300 is
measured, the switches S.sub.11-S.sub.1n are controlled to be off,
and the function tester 100 is disconnected from the IC under test
while only the d.c. tester 200 is connected to the IC under test
300. In addition, within the d.c. tester 200, the first S1 switch
is turned off, the second and the third switch S2, S3 are turned
on, the switch S4 is turned off, and the switch S5 is turned on for
the execution of the d.c. test.
INDUSTRIAL AVAILABILITY
[0068] As described above, with the IC testing method according to
the invention, changing S.sub.21-S.sub.2n which takes time for its
completion due to their slow response is effected during the
execution of the function test, and the driver 12 is controlled to
its high impedance mode in the course of the function test in order
to execute the d.c. test (the leak test) for the purpose of the
testing method. Accordingly, the function test and the leak test
can be completed in a time interval represented by a sum of time
interval required for the function test and a net time interval
required for the d.c. test (not including a time interval to change
the switches). As a consequence, there is obtained an advantage
that an overall testing time interval may be considerably reduced.
It then follows that its effect will be remarkable when applied in
testing quantities of IC's in a brief time interval by IC
manufacturing maker, for example.
* * * * *