U.S. patent application number 09/945241 was filed with the patent office on 2002-03-21 for method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument.
Invention is credited to Makabe, Akira, Matsushima, Fumiaki, Ota, Tsutomu.
Application Number | 20020033531 09/945241 |
Document ID | / |
Family ID | 18754052 |
Filed Date | 2002-03-21 |
United States Patent
Application |
20020033531 |
Kind Code |
A1 |
Matsushima, Fumiaki ; et
al. |
March 21, 2002 |
Method for forming a bump, semiconductor device and method of
fabricating same, semiconductor chip, circuit board, and electronic
instrument
Abstract
A method for forming a bump includes the steps of forming a
resist layer so that a through-hole formed therein is located on a
pad; and forming a metal layer to be electrically connected to the
pad conforming to the shape of the through-hole. The metal layer is
formed so as to have a shape in which is formed a region for
receiving a soldering or brazing material.
Inventors: |
Matsushima, Fumiaki;
(Chino-shi, JP) ; Ota, Tsutomu; (Chino-shi,
JP) ; Makabe, Akira; (Shiojin-shi, JP) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, PLC
P.O. BOX 828
BLOOMFIELD HILLS
MI
48303
US
|
Family ID: |
18754052 |
Appl. No.: |
09/945241 |
Filed: |
August 31, 2001 |
Current U.S.
Class: |
257/734 ;
257/E21.508; 257/E23.021 |
Current CPC
Class: |
H01L 2924/01078
20130101; H01L 2924/0103 20130101; H01L 2924/01047 20130101; H01L
24/11 20130101; H01L 2924/01061 20130101; H01L 24/03 20130101; H01L
2224/13083 20130101; H01L 24/13 20130101; H01L 2924/01075 20130101;
H01L 2224/11849 20130101; H01L 2224/13012 20130101; H01L 24/05
20130101; H01L 2224/05001 20130101; H01L 2224/11901 20130101; H01L
2924/01013 20130101; H01L 2224/13155 20130101; H01L 2924/01082
20130101; H01L 2224/1147 20130101; H01L 2224/131 20130101; H01L
2224/13144 20130101; H01L 2224/13078 20130101; H01L 2924/01004
20130101; H01L 2924/15311 20130101; H01L 2224/274 20130101; H01L
2924/01029 20130101; H01L 2924/01033 20130101; H01L 2924/014
20130101; H01L 2924/14 20130101; H01L 2224/05568 20130101; H01L
2224/1308 20130101; H01L 2924/00013 20130101; H01L 2224/11462
20130101; H01L 2924/01046 20130101; H01L 24/94 20130101; H01L
2224/1411 20130101; H01L 2924/01005 20130101; H01L 2924/01079
20130101; H01L 2224/11822 20130101; H01L 2924/01006 20130101; H01L
2224/05022 20130101; H01L 2224/13144 20130101; H01L 2924/00014
20130101; H01L 2224/13155 20130101; H01L 2924/00014 20130101; H01L
2224/131 20130101; H01L 2924/014 20130101; H01L 2224/1308 20130101;
H01L 2224/131 20130101; H01L 2924/014 20130101; H01L 2924/00013
20130101; H01L 2224/13099 20130101; H01L 2224/13012 20130101; H01L
2924/00012 20130101; H01L 2224/05644 20130101; H01L 2924/00014
20130101; H01L 2224/05124 20130101; H01L 2924/00014 20130101; H01L
2224/05144 20130101; H01L 2924/00014 20130101; H01L 2224/05147
20130101; H01L 2924/00014 20130101; H01L 2224/05155 20130101; H01L
2924/00014 20130101; H01L 2224/05164 20130101; H01L 2924/00014
20130101 |
Class at
Publication: |
257/734 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 4, 2000 |
JP |
2000-267076 |
Claims
What is claimed is:
1. A method for forming a bump comprising the steps of: forming a
resist layer so that a through-hole formed therein is located on a
pad; and forming a metal layer to be electrically connected to the
pad conforming to the shape of the through-hole, wherein the metal
layer is formed so as to have a shape in which is formed a region
for receiving a soldering or brazing material.
2. The method for forming a bump according to claim 1, wherein the
resist layer is formed so as to have a projection on the inner side
of the through-hole.
3. The method for forming a bump according to claim 1, wherein the
resist layer is formed so that part of the resist layer remains at
the center of the through-hole.
4. The method for forming a bump according to claim 1, wherein a
plurality of the through-holes are formed in the resist layer so
that at least a part of each of the through-holes is superposed on
the pad, and a plurality of the metal layers are formed, each of
the plurality of the metal layers conforming to each of the
through-holes to form the region for receiving the soldering or
brazing material between the adjacent metal layers of the plurality
of the metal layers on the pad.
5. The method for forming a bump according to claim 1, wherein the
metal layer comprises first and second metal layers, wherein the
first metal layer is formed in a state in which the resist layer is
formed, and the second metal layer is formed on the first metal
layer.
6. The method for forming a bump according to claim 1, wherein the
metal layer comprises first and second metal layers, wherein the
first metal layer is formed in a state in which the resist layer is
formed, and after removing the resist layer, the second metal layer
is formed so as to cover a surface of the first metal layer.
7. The method for forming a bump according to claim 5, wherein the
pad is covered with an insulating film, the resist layer is formed
on the insulating film, an opening for exposing at least part of
the pad is formed in the insulating film after forming the
through-hole in the resist layer, and the first metal layer is
formed on the pad in a state in which the resist layer is
formed.
8. The method for forming a bump according to claim 6, wherein the
pad is covered with an insulating film, the resist layer is formed
on the insulating film, an opening for exposing at least part of
the pad is formed in the insulating film after forming the
through-hole in the resist layer, and the first metal layer is
formed on the pad in a state in which the resist layer is
formed.
9. The method for forming a bump according to claim 5, wherein the
first and second metal layers are formed by electroless
plating.
10. The method for forming a bump according to claim 6, wherein the
first and second metal layers are formed by electroless
plating.
11. The method for forming a bump according to claim 5, wherein the
first metal layer is formed of a material containing nickel.
12. The method for forming a bump according to claim 6, wherein the
first metal layer is formed of a material containing nickel.
13. The method for forming a bump according to claim 5, wherein the
second metal layer is formed of a material containing gold.
14. The method for forming a bump according to claim 6, wherein the
second metal layer is formed of a material containing gold.
15. A method of fabricating a semiconductor device comprising the
steps of: bonding a plurality of metal layers to a plurality of
leads through a soldering or brazing material, each of the metal
layers formed on each of a plurality of pads of a semiconductor
chip , each of the metal layers having a shape in which is formed a
region for receiving the soldering or brazing material, wherein the
soldering or brazing material, when melted, is allowed to flow into
the region of each of the metal layers for receiving the soldering
or brazing material so as not to spread onto an adjacent pad of the
plurality of pads.
16. The method of fabricating a semiconductor device according to
claim 15, wherein at least one depression is formed in a side of
one of the metal layers, and the soldering or brazing material is
allowed to flow into the depression.
17. The method of fabricating a semiconductor device according to
claim 15, wherein one of the metal layers is formed so that a
depression which is provided in the direction of the height of the
metal layers is formed at the center, and the soldering or brazing
material is allowed to flow into the depression.
18. The method of fabricating a semiconductor device according to
claim 15, wherein two or more metal layers of the plurality of
metal layers are formed so as to be connected to one of the pads,
and the soldering or brazing material is allowed to flow into a
region formed between the adjacent metal layers of the plurality of
metal layers on one of the pads.
19. A semiconductor device fabricated by the fabrication method
according to claim 15.
20. A semiconductor chip comprising a plurality of pads, and a
metal layer disposed on each of the pads which is formed to have a
shape in which is formed a region for receiving a soldering or
brazing material.
21. The semiconductor chip according to claim 20, wherein at least
one depression is formed in a side of the metal layer.
22. The semiconductor chip according to claim 20, wherein a
depression which is provided in the direction of the height of the
metal layer is formed at the center of the metal layer.
23. The semiconductor chip according to claim 20, wherein two or
more the metal layers are formed on one of the pads.
24. A semiconductor device comprising: a semiconductor chip having
a plurality of pads; a metal layer disposed on each of the pads,
the metal layer formed to have a shape in which is formed a region
for receiving a soldering or brazing material; and a plurality of
leads, wherein the metal layer is bonded to one of the leads
through the soldering or brazing material, and part of the
soldering or brazing material is put in the region for receiving
the soldering or brazing material.
25. The semiconductor device according to claim 24, wherein at
least one depression is formed in a side of the metal layer, and
the soldering or brazing material is put in the depression.
26. The semiconductor device according to claim 24, wherein a
depression which is provided in the direction of the height of the
metal layer is formed at the center of the metal layer, and the
soldering or brazing material is put in the depression.
27. The semiconductor device according to claim 24, wherein two or
more the metal layers are formed on one of the pads, and the
soldering or brazing material is put in a region formed between
adjacent metal layers of the two or more the metal layers on one of
the pads.
28. A circuit board on which is mounted the semiconductor device
according to claim 24.
29. An electronic instrument comprising the semiconductor device
according to claim 24.
Description
[0001] Japanese Patent Application No. 2000-267076, filed Sep. 4,
2000, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
[0002] The present invention relates to a method for forming a
bump, a semiconductor device and a method of fabricating the same,
a semiconductor chip, a circuit board, and an electronic
instrument.
BACKGROUND
[0003] A method is known in the art in which metal bumps are formed
on pads of a semiconductor chip by applying electroless plating or
the like. The semiconductor chip is electrically connected to an
interconnect pattern (leads) on a substrate by allowing solder
applied to the metal bumps to melt, for example. According to this
method, the pads can be connected to the leads by melting the
solder, differing from the case of connecting the pads to the leads
by applying heat and pressure to the leads, thereby decreasing the
amount of pressure applied to the surface of the semiconductor
chip. This allows the pads to be disposed not only in the end
sections of the semiconductor chip but also in a device formation
region, whereby a larger number of pads can be disposed at a
coarser pitch. Moreover, use of solder ensures that a semiconductor
device can be fabricated at low cost in comparison with the case of
forming gold bumps.
[0004] However, according to this configuration, solder applied to
each pad may flow onto the adjacent pads upon melting when
connecting the pads to the interconnect pattern, thereby causing a
short circuit to occur between the pads. This problem cannot be
solved by merely decreasing the amount of solder applied to each
pad.
SUMMARY
[0005] A method for forming a bump according to the first aspect of
the present invention comprises the steps of:
[0006] forming a resist layer so that a through-hole formed therein
is located on a pad; and
[0007] forming a metal layer to be electrically connected to the
pad conforming to the shape of the through-hole,
[0008] wherein the metal layer is formed so as to have a shape in
which is formed a region for receiving a soldering or brazing
material.
[0009] A method of fabricating a semiconductor device according to
the second aspect of the present invention comprises the steps
of:
[0010] bonding a plurality of metal layers to a plurality of leads
through a soldering or brazing material, each of the metal layers
formed on each of a plurality of pads of a semiconductor chip, each
of the metal layers having a shape in which is formed a region for
receiving the soldering or brazing material,
[0011] wherein the soldering or brazing material, when melted, is
allowed to flow into the region of each of the metal layers for
receiving the soldering or brazing material so as not to spread
onto an adjacent pad of the plurality of pads.
[0012] A semiconductor device according to the third aspect of the
present invention is fabricated by the above method of fabricating
a semiconductor device.
[0013] A semiconductor chip according to the fourth aspect of the
present invention comprises a plurality of pads, and a metal layer
disposed on each of the pads which is formed to have a shape in
which is formed a region for receiving a soldering or brazing
material.
[0014] A semiconductor device according to the fifth aspect of the
present invention comprises:
[0015] a semiconductor chip having a plurality of pads;
[0016] a metal layer disposed on each of the pads, the metal layer
formed to have a shape in which is formed a region for receiving a
soldering or brazing material; and
[0017] a plurality of leads,
[0018] wherein the metal layer is bonded to one of the leads
through the soldering or brazing material, and part of the
soldering or brazing material is put in the region for receiving
the soldering or brazing material.
[0019] According to the sixth aspect of the present invention,
there is provided a circuit board on which the above semiconductor
device is mounted.
[0020] An electronic instrument according to the seventh aspect of
the present invention comprises the above semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a view showing a method for forming bumps
according to a first embodiment to which the present invention is
applied.
[0022] FIG. 2 is a view showing the method for forming bumps
according to the first embodiment to which the present invention is
applied.
[0023] FIGS. 3A to 3C are views showing the method for forming
bumps according to the first embodiment to which the present
invention is applied.
[0024] FIGS. 4A to 4C are views showing the method for forming
bumps according to the first embodiment to which the present
invention is applied.
[0025] FIG. 5 is a view showing the method for forming bumps
according to the first embodiment to which the present invention is
applied.
[0026] FIGS. 6A to 6C are views showing the method for forming
bumps according to a modification example of the first embodiment
to which the present invention is applied.
[0027] FIG. 7 is a view showing a semiconductor device and a method
of fabricating the semiconductor device according to the first
embodiment to which the present invention is applied.
[0028] FIG. 8 is a view showing a method for forming bumps
according to a second embodiment to which the present invention is
applied.
[0029] FIGS. 9A to 9C are views showing the method for forming
bumps according to the second embodiment to which the present
invention is applied.
[0030] FIG. 10 is a view showing the method for forming bumps
according to the second embodiment to which the present invention
is applied.
[0031] FIG. 11 is a view showing a method for forming bumps
according a modification example of the second embodiment to which
the present invention is applied.
[0032] FIGS. 12A and 12B are views showing a method for forming
bumps according to a third embodiment to which the present
invention is applied.
[0033] FIG. 13 is a view showing a circuit board equipped with a
semiconductor device according to an embodiment to which the
present invention is applied.
[0034] FIG. 14 is a view showing an electronic instrument equipped
with a semiconductor device according to an embodiment to which the
present invention is applied.
[0035] FIG. 15 is a view showing an electronic instrument equipped
with a semiconductor device according to an embodiment to which the
present invention is applied.
DETAILED DESCRIPTION
[0036] The embodiment of the present invention has been achieved to
solve the above conventional problem. An object of the embodiment
of the present invention is to provide a method for forming a bump
capable of dealing with a fine pitch with high reliability, a
semiconductor device and a method of fabricating the same, a
semiconductor chip, a circuit board, and an electronic
instrument.
[0037] (1) A method for forming a bump according to one embodiment
of the present invention comprises the steps of:
[0038] forming a resist layer so that a through-hole formed therein
is located on a pad; and
[0039] forming a metal layer to be electrically connected to the
pad conforming to the shape of the through-hole,
[0040] wherein the metal layer is formed so as to have a shape in
which is formed a region for receiving a soldering or brazing
material.
[0041] According to this embodiment of the present invention, the
metal layers are formed into a specific shape conforming to the
shape of the through-holes. The metal layers have a region for
receiving the brazing material. This allows the brazing material to
flow into the above region of the metal layers, thereby preventing
the brazing material from spreading outside the metal layers.
Specifically, the brazing material melted on the metal layers can
be prevented from flowing onto the adjacent pads, for example.
Therefore, occurrence of a short circuit between the pads can be
prevented, whereby the yield in the fabrication can be
increased.
[0042] (2) In this method for forming a bump,
[0043] the resist layer may be formed so as to have a projection on
the inner side of the through-hole.
[0044] This enables the formation of depressions in the sides of
the metal layers. This allows the brazing material to flow into the
depressions of the metal layers, thereby preventing the brazing
material from spreading outside the metal layers.
[0045] (3) In this method for forming a bump,
[0046] the resist layer may be formed so that part of the resist
layer remains at the center of the through-holes.
[0047] This enables the formation of the region for receiving the
brazing material at the center of the metal layers. This allows the
brazing material to flow into the region at the center of the metal
layers, thereby preventing the brazing material from spreading
outside the metal layers.
[0048] (4) In this method for forming a bump,
[0049] a plurality of the through-holes may be formed in the resist
layer so that at least a part of each of the through-holes is
superposed on the pad, and
[0050] a plurality of the metal layers may be formed, each of the
plurality of the metal layers conforming to each of the
through-holes to form the region for receiving the soldering or
brazing material between the adjacent metal layers of the plurality
of the metal layers on the pad.
[0051] This prevents the brazing material from spreading outside
the metal layers by allowing the brazing material to flow into the
region formed between the adjacent metal layers on each pad.
[0052] (5) In this method for forming a bump,
[0053] the metal layer may comprise first and second metal
[0054] wherein the first metal layer may be formed in a state in
which the resist layer is formed, and the second metal layer may be
formed on the first metal layer.
[0055] In the case where a material to which the brazing material
readily adheres in comparison with the first metal layers is used
as the material for the second metal layers, the brazing material
can be applied only to the upper surface of the metal layers.
Specifically, this prevents the brazing material from spreading
outside the metal layers more reliably.
[0056] (6) In this method for forming a bump,
[0057] the metal layer may comprise first and second metal
layers,
[0058] wherein the first metal layer may be formed in a state in
which the resist layer is formed, and
[0059] after removing the resist layer, the second metal layer may
be formed so as to cover a surface of the first metal layer.
[0060] This prevents the surface of the first metal layer from
being oxidized.
[0061] (7) In this method for forming a bump,
[0062] the pad may be covered with an insulating film,
[0063] the resist layer may be formed on the insulating film,
[0064] an opening for exposing at least part of the pad may be
formed in the insulating film after forming the through-hole in the
resist layer, and
[0065] the first metal layer may be formed on the pad in a state in
which the resist layer is formed.
[0066] Since the openings are formed in the insulating film and the
first metal layers to be electrically connected to the pads are
formed using the through-holes in the same resist layer, the bumps
can be formed by simplified steps.
[0067] (8) In this method for forming a bump,
[0068] the first and second metal layers may be formed by
electroless plating.
[0069] (9) In this method for forming a bump,
[0070] the first metal layer may be formed of a material containing
nickel.
[0071] (10) In this method for forming a bump,
[0072] the second metal layers may be formed using a material
containing gold.
[0073] (11) A method of fabricating a semiconductor device
according to another embodiment of the present invention comprises
the steps of:
[0074] bonding a plurality of metal layers to a plurality of leads
through a soldering or brazing material, each of the metal layers
formed on each of a plurality of pads of a semiconductor chip, each
of the metal layers having a shape in which is formed a region for
receiving the soldering or brazing material,
[0075] wherein the soldering or brazing material, when melted, is
allowed to flow into the region of each of the metal layers for
receiving the soldering or brazing material so as not to spread
onto an adjacent pad of the plurality of pads.
[0076] According to this embodiment of the present invention, the
brazing material applied between the metal layers and the leads is
allowed to flow into the region of the metal layer, thereby
preventing the brazing material from spreading outside the metal
layers. Specifically, the brazing materials melted on the metal
layers can be prevented from flowing onto the adjacent pads.
Therefore, occurrence of a short circuit between the pads can be
prevented, whereby the yield in the fabrication can be
increased.
[0077] (12) In this method of fabricating a semiconductor
device,
[0078] at least one depression may be formed in a side of one of
the metal layers, and
[0079] the soldering or brazing material may be allowed to flow
into the depression.
[0080] This prevents the brazing material from spreading outside
the metal layers by allowing the brazing material to flow into the
depression of the metal layers.
[0081] (13) In this method of fabricating a semiconductor
device,
[0082] one of the metal layer may be formed so that a depression
which is provided in the direction of the height of the metal
layers is formed at the center, and
[0083] the soldering or brazing material may be allowed to flow
into the depression.
[0084] This prevents the brazing material from spreading outside
the metal layers by allowing the brazing material to flow into the
depression which is provided in the direction of the height of the
metal layers.
[0085] (14) In this method of fabricating a semiconductor
device,
[0086] two or more metal layers of the plurality of metal layers
may be formed so as to be connected to one of the pads, and
[0087] the soldering or brazing material may be allowed to flow
into a region formed between the adjacent metal layers of the
plurality of metal layers on one of the pads.
[0088] This prevents the brazing material from spreading outside
the metal layers by allowing the brazing material to flow into the
region formed between the adjacent metal layers on each pad.
[0089] (15) A semiconductor device according to an embodiment of
the present invention is fabricated by the above method of
fabricating a semiconductor device.
[0090] (16) A semiconductor chip according to further embodiment of
the present invention comprises a plurality of pads, and a metal
layer disposed on each of the pads which is formed to have a shape
in which is formed a region for receiving a soldering or brazing
material.
[0091] (17) In this semiconductor chip,
[0092] at least one depression may be formed in a side of the metal
layer.
[0093] (18) In this semiconductor chip,
[0094] a depression which is provided in the direction of the
height of the metal layers may be formed at the center of the metal
layers.
[0095] (19) In this semiconductor chip, two or more the metal
layers may be formed on one of the pads.
[0096] (20) A semiconductor device according to still another
embodiment of the present invention comprises:
[0097] a semiconductor chip having a plurality of pads;
[0098] a metal layer disposed on each of the pads, the metal layer
formed to have a shape in which is formed a region for receiving a
soldering or brazing material; and
[0099] a plurality of leads,
[0100] wherein the metal layer is bonded to one of the leads
through the soldering or brazing material, and part of the
soldering or brazing material is put in the region for receiving
the soldering or brazing material.
[0101] According to this embodiment of the present invention, the
brazing material can be prevented from spreading outside the metal
layer by allowing part of the brazing material to flow into the
region of the metal layers. Specifically, the brazing material
melted on the metal layers can be prevented from flowing onto the
adjacent pads. Therefore, a highly reliable semiconductor device
can be provided by preventing occurrence of a short circuit between
the pads.
[0102] (21) In this semiconductor device,
[0103] at least one depression may be formed in a side of the metal
layer, and
[0104] the soldering or brazing material may be put in the
depression.
[0105] (22) In this semiconductor device,
[0106] a depression which is provided in the direction of the
height of the metal layer may be formed at the center of the metal
layer, and
[0107] the soldering or brazing material may be put in the
depression.
[0108] (23) In this semiconductor device,
[0109] two or more the metal layers may be formed on one of the
pads, and
[0110] the soldering or brazing material may be put in a region
formed between adjacent metal layers of the two or more the metal
layers on one of the pads.
[0111] (24) According to still another embodiment of the present
invention, there is provided a circuit board on which the above
semiconductor device is mounted.
[0112] (25) An electronic instrument according to yet another
embodiment of the present invention comprises the above
semiconductor device.
[0113] Preferred embodiments of the present invention are described
below with reference to the drawings. However, the present
invention is not limited to the following embodiments.
[0114] (First Embodiment)
[0115] FIGS. 1 to 6C are views showing a method for forming bumps
according to a first embodiment to which the present invention is
applied. The present embodiment illustrates an example in which
bumps are formed on a semiconductor chip. However, the method for
forming bumps according to the present invention is not limited
thereto. The method may be applied for forming bumps on leads. The
leads may be an interconnect pattern formed on a substrate. In this
case, lands of the interconnect pattern correspond to pads. The
present invention may be applied when forming bumps on pads formed
on a semiconductor wafer.
[0116] In the present embodiment, a semiconductor chip 10 shown in
FIG. 1 is provided. The semiconductor chip 10 is generally formed
in the shape of a rectangular parallelepiped (including cube). The
semiconductor chip 10 may be formed in the shape of a sphere, for
example. The thickness of the semiconductor chip 10 is not limited.
The semiconductor chip 10 ground into a thin piece may be used.
[0117] The semiconductor chip 10 includes a plurality of pads 12.
The pads 12 become electrodes for an integrated circuit formed
inside the semiconductor chip 10. The pads 12 are generally formed
on the side of the semiconductor chip 10 on which the integrated
circuit is formed. In this case, the pads 12 may be formed either
outside or inside the region in which the integrated circuit is
formed. The pads 12 are formed in one or more of columns at the
ends or center of the semiconductor chip 10. The pads 12 may be
arranged in a matrix of a plurality of rows and columns on the
surface of the semiconductor chip 10.
[0118] The planar shape of the pads 12 may be either rectangular or
circular. The pads 12 are generally formed using a material
containing aluminum. The pads 12 may be formed using a material
containing copper or the like.
[0119] An insulating film 14 is formed on the surface of the
semiconductor chip 10 on which the pads 12 are formed. In the
present embodiment, the insulating film 14 is formed so as to cover
each pad 12, as shown in FIG. 1. Specifically, the semiconductor
chip 10 in which each pad 12 is not exposed through the insulating
film 14 may be used. In the present embodiment, bumps are formed on
the pads 12 using a resist layer formed to allow each pad 12 to be
exposed through the insulating film 14.
[0120] The insulating film 14 is formed of either a single layer or
a plurality of layers. The thickness of the insulating film 14 is
not limited. The insulating film 14 may be referred to as a
passivation film. The insulating film 14 is formed using SiO.sub.2,
SiN, a polyimide resin, or the like.
[0121] A method of fabricating a semiconductor device according to
the present embodiment includes the following steps using the
semiconductor chip 10. The following description is also applicable
to semiconductor wafer processing.
[0122] A resist layer 20 is formed on the semiconductor chip 10, as
shown in FIGS. 2 and 3A. FIG. 2 is a plan view and FIG. 3 is a
cross-sectional view showing the semiconductor chip 10. The resist
layer 20 is formed on the surface of the semiconductor chip 10 on
which the pads 12 are formed, specifically, on the insulating film
14. The thickness of the resist layer 20 may be appropriately
determined depending on the height of bumps which are formed later.
The resist layer 20 may be formed to a thickness of about 20 .mu.m,
for example.
[0123] The resist layer 20 has through-holes 22 formed therein
above the pads 12, specifically, on the insulating film 14.
Specifically, the through-holes 22 are formed so that at least part
(part or all) of the through-holes 22 is superposed on the pads 12.
Allowing part of the through-holes 22 to be superposed on the pads
12 enables the bumps formed in the through-holes 22 to be
electrically connected to the pads 12.
[0124] In the present embodiment, the through-holes 22 are formed
so that projections are formed on the inner side of the
through-holes 22, as shown in FIG. 2. In other words, a plurality
of projections is formed on the wall surface of the resist layer 20
in contact with the through-holes 22. One or a plurality of
projecting sections 24 is formed on the resist layer 20. The planar
shape of the through-holes 22 may be similar to the shape of the
pads 12, wherein part of the resist layer 20 projects to each side
toward the inside of the through-holes 22. The planar shape of the
through-holes 22 may be circular, wherein part of the resist layer
20 projects toward the inside of the through-holes 22. Depressions
36 (see FIG. 5) can be formed in the side of the bumps by forming
the projecting sections 24 of the resist layer 20. The
through-holes 22 may be formed through the resist layer 20 in the
same planar shape in the direction of the thickness of the resist
layer 20.
[0125] Photolithographic technology may be applied as a method for
forming the resist layer 20. Specifically, the photosensitive
resist layer 20 may be exposed to energy through a mask (not shown)
and subjected to development, thereby forming the through-holes 22.
The through-holes 22 can be formed into a specific shape by forming
a mask so that the resist layer 20 projects toward the inside of
the through-holes 22. The resist layer 20 may be either a positive
resist or a negative resist.
[0126] The through-holes 22 may be formed into a specific shape by
etching the non-photosensitive resist layer 20. The resist layer 20
may be formed by applying screen printing or an ink-jet method
insofar as the through-holes 22 are formed into a specific
shape.
[0127] The through-holes 22 may be formed so as not to cross the
circumference of the pads 12, as shown in FIG. 2. This enables the
bumps to be formed without causing a short circuit to occur between
adjacent pads 12 even if the pitch between each pad 12 is extremely
fine. The through-holes 22 may be formed so as to be larger than
the circumference of the pads 12. The through-holes 22 may be
formed so that part of the circumference thereof intersects the
circumference of the pads 12.
[0128] Part of the insulating film 14 is removed through the
through-holes 22 formed in the resist layer 20, as shown in FIG.
3B. Specifically, openings 26 for exposing at least part (part or
all) of the pads 12 are formed by removing the insulating film 14
in the area inside the through-holes 22. The openings 26 may be
formed by etching. The etching technique may be either a chemical
or physical technique, or a combination of these techniques.
Etching characteristics may be either isotropic or an isotropic. In
the case where isotropic etching is applied, the openings 26 in the
insulating film 14 may be formed outside the circumference of the
through-holes 22. The openings 26 in the insulating film 14 may be
formed inside the circumference of the pads 12. The openings 26 in
the insulating film 14 may be formed outside the circumference of
the pads 12. The size of the exposed area of the pads 12 by the
openings 26 is not limited. For example, the exposed area may be in
the shape of a square having a side length of about 20 .mu.m.
[0129] First metal layers 30 are formed conforming to the shape of
the through-holes 22, as shown in FIG. 3C. Specifically, the first
metal layers 30 are formed along the inner side of the
through-holes 22. The through-holes 22 may be completely filled
with the first metal layers 30 so that the surfaces of the first
metal layers 30 and the resist layer 20 are level. The first metal
layers 30 may be either higher than or lower than the surface of
the resist layer 20. The first metal layers 30 can be formed into a
specific shape by forming the first metal layers 30 along the inner
sides of the through-holes 22.
[0130] Since the through-holes 22 link with the openings 26 in the
insulating film 14, the bumps to be electrically connected to the
pads 12 can be formed by forming the first metal layers 30 in the
through-holes 22. The first metal layers 30 may be formed of either
a single layer as shown in FIG. 3C or a plurality of layers. The
first metal layers 30 may be formed using a material containing
nickel. Use of nickel layers as the first metal layers 30 enables
the bumps to be formed at low cost in a comparatively short period
of time. The first metal layers 30 may be formed using a material
containing gold.
[0131] The first metal layers 30 may be formed by electroless
plating. A method for forming the nickel layers (first metal layers
30) on the pads 12 containing aluminum is described below.
[0132] The surface (aluminum) of the pads 12 may be replaced by
zinc using a zincate treatment. Specifically, aluminum is replaced
by zinc by applying an alkaline zinc solution onto the surface of
each pad 12. In this case, the semiconductor chip 10 may be dipped
into an alkaline zinc solution. It is preferable to heat the resist
layer 20 in advance for this treatment at a temperature of about
100-200.degree. C. for several minutes. This provides the resist
layer 20 with an increased resistance to a strong alkaline
solution. Specifically, the resist layer 20 becomes scarcely
soluble. The resist layer 20 may be irradiated with ultraviolet
rays in order to prevent heat deformation of the resist layer 20.
It is preferable to use ultraviolet rays with a dominant wavelength
of 254 nm. The dose may be appropriately adjusted depending on the
thickness of the resist layer 20. It is advantageous to irradiate
the resist layer 20 with ultraviolet rays while allowing a solvent
included in the resist layer 20 to volatile under reduced pressure.
It is also advantageous to heat the resist layer 20 and the like at
a temperature of about 100-200.degree. C. during irradiation with
ultraviolet rays.
[0133] It is preferable to dissolve residual insulating films 14
remaining on the semiconductor chip 10 before dipping the pads 12
into an alkaline zinc solution. The residual insulating films 14
may be dissolved by dipping the semiconductor chip 10 into a weak
hydrogen fluoride solution. After dissolving the residual
insulating films 14, it is preferable to remove oxide films formed
in the exposed area of the pads 12 by dipping the pads 12 into an
alkaline solution. This enables the surface of the pads 12 to be
reliably exposed, whereby aluminum on the surface of the pads 12
can be replaced by zinc.
[0134] Zinc may be deposited on the surface of the pads 12 by
dipping the pads 12 into an alkaline zinc solution, dissolving zinc
by which aluminum is replaced using nitric acid, and further
dipping the pads 12 into an alkaline zinc solution. This enables
zinc to be reliably deposited on the surface of the pads 12.
[0135] The pads 12 are dipped into an electroless nickel solution,
thereby forming the nickel layers (first metal layers 30) in the
through-holes 22. In this case, the solution maybe heated. For
example, an electroless nickel solution (4.5 pH) may be heated at a
temperature of about 90.degree. C. The semiconductor chip 10 is
dipped into this solution for about 45 minutes, thereby forming the
nickel layers (first metal layers 30) with a thickness of about 20
.mu.m. The thickness of the first metal layers 30 may be either
smaller than or greater than the height of the through-holes 22.
The thickness of the first metal layers 30 may be appropriately
determined by a period of time for dipping the pads 12 into the
solution or the like.
[0136] Other metal layers may be interposed between the pads 12 and
the first metal layers 30. For example, in the case of forming the
first metal layers 30 on the pads 12 by the zincate treatment, part
of the zinc layers remaining on the aluminum (pads 12) may be
interposed between the first metal layers 30 and the pads 12.
[0137] Differing from the above example, a solution containing a
reducing agent such as palladium may be applied to the pads 12 and
an electroless nickel solution may be applied thereafter, thereby
forming the nickel layers (first metal layers 30) with palladium as
nuclei.
[0138] In the above steps, the first metal layers 30 are formed in
the through-holes 22 while allowing the resist layer formed to
expose each pad 12 to remain. Specifically, the openings 26 are
formed in the insulating film 14 and the first metal layers 30
connected to the pads 12 are formed using the same resist layer 20,
whereby the bumps can be formed by simplified steps.
[0139] After forming the first metal layers 30, the resist layer 20
is removed, as shown in FIG. 4A. The first metal layers 30 are
formed conforming to the shape of the through-holes 22 by the above
steps.
[0140] Second metal layers 32 may be optionally formed on the
surface of the first metal layers 30, as shown in FIG. 4B. The
second metal layers 32 may be formed of a single layer as shown in
FIG. 4B or a plurality of layers. It is preferable to form the
second metal layers 32 conforming to the shape of the first metal
layers 30. Specifically, it is preferable to form thin second metal
layers 32 so that the depressions in the first metal layers 30 are
not filled with the second metal layers 32. The second metal layers
32 may be formed so as to cover the surface of the first metal
layers 30. This prevents the surface of the first metal layers 30
from being oxidized. It is preferable to form at least the surface
of the second metal layers 32 using a material containing gold.
[0141] The second metal layers 32 may be formed by electroless
plating. For example, gold layers (second metal layers 32) may be
formed on the surface of the nickel layers (first metal layers 30)
by dipping the semiconductor chip 10 into an electroless gold
plating solution. The thickness of the gold layers (second metal
layers 32) is not limited insofar as the gold layers can be formed
on the surface of the first metal layers 30. For example, the gold
layers (second metal layers 32) may be formed to a thickness of
about 0.15 .mu.m.
[0142] In the case of forming the first metal layers 30 or second
metal layers 32 by electroless plating by dipping the semiconductor
chip 10 into a desired solution, it is preferable to cover the side
and the back face of the semiconductor chip 10 with a protective
film in advance. A resist layer may be used as the protective film.
In this case, the resist layer may be a non-photosensitive resist.
The resist layer may be formed to a thickness of about 2 .mu.m on
the side and the back face of the semiconductor chip 10. Potential
changes in each pad 12 of the semiconductor chip 10 caused by
dipping the semiconductor chip 10 into the solution can be
prevented by thus forming a protective film. Specifically,
treatment for each pad 12 such as deposition of a metal by
electroless plating can be more uniform.
[0143] It is preferable to eliminate light when dipping the
semiconductor chip 10 into a desired solution. This prevents the
occurrence of potential changes in each pad 12 of the semiconductor
chip 10.
[0144] Bumps 34 including the first and second metal layers 30 and
32 can be formed in this manner, as shown in FIG. 4C. Brazing
materials 40 may be further applied to the second metal layers 32,
as shown in FIG. 4C. The soldering or brazing materials 40 are
applied to each second metal layer 32. The soldering or brazing
materials 40 may be solder. For example, solder balls (soldering or
brazing materials 40) may be formed on the bumps 34 by dipping the
upper surface of the bumps 34 (part of the second metal layers 32)
into a solder bath. Since solder readily adheres to the gold layers
(second metal layers 32), solder (soldering or brazing materials
40) can be easily applied to the bumps 34. Solder may be formed
using a material containing tin and silver, for example. The height
of the solder balls (soldering or brazing materials 40) is not
limited. For example, the height of the solder balls may be about
15 .mu.m. In the case of applying the soldering or brazing
materials 40 to the semiconductor chip 10, the first and second
metal layers 30 and 32 and the soldering or brazing material 40 may
be collectively referred to as a bump.
[0145] FIG. 5 is a lateral cross-sectional view showing the bumps
34 (first and second metal layers 30 and 32) parallel to the plan
view of the semiconductor chip 10. At least one depression 36
(region for receiving soldering or brazing materials 40) is formed
on the side of the bumps 34, as shown in FIG. 5. Specifically, part
of the first metal layers 30 is made concave by the projecting
sections 24 (see FIG. 2) of the resist layer 20 by forming the
first metal layers 30 conforming to the shape of the through-holes
22. The second metal layers 32 are formed conforming to the shape
of the first metal layers 30. The depressions of the first metal
layers 30 are formed as the depressions 36 of the bumps 34.
[0146] This allows the soldering or brazing materials 40 to flow
into the depressions 36 of the bumps 34 when allowing the soldering
or brazing materials 40 to melt on the bumps 34. Since the
depressions 36 are formed toward the inside of the bumps 34, the
soldering or brazing materials 40 can be absorbed into the inside
the bumps 34. This prevents part of the soldering or brazing
materials 40 flowing out from the bumps 34 upon melting from
spreading in the direction parallel to the surface of the
semiconductor chip 10 (lateral direction), whereby the soldering or
brazing materials 40 can be absorbed in the direction of the height
of the bumps 34 (vertical direction) Therefore, even if each pad 12
is formed at a fine pitch, the soldering or brazing materials 40
can be used without allowing the soldering or brazing materials 40
to flow onto the adjacent pads 12, specifically, without causing a
short circuit to occur.
[0147] The depressions 36 of the bumps 34 may be formed so that the
peak of a triangle faces the center, as shown in FIG. 5. The
depressions 36 of the bumps 34 may be formed in the shape of a
quadrangle or a semicircle toward the center of the bumps 34. The
depressions 36 may be formed in other shapes. In the case where one
side of the bumps 34 is about 20 .mu.m and the pitch between each
pad 12 is about 40 .mu.m in a plan view of the semiconductor chip
10, the depressions 36 of the bumps 34 may be formed at a depth of
about 5 .mu.m from the end sections toward the center. This enables
the soldering or brazing materials 40 to be absorbed
effectively.
[0148] Differing from the example shown in FIG. 5, the depressions
36 of the bumps 34 may be formed only on the sides of the bumps 34
facing the adjacent pads 12 (bumps 34). For example, in the case
where the pads 12 are formed in one row in the end sections of the
semiconductor chip 10, the depressions 36 may be formed only on the
sides of the bumps 34 on each pad 12 facing both adjacent pads 12.
This prevents the soldering or brazing materials 40 from spreading
in the directions of the adjacent pads 12, thereby preventing
occurrence of a short circuit between the pads 12. In the case
where each pad 12 is formed in a matrix, for example, the
depressions 36 are preferably formed on all sides of the bumps
34.
[0149] FIGS. 6A to 6C are views showing a method for forming bumps
according to a modification example of the present embodiment. This
modification example differs from the above-described embodiment as
to the structure of second metal layers 33.
[0150] The second metal layers 33 are formed in the through-holes
22 formed in the resist layer 20, as shown in FIG. 6A.
Specifically, the second metal layers 33 are formed on the upper
surface of the first metal layers 30 without removing the resist
layer 20. At least the surface of the second metal layers 33 may be
formed using a material containing gold. Gold layers (second metal
layers 33) may be formed to a thickness of about 0.1 .mu.m. The
second metal layers 33 may be formed by electroless plating. Other
formation method and structure of the second metal layers 33 are
the same as described above.
[0151] After forming the second metal layers 33, the resist layer
20 is removed, as shown in FIG. 6B. The first and second metal
layers 30 and 33 are formed conforming to the shape of the
through-holes 22.
[0152] Bumps 35 in which the second metal layers 33 are formed on
the upper surface of the first metal layers 30 are formed in this
manner, as shown in FIG. 6C. In other words, the bumps 35 include
the gold layers (second metal layers 33) only on the upper surface
thereof, for example. This enables solder balls (soldering or
brazing materials 40) to be formed only on the upper surface of the
bumps 35 by dipping the bumps 35 into a solder bath, for example.
Specifically, allowing no gold layer (second metal layer 33) to be
formed on the side of the bumps 35 more reliably prevents the
solder (soldering or brazing material 40) from spreading in the
lateral direction from the side of the bumps 35 upon melting.
[0153] In the above example, the bumps 34 are formed using the same
resist layer 20 used to allow the insulating film 14 to expose each
pad 12. Differing from this example, the bumps 34 may be formed by
forming another resist layer after removing the resist layer. In
this case, through-holes in the resist layer for forming openings
in the insulating film 14 which is formed first may be in the shape
of either a square or a circle having no depressions. The bumps 34
having the depressions 36 can be formed by forming a resist layer
for forming the metal layers (first metal layer 30, for example),
which is formed later, so as to have the through-holes 22 formed
therein.
[0154] According to the method for forming bumps of the present
embodiment, the metal layers (bumps 34) are formed into a specific
shape conforming to the shape of the through-holes 22. The metal
layers (bumps 34) have regions for receiving the soldering or
brazing materials 40. This prevents the soldering or brazing
materials 40 from spreading outside the metal layers (bumps 34) by
allowing the soldering or brazing materials 40 to flow into these
regions of the metal layers (bumps 34). Specifically, the soldering
or brazing materials 40 melted on the metal layers (bumps 34) can
be prevented from flowing onto the adjacent pads 12, for example.
Therefore, the yield in the fabrication can be increased by
preventing occurrence of a short circuit between the pads 12.
[0155] In the case where the pads 12 are formed using a material
containing copper, when forming nickel layers (first metal layers
30) on copper, for example, a solution containing a reducing agent
such as palladium is applied to the pads 12 and an electroless
nickel solution is then applied, thereby forming the nickel layers
(first metal layers 30) with palladium as nuclei.
[0156] The above metals and solutions are only examples. The
present embodiment is not limited thereto. For example, copper may
be used as a metal used for electroless plating.
[0157] A method of fabricating a semiconductor device according to
the present embodiment includes a step of bonding the metal layers
(first and second metal layers 30 and 32) connected to a plurality
of pads 12 of the semiconductor chip 10 to a plurality of leads
(interconnect pattern 52) through the soldering or brazing
materials 40, as shown in FIG. 7. The metal layers have regions for
receiving the soldering or brazing materials 40. The metal layers
may be the bumps 34 (first and second metal layers 30 and 32) in
which the depressions 36 are formed by the above formation method.
Specifically, the regions for receiving the soldering or brazing
materials 40 correspond to the depressions 36 of the bumps 34.
[0158] Each bump 34 is electrically connected to one of the leads
through the soldering or brazing material 40. The leads may be the
interconnect pattern 52 formed on a substrate 50. In this case, the
semiconductor chip 10 may be bonded face down to the substrate 50.
The bumps 34 may be bonded to the lands of the interconnect pattern
52.
[0159] The melting soldering or brazing materials 40 are absorbed
into the depressions 36 of the bumps 34 when bonding the bumps 34
to the interconnect pattern 52. Specifically, the soldering or
brazing materials 40 are allowed to flow into the depressions 36 of
the bumps 34 so as not to spread to the adjacent pads 12 (bumps
34). In other words, part of the soldering or brazing materials 40
flowing from the bumps 34 upon melting is prevented from spreading
in the direction parallel to the surface of the semiconductor chip
10 (lateral direction) and is absorbed in the direction of the
height of the bumps 34 (vertical direction). This prevents
occurrence of a short circuit between each pad 12, thereby
increasing the yield in the fabrication of the semiconductor
device.
[0160] The soldering or brazing materials 40 may be applied to the
bumps 34 of the semiconductor chip 10, through which the bumps 34
may be bonded to the interconnect pattern 52 (lands) The soldering
or brazing materials 40 may be applied to the interconnect pattern
52 (lands) on the substrate 50. The bumps 34 may be bonded to the
interconnect pattern 52 (lands) due to surface tension of the
soldering or brazing materials 40 during melting.
[0161] The leads may be inner leads in the case where the TAB
technology is applied, or all conductive members bonded through the
soldering or brazing materials 40.
[0162] A semiconductor device according to the present embodiment
includes the semiconductor chip 10 including a plurality of pads
12, the metal layers (bumps 34) connected to each pad 12, and a
plurality of leads (interconnect pattern 52). The metal layers have
regions into which the soldering or brazing materials 40 flow. Each
metal layer is bonded to one of the leads through the soldering or
brazing materials 40. In this case, each metal layer has regions
for receiving the soldering or brazing materials 40. The metal
layers may be the above bumps 34. Part of the soldering or brazing
materials 40 flows into the depressions 36 of the bumps 34. Other
structures are the same as described above. The leads may be the
interconnect pattern 52 formed on the substrate 50.
[0163] External terminals 54 connected to the interconnect pattern
52 may be formed on the substrate 50. For example, the external
terminals 54 which are connected to the interconnect pattern 52
through through-holes (not shown) formed in the substrate 50 may be
formed. The external terminals 54 may be formed by solder balls.
Instead of positively forming the external terminals 54, solder
cream may be applied to the interconnect pattern of the circuit
board, and the semiconductor device may be mounted on the circuit
board due to surface tension during melting.
[0164] According to the present embodiment, the soldering or
brazing materials 40 can be prevented from spreading outside the
metal layers by allowing part of the soldering or brazing materials
40 to flow into the regions (depressions 36) of the metal layers
(bumps 34). Specifically, the soldering or brazing materials 40
melted on the metal layers can be prevented from flowing onto the
adjacent pads 12. Therefore, a highly reliable semiconductor device
can be provided by preventing occurrence of a short circuit between
the pads 12.
[0165] (Second Embodiment)
[0166] FIGS. 8 to 11 are views showing a method for forming bumps
according to a second embodiment to which the present invention is
applied. The present embodiment differs from the first embodiment
as to the formation method and the structure of metal layers (bumps
74). The description relating to the first embodiment may be
applied to the following embodiment as far as possible.
[0167] A resist layer 60 is formed on the semiconductor chip 10, as
shown in FIGS. 8 and 9A. The resist layer 60 has a plurality of
through-holes 62, at least part (part or all) of which is
superposed on one pad 12. A plurality of through-holes 62 may be
disposed inside the pads 12 or located outside of the circumference
of the pads 12. The resist layer 60 is formed while allowing a
portion 64 to remain inside the pads 12 in order to form a
plurality of through-holes 62. The shape of the through-holes 62
may be either rectangular as shown in FIG. 8 or circular without
specific limitations. The portion 64 of the resist layer 60 is
formed to provide a region 76 between metal layers (first and
second metal layers 70 and 72) as described later. The portion 64
is formed to a size so as to allow the soldering or brazing
material 40 to flow into the region 76. The arrangement and the
number of through-holes 62 may be appropriately determined taking
into consideration the size which allows the soldering or brazing
material 40 to flow into the region 76.
[0168] Part of the insulating film 14 is removed through a
plurality of through-holes 62 in the resist layer 60, as shown in
FIG. 9B. Specifically, a plurality of openings 66 is formed in the
insulating film 14 on each pad 12 using the through-holes 62. In
other words, a plurality of exposed areas is formed on each pad 12.
This enables a plurality of bumps to be formed on each pad 12 so as
to be connected to the pads 12 . The size of a plurality of exposed
areas in each pad 12 is not limited. For example, the exposed area
may be in the shape of a square with a side length of about 20
pm.
[0169] First and second metal layers 70 and 72 are formed as shown
in FIG. 9C. For example, the first metal layers 70 maybe formed in
each through-hole 62. The second metal layers 72 may be formed so
as to cover the surface of the first metal layers 70 after removing
the resist layer 60. Bumps 74 including the first and second metal
layers 70 and 72 are formed in this manner. A plurality of bumps 74
can be formed on each pad 12 by forming a plurality of
through-holes 62 for each pad 12.
[0170] The region 76 is formed between the adjacent bumps 74 on
each pad 12, as shown in FIG. 9C. Specifically, the regions 76
between the bumps 74 are formed by allowing the portions 64 of the
resist layer 60 to remain. In the case of forming the second metal
layers 72 after removing the resist layer 60, it is preferable to
form thin second metal layers 72 so that the regions 76 are not
filled with the second metal layers 72.
[0171] The formation method and other structures of the first and
second metal layers 70 and 72 may be the same as described above.
In the present embodiment, the first metal layers 70 may be formed
so that at least one depression (see FIG. 5) is formed on the side
of the first metal layers 70, as illustrated for the above
embodiment.
[0172] Brazing materials 80 may be applied to the bumps 74. The
soldering or brazing materials 80 may be solder as described above.
Solder may be applied to each bump 74 by dipping the bumps 74 into
a solder bath, for example. The amount of solder applied to the
bumps 74 can be decreased by forming a plurality of bumps 74 on
each pad 12, thereby preventing an excess amount of solder from
flowing out.
[0173] FIG. 10 is a lateral cross-sectional view showing the bumps
74 (first and second metal layers 70 and 72) parallel to a plan
view of the semiconductor chip 10. The regions 76 formed between
the adjacent bumps 74 on each pad 12 are of a size so as to allow
the soldering or brazing materials 80 to flow into the regions 76.
The regions 76 may be appropriately determined by the number and
arrangement of the through-holes 62 formed in the resist layer
60.
[0174] According to the present embodiment, the soldering or
brazing materials 80 can be prevented from spreading outside the
bumps 74 when allowing the soldering or brazing materials 80 to
melt on the bumps 74. Specifically, the regions 76 formed between
the adjacent bumps 74 on each pad 12 absorb part of the soldering
or brazing materials 80 flowing outside the bumps 74 upon melting.
Specifically, the melted soldering or brazing materials 80 can be
prevented from spreading in the direction parallel to the surface
of the semiconductor chip 10 (lateral direction), and are absorbed
in the direction of the thickness of the bumps 74 (vertical
direction).
[0175] FIG. 11 is a view showing a method for forming bumps
according to a modification example of the present embodiment.
Second metal layers 73 may be formed on the upper surface of the
first metal layers 70, as shown in FIG. 11. The second metal layers
73 may be formed using a plurality of through-holes 62 in the
resist layer 60. Allowing no gold layer (second metal layer 73) to
be formed on the side of the bumps 75 more reliably prevents the
melted solder from spreading from the side of the bumps 75 in the
lateral direction.
[0176] (Third Embodiment)
[0177] FIGS. 12A and 12B are views showing a method for forming
bumps according to a third embodiment to which the present
invention is applied. The present embodiment differs from the above
embodiments as to the formation method and structure of metal
layers (bumps 100).
[0178] A resist layer 90 is formed on the semiconductor chip 10, as
shown in FIG. 12A. The resist layer 90 is provided with
through-holes 92, with at least part (part or all) of each
superposed on the pads 12. The through-holes 92 are formed in the
resist layer 90 so that part of the resist layer 90 remains at the
center of the through-holes 92 in a plan view of the semiconductor
chip 10. For example, the through-holes 92 are formed in the shape
of a ring which encloses the center (portion 94 of the resist layer
90).
[0179] The through-holes 92 may be formed in the shape of either a
square ring or a circular ring. The portion 94 of the resist layer
90 forms a region (depression 102) of bumps 100 (including first
and second metal layers) formed later. The portion 94 of the resist
layer 90 is preferably formed small enough to allow the bumps 100
to be securely connected to the pads 12, but large enough to allow
the soldering or brazing materials to flow into the depressions 102
of the bump 100.
[0180] FIG. 12B is a lateral cross-sectional view showing the bumps
100 parallel to a plan view of the semiconductor chip 10. The bumps
100 are formed into the shape of a ring so that the depression 102
is formed at the center in a plan view of the semiconductor chip
10. The depressions 102 are formed in the direction of the height
of the bumps 100. Part of the pads 12 may be exposed at the bottom
of the depressions 102. The shape of the depressions 102 may be
either circular or square. Either one or a plurality of depressions
102 may be formed.
[0181] According to the present embodiment, part of the soldering
or brazing materials flowing outside the bumps 100 upon melting can
be absorbed into the depressions 102 of the bumps 100.
Specifically, the melted soldering or brazing materials can be
absorbed in the direction of the height of the bumps 100 (vertical
direction) by preventing the soldering or brazing materials from
spreading in the direction parallel to the surface of the
semiconductor chip 10 (lateral direction) Moreover, the melted
soldering or brazing materials can be prevented from flowing
outside in one direction by forming the depressions 102 at the
center of the bumps 100. Specifically, an excess amount of
soldering or brazing materials can be absorbed uniformly.
[0182] Any of the above embodiments may be applied to the present
embodiment. Specifically, the bumps 100 may have at least one
depression on the side in the present embodiment. A plurality of
bumps 100 may be formed on each pad 12. Bumps may be formed by
combining these structures.
[0183] FIG. 13 shows a circuit board 200 equipped with a
semiconductor device 1 according to the present embodiment. The
circuit board 200 is generally formed using an organic substrate
such as a glass epoxy substrate or a polyimide film or a glass
substrate such as a liquid crystal display substrate. An
interconnect pattern formed of copper or the like is formed on the
circuit board 200 so as to form a desired circuit. The interconnect
pattern and the semiconductor device 1 are electrically connected
by mechanically connecting the interconnect pattern with the
external terminals 54 of the semiconductor device 1.
[0184] FIGS. 14 and 15 respectively illustrate a notebook-type
personal computer 300 and a portable telephone 400 as examples of
an electronic instrument equipped with the semiconductor device 1
to which the present invention is applied.
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