U.S. patent application number 09/850920 was filed with the patent office on 2002-03-14 for deuterium treatment of semiconductor devices.
Invention is credited to Hess, Karl, Lee, Jinju, Lyding, Joseph W..
Application Number | 20020031920 09/850920 |
Document ID | / |
Family ID | 27361464 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020031920 |
Kind Code |
A1 |
Lyding, Joseph W. ; et
al. |
March 14, 2002 |
Deuterium treatment of semiconductor devices
Abstract
Semiconductor device annealing process with deuterium at
superatmospheric pressures to improve reduction of the effects of
hot carrier stress during device operation, and devices produced
thereby.
Inventors: |
Lyding, Joseph W.;
(Champaign, IL) ; Hess, Karl; (Champaign, IL)
; Lee, Jinju; (Urbana, IL) |
Correspondence
Address: |
SHARP COMFORT & MERRETT, PC
13355 NOEL ROAD
SUITE 1340
DALLAS
TX
75240
US
|
Family ID: |
27361464 |
Appl. No.: |
09/850920 |
Filed: |
May 7, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09850920 |
May 7, 2001 |
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09518802 |
Mar 3, 2000 |
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09518802 |
Mar 3, 2000 |
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09020565 |
Jan 16, 1998 |
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6147014 |
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09020565 |
Jan 16, 1998 |
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PCT/US97/00629 |
Jan 16, 1997 |
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PCT/US97/00629 |
Jan 16, 1997 |
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08586411 |
Jan 16, 1996 |
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5872387 |
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Current U.S.
Class: |
438/795 ;
257/410; 257/E21.194; 257/E21.212; 257/E21.324; 438/798 |
Current CPC
Class: |
H01L 21/28176 20130101;
H01L 21/3003 20130101; Y10S 438/909 20130101; H01L 29/518 20130101;
H01L 21/324 20130101; H01L 29/513 20130101 |
Class at
Publication: |
438/795 ;
257/410; 438/798 |
International
Class: |
H01L 029/76; H01L
021/336; H01L 029/94; H01L 031/062; H01L 031/113; H01L 031/119;
H01L 021/324; H01L 021/42; H01L 021/477 |
Goverment Interests
[0002] This invention was made with Government support under
Contract No. N00014-98-1-0604 awarded by Office of Naval Research.
The Government has certain rights in the invention.
Claims
1. A process for treating a semiconductor device including a
semiconductor region and an insulating layer having an interface
with the semiconductor region, comprising the steps of annealing
said semiconductor device during manufacture thereof, in an ambient
including deuterium wherein said deuterium has a partial pressure
in excess of atmospheric pressure, to form a concentration of
deuterium at the interface between said semiconductor region and
said insulating layer region effective to substantially reduce
degradation of said device associated with hot carrier stress.
2. A process according to claim 1, wherein said deuterium partial
pressure is between about 2 atmospheres and 15 atmospheres and the
annealing is carried out at a temperature between about 150.degree.
C. and 600.degree. C.
3. A process according to claim 2, wherein the annealing process is
carried out for a period in excess of 5 minutes.
4. A process according to claim 3, wherein the annealing period is
between 30 minutes and 3 hours.
5. A process for treating a semiconductor device including a
semiconductor region and an insulating layer having an interface
with the semiconductor region, comprising the steps of exposing
said semiconductor device during manufacture thereof to an ambient
including deuterium wherein said deuterium has a partial pressure
between about 2 atmospheres to about 15 atmospheres, at a
temperature above about 150.degree. C. to form a concentration of
deuterium greater than 10.sup.16 atoms/cc at the interface between
said semiconductor region and said insulating layer.
6. A process for treating a semiconductor device including a
semiconductor region and an insulating layer having an interface
with the semiconductor region, comprising the steps of annealing
said semiconductor device during manufacture thereof in an ambient
including deuterium wherein said deuterium has a partial pressure
in excess of atmospheric pressure up to about 10 atmospheres, at a
temperature above about 350.degree. C. to form a concentration of
deuterium at the interface between said semiconductor region and
said insulating layer.
7. A process according to claim 6, wherein said deuterium partial
pressure is between about 2 atmospheres and about 6
atmospheres.
8. A process according to claim 6, wherein said temperature is in
the approximate range 350.degree. C. to 450.degree. C.
9. A process according to claim 6, wherein said annealing is for a
period of about 1-3 hours.
10. A process according to claim 6, wherein said annealing
treatment is the final thermal processing step in the manufacturing
process for the device.
11. A process for treating a semiconductor device including at
least one insulating layer overlying a semiconductor region,
comprising the steps of exposing said semiconductor device during
manufacture thereof to an ambient including deuterium wherein said
deuterium has a partial pressure in excess of atmospheric pressure,
at a temperature above about 300.degree. C. to form a concentration
of deuterium in the insulating layer of at least 10.sup.18
atoms/cc.
12. A process for treating an insulated gate field effect
transistor device during manufacture thereof to form a
concentration of deuterium at an interface between a gate insulator
and a channel region of said device, comprising annealing the
device in a superatmospheric pressure deuterium ambient at a
temperature in the range 300.degree. C. to 600.degree. C. for a
time sufficient to provide a deuterium concentration of at least
10.sup.18 atoms/cc at said interface.
13. A process according to claim 12, wherein said deuterium partial
pressure is between about 2 atmospheres and about 6
atmospheres.
14. A process according to claim 12, wherein said temperature is in
the approximate range 350.degree. C. to 450.degree. C.
15. A process according to claim 12, wherein said annealing is for
a period of about 1-3 hours.
16. A process according to claim 12, wherein said annealing
treatment is the final thermal processing step in the manufacturing
process for the device.
17. A process according to claim 12, wherein said annealing
treatment is carried out contact formation and interconnect
metallization.
18. A process according to claim 12, wherein said deuterium
concentration is in the range 10.sup.18 to 10.sup.21 atoms/cc.
19. A process for treating an insulated gate field effect
transistor device including a channel region extending between
source and drain regions, an insulating layer forming an interface
with said channel region, and contacts to said source and drain
regions and on said gate insulator layer, comprising, subsequent to
formation of said source, drain and gate contacts, annealing the
device in an ambient including deuterium at a partial pressure
between about 2 and 10 atmospheres, at a temperature between about
300.degree. C. and 600.degree. C. for a period between about 30
minutes and three hours, to form a concentration of deuterium at
said interface region.
20. A process for treating an insulated gate field effect
transistor device including a channel region extending between
source and drain regions, an insulating layer forming an interface
with said channel region, and contacts to said source and drain
regions and on said gate insulator layer, comprising, subsequent to
formation of said source, drain and gate contacts, annealing the
device in an ambient including deuterium at a partial pressure
between about 2 and 6 atmospheres, at a temperature between about
350.degree. C. and 450.degree. C. to form a concentration of
deuterium at said interface region effective to substantially
reduce degradation of said device associated with hot carrier
stress.
21. A process according to claim 20, wherein said annealing step
comprises the final thermal processing step in manufacture of the
device.
22. A process according to claim 20, wherein the annealing ambient
is 100% deuterium.
23. A process for treating an insulated gate field effect
transistor device including a channel region extending between
source and drain regions, an insulating layer forming an interface
with said channel region, contacts to said source and drain regions
and on said gate insulator layer, insulating sidewall spacers
adjacent to said gate contact, and an insulating barrier cap over
said gate contact, comprising, subsequent to formation of said
source, drain and gate contacts, of said sidewall spacers and of
said insulating barrier cap, annealing the device in an ambient
including deuterium at a partial pressure between about 2 and 10
atmospheres, at a temperature between about 300.degree. C. and
600.degree. C. for a period between from 30 minutes to about three
hours, to form a concentration of deuterium at said interface
region effective to substantially reduce degradation of said device
associated with hot carrier stress.
24. A process according to claim 23, wherein said deuterium
concentration is in the range 10.sup.18 to 10.sup.21 atoms/cc.
25. A semiconductor device including a semiconductor region and an
insulating layer having an interface with the semiconductor region,
including a concentration of deuterium in excess of about 10.sup.18
atoms/cc at the interface between said semiconductor region and
said insulating layer region, said deuterium concentration
effective to substantially reduce degradation of said device
associated with hot carrier stress.
26. A semiconductor device according to claim 25, wherein said
deuterium concentration is in the range 10.sup.18 to 10.sup.21
atoms/cc.
27. An insulated gate field effect transistor device including a
channel region extending between source and drain regions, an
insulating layer forming an interface with said channel region, and
contacts to said source and drain regions and on said gate
insulator layer, including a concentration of deuterium in excess
of about 10.sup.18 atoms/cc at said interface region effective to
substantially reduce degradation of said device associated with hot
carrier stress.
28. An insulated gate field effect device according to claim 27,
wherein said deuterium concentration is in the range 10.sup.18 to
10.sup.21 atoms/cc.
29 A semiconductor device including a semiconductor region and an
insulating layer having an interface with conductive layer,
including a concentration of deuterium in excess of about 10.sup.18
atoms/cc in said insulating layer.
30. A semiconductor device according to claim 29, wherein said
deuterium concentration is in the range 10.sup.18 to 10.sup.21
atoms/cc.
Description
[0001] This application is a continuation-in-part of application
Ser. No. 09/518,802 filed Mar. 3, 2000 which is a divisional of
application Ser. No. 09/020,565 filed Jan. 16,1998 (U.S. Pat. No.
6,147,014 which is a continuation of international application
PCT/US97/00629 filed Jan. 16, 1997 which is a continuation-in-part
of application Ser. No. 08/586,411 filed Jan. 16, 1996 (U.S. Pat.
No. 5,872,387) all of which are hereby incorporated herein by
reference as if each had been individually incorporated by
reference and fully set forth herein.
BACKGROUND OF THE INVENTION
[0003] This invention relates to treating semiconductor devices
with deuterium to improve operating characteristics, and in
particular to improve hot-carrier reliability of transistors, and
to semiconductor devices resulting from such treatment.
[0004] Degradation of operating performance of semiconductor
devices (for example CMOS transistor device structures) due to hot
carrier effects attributed to hydrogen desorption at an oxide
(typically silicon oxide)/semiconductor(typically silicon)
interface has been recognized and studied for many years. One
proposed solution has been to subject such devices to hydrogen
(H.sub.2) annealing but in practice this has been recognized as
ineffective. A more effective approach to alleviating the problem
has been to include a deuterium annealing step at a convenient
point in the device fabrication process manufacturing process,
before or subsequent to contact formation and interconnects
(metallization). Known deuterium annealing processes include, for
example, those disclosed by U.S. Pat. No. 5,872,387, in J. W.
Lyding, K. Hess and I. C. Kizilyalli, "Reduction of Hot Electron
Degradation in Metal Oxide Semicondutor Transistors by Deuterium
Processing," Appl. Phys. Lett. 68, p. 2526 (1996), and in I. C.
Kizilyalli, J. W. Lyding, and K. Hess, "Deuterium post-metal
annealing of MOSFETs for improved hot carrier reliability," IEEE
Electron Device Lett., vol 18, p. 81, March 1997, all of which,
together with the publications to which subsequent reference is
made herein, are hereby incorporated herein by reference as if each
had been individually incorporated by reference and fully set forth
herein.
[0005] While the beneficial impact of deuterium annealing on
semiconductor device operating lifetime has been quite dramatic,
and has improved, state of the art semiconductor devices remain
prone to hot carrier problems and further improvements in
processing to further alleviate this problem are desirable.
SUMMARY OF THE INVENTION
[0006] In one aspect, the present invention provides a process for
manufacturing a semiconductor device including a semiconductor
region and an insulating layer having an interface with the
semiconductor region, comprising the steps of exposing the
semiconductor device to an ambient including deuterium wherein said
deuterium has a partial pressure in excess of atmospheric pressure
to form a concentration of deuterium at the interface between said
semiconductor region and said insulating layer. The deuterium
annealing process may be carried out at any convenient point during
the fabrication process but it is preferred to implement it after
completion of all high temperature processing steps, i.e. typically
after contact formation, to reduce deuterium dissipation which
otherwise may occur. The invention has been found to result in
significant advantages in increasing lifetime of semiconductor
devices subject to hot carrier stress during operation, as compared
to hydrogen annealing and deuterium annealing at atmospheric
pressure.
[0007] In another aspect, the present invention provides a process
for manufacturing a semiconductor device including at least one
insulating layer overlying a semiconductor region, comprising the
steps of exposing said semiconductor device to an ambient including
deuterium wherein said deuterium has a partial pressure in excess
of atmospheric pressure. This aspect of the invention may be
utilized to provide a high concentration of deuterium in interlevel
dielectric layers used to insulate adjacent metal circuitry layers
in semiconductor devices.
[0008] While a 100% deuterium ambient is preferred for the
annealing process, other ambients may be used, for example a
nitrogen/deuterium ambient, provided the deuterium partial pressure
is above one atmospheric pressure. Thus, for example, a 50%
deuterium 50% nitrogen ambient at 10 atmospheres may be used,
resulting in a deuterium partial pressure of 5 atmospheres.
[0009] It is contemplated that deuterium pressures up to about 100
atmospheres may be technologically significant but for commercial
purposes, pressures above about 15 atmospheres are less likely to
be of interest. At deuterium pressures above about 10 atmospheres,
additional interface defects may arise under some temperature
conuitions so that, for commercially practical purposes, deuterium
pressures not exceeding about 10 atmospheres are regarded as
preferable in practicing the invention. For any particular set of
process parameters, the deuterium concentration resulting from the
annealing process will increase with increasing deuterium
pressure.
[0010] A process according to the invention may be carried out at
temperatures of about 150.degree. C. and above, typically up to
about 600.degree. C. and advantageously over the approximate range
350.degree. C.-450.degree. C. One advantage of the invention is
that deuterium annealing carried out at deuterium pressures in
excess of one atmosphere permit a reduction in processing
temperature while resulting in equivalent benefits associated with
deuterium annealing carried out at one atmosphere. For example,
deuterium annealing at about 350.degree. C. carried out in
accordance with the invention has been found to produce similar
benefits as deuterium processing at one atmosphere carried out in a
temperature range of about 400.degree. C. to 450.degree. C.
[0011] A deuterium annealing process embodying the invention may
typically be carried out over a period in excess of about 5
minutes, typically from about 10 minutes, preferably 30 minutes, to
about 3 hours. The particular combination of deuterium
superatmospheric pressure, annealing temperature and annealing time
may be empirically determined and be affected, for example, by the
particular device structure and the deuterium concentration desired
at the target location. Increasing deuterium pressure permits a
shorter annealing time to achieve a particular deuterium
concentration at the target location. The deuterium concentration
at the target location should be at least 10.sup.16 atoms/cc,
desirably is in excess of about 10.sup.18 atoms/cc, and
advantageously may be in the range 10.sup.19 to 10.sup.21
atoms/cc.
[0012] One problem related to carrying out post metal deuterium
annealing is that current MOS technologies often employ silicon
nitride sidewall spacers adjacent the gate insulator, and sometimes
a barrier layer, such as a silicon nitride cap, is formed over the
gate and other contacts, through which the deuterium has to
penetrate. It has been found that an annealing process embodying
the invention, using deuterium at superatmospheric pressure, is
effective in improving deuterium penetration of such sidewall
spacers and barrier layers. Consequently, the employment of a
deuterium annealing process in accordance with the invention
becomes more feasible as a final thermal process in semiconductor
device fabrication which is advantageous in minimizing deuterium
dissipation. Reference to a thermal process is intended to include
any processing involving one or more cycles involving heating
followed by cooling, e.g. deposition processing, which typically
may occur at temperatures around 300.degree. C. and upwards, in
part dependent on the processing time involved.
[0013] The invention has particular application in processing CMOS
structures in order to introduce a concentration of deuterium at
the gate oxide/silicon interface, and advantageously is carried out
after contact formation as the final thermal processing step.
Suitably, the deuterium annealing process is carried out in a 100%
deuterium ambient at a superatmospheric pressure up to about 6
atmospheres. Annealing temperatures in the approximate range
350.degree. C. to 600.degree. C. may conveniently be used but
temperatures toward the lower end of this range, suitably
350.degree. C., are preferred and annealing periods may typically
range from about 30 minutes to about 3 hours.
[0014] Deuterium processing of CMOS transistors in accordance with
the invention has been found to be advantageous in facilitating
incorporation of higher concentrations of deuterium at the gate
silicon oxide/silicon interface, resulting in greater lifetime
improvement in comparison to ambient (atmospheric pressure)
deuterium annealing. It has been discovered that high pressure
deuterium carried out in accordance with the invention also
advantageously not only can increase the magnitude of the
improvement but also can shorten the annealing time required to
produce a given concentration of deuterium at the gate
oxide/silicon interface.
[0015] As reported in J. Lee, K. Cheng, Z. Chen, K. Hess, J. W.
Lyding, Y-K Kim, H-S Lee, Y-W kim and K-P suh, Application of High
Pressure Deuterium Annealing for Improving the Hot carrier
reliability of CMOS Transistors," IEEE Elec. Dev. Lett., 21, p.221
(2000), the efficacy of annealing in a superatmospheric deuterium
ambient has been demonstrated in fabrication of complementary
metal-oxide-semiconductor (CMOS) transistors where it has been
found that a greater than tenfold increase in device reliability
lifetime can be achieved compared to deuterium processing at
ambient pressure as reported in J. W. Lyding, Karl Hess, and I. C.
Kizilyalli, "Reduction of Hot Electron Degradation in Metal Oxide
Semiconductor Transistors by Deuterium Processing," Appl. Phys.
Lett. 68, 2526 (1996). Furthermore, it is possible to significantly
lower processing temperatures and still achieve a large lifetime
improvement by processing at high deuterium pressure. This is
particularly significant in view of the low thermal budgets of the
latest CMOS technologies. High pressure deuterium processing in
accordance with the invention appears likely to be beneficial for
MOS technologies such as n-channel (NMOS) and p-channel (PMOS)
devices, flash memory devices, the drive transistor and storage
capacitor in dynamic random access memory (DRAM), static random
access memory (SRAM) transistor, bipolar technologies,
charge-coupled display (CCD) devices, biCMOS technology,
silicon-germanium MOS devices, and compound semiconductor devices
comprised of elements from columns III and V of the periodic table.
High pressure deuterium embodying the invention may be used to
incorporate high concentrations of deuterium in the interlayer
dielectrics used to insulate adjacent metal circuitry layers in
integrated circuits, e.g. microchips employing MOS, particularly
CMOS, technology processing, as there is evidence that deuterium is
beneficial in those locations. Solar cells based on crystalline
silicon, polycrystalline silicon, and amorphous hydrogenated
silicon are also known to benefit from deuterium incorporation and
would therefore be improved by high pressure deuterium processing
in accordance with the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] By way of example, embodiments of the present invention will
be described in greater detail with reference to the accompanying
drawings, in which: FIG. 1 depicts one illustrative metal oxide
semiconductor field effect transistor device structure with respect
to which a process according to the present invention will be
described;
[0017] FIG. 2 is a graph showing percentage change in
transconductance versus time under different biasing conditions
(drain voltage V.sub.d) of a MOSFET device annealed by a process
embodying the invention;
[0018] FIG. 3 is a log-log graph plotting device lifetime versus
substrate current for devices annealed by a process according to an
embodiment of the invention and for a comparable device subjected
to hydrogen annealing;
[0019] FIG. 4 depicts extrapolated lifetime improvements associated
with MOSFETS annealed under different annealing conditions in
accordance with the invention; and
[0020] FIG. 5 depicts SIMS plots showing deuterium concentration
across the gate oxide layer and channel of a MOSFET device annealed
in accordance with the invention using different annealing
parameters.
DETAILED DESCRIPTION OF THE INVENTION
[0021] The present invention may be practised using a p- or n-type
substrate which may, for example, be doped or undoped crystalline
silicon or amorphous silicon, gallium arsenide, or gallium aluminum
arsenide. However, the following embodiments will be described with
reference to use of a silicon substrate.
[0022] FIG. 1 is a diagram of an illustrative MOSFET, part of a
CMOS structure, to which the present invention can be applied. The
device 11 includes a silicon substrate 12 including at a surface of
the substrate a drain 13, a source 14 and a channel 15 extending
between them. A field oxide or other electrically insulative
(dielectric) layer 16 is also provided adjacent the drain and
source regions, as is a gate insulator (dielectric) 17 overlying
the channel region and partly overlapping the drain and source
regions. The drain and source regions 13 and 14 are n+ doped for an
n-channel (p substrate) MOSFET device and p+ doped for a p-channel
(n substrate) MOSFET device. Insulators 16 and 17 can be formed of
a single layer or of multiple layers, and can include for instance
an oxide and/or nitride of silicon (for convenience referred to as
SiON), e.g. a silicon dioxide, silicon nitride, silicon oxy
nitride, or silicon-rich oxide film. Insulating gate sidewall
spacers 22 are formed adjacent the gate contact and an insulating
barrier layer or cap 21 is formed over the gate contact 20. A SiON
material, typically silicon nitride, may be used for the sidewall
spacers 21 and cap 22. The device 11 also includes conductive
contacts 18, 19 and 20 for the drain 13, source 14 and gate
insulator 17, which can include one or more conductive materials
such as metals, e.g. aluminum, gold, or copper; metal silicides
such as tungsten, molybdenum, tantalum or titanium silicide, or
combinations thereof; polysilicon; and titanium nitride. In an
integrated circuit structure, the MOSFET device would be connected
to other circuit components by one or more levels of interconnects
separated by insulator layers; for example, first level
interconnects 24 on insulator layer 25 are shown from the drain and
source contacts 18, 19 in FIG. 1. The illustrated device is typical
of a MOSFET employing a polysilicon gate contact with sidewall
spacers and an overlying barrier layer or cap. Alternatively, the
sidewall spacers 22 and/or the cap 21 could be formed as disclosed
in U.S. Pat. No. 6,147,014. The general fabrication techniques for
semiconductor devices of involved in carrying out the invention can
be conventional, including conventional growth or deposition and of
various semiconductor, insulating and conductive layers and doping
operations employing appropriate masks.
[0023] In accordance with the invention, the semiconductor device
is annealed in deuterium at superatmospheric pressure at a
convenient point during fabrication but preferably after the drain,
source and gate contacts 19, 18 and 20, the barrier cap 21, and
interconnect metallization have been completed, and advantageously
is carried out as the final thermal processing step. This annealing
process results in a concentration of deuterium in the gate
insulator layer and particularly at the gate insulator/channel
interface and a significant increase in the level of reduction of
hot carrier stress effects during operation of the device, thereby
further increasing the lifetime of the device as compared with
known hydrogen annealing or deuterium annealing at normal
atmospheric pressure.
[0024] In preferred embodiments of the invention, used in
processing an MOSFET device as depicted in FIG. 1, the deuterium
annealing process is typically carried out at superatmospheric
pressures from about 2 atmospheres up to about 6 atmospheres at a
temperature of about 450.degree. C. However, the superatmospheric
pressure annealing process may be carried out a lower temperatures,
for example from about 150.degree. C. upwards and it has been
discovered that a superatmospheric annealing process in accordance
with the invention at 350.degree. C. can yield performance
improvements equivalent to those obtained in a carrying out a
deuterium annealing process at atmospheric pressure at a
temperature of 450.degree. C. using otherwise identical process
parameters. Time periods for the annealing process are dependent on
several factors, including the desired deuterium concentration at
the semiconductor(silicon)/gate oxide(silicon dioxide) interface
between the semiconductor (silicon) channel 15 and the gate
insulator (silicon dioxide) 17, the anneal temperature and the
superatmospheric pressure. Generally, increasing deuterium pressure
requires a shorter anneal time at a given temperature. Preferably,
the deuterium concentration at the channel/gate oxide interface is
at least 10.sup.18 atoms/cc and advantageously may be in the range
10.sup.18 to 10.sup.21 atoms/cc. A superatmospheric pressure
annealing process embodying the invention is preferably carried out
in a 100% deuterium ambient; diluting the deuterium would decrease
the effective deuterium pressure. However, the deuterium may be
mixed with another gas (e.g. nitrogen) provided that in the
mixture, the partial pressure of deuterium is above atmospheric
pressure and equivalent to the desired deuterium pressure. The
superatmospheric pressure deuterium annealing process may be
carried out in a closed (static) pressurized deuterium environment
but preferably the deuterium (or deuterium gas mixture) may be
flowed through the reaction vessel at a suitable rate, e.g. on an
industrial process level at about 100 to 200 liters/hour. The
reaction vessel itself would need to be suitably thick walled and
designed and fabricated to provide effective gas confinement under
the applicable superatmospheric operating conditions.
[0025] The conditioning of the semiconductor device with deuterium
has been found to significantly reduce effects associated with
depassivation of the device by hot-carrier (e.g. hot-electron)
effects. For example, as reported in the Experimental below,
dramatic increases in device lifetime are observed when deuterium
is used to passivate the devices, as compared to hydrogen annealing
at atmospheric pressure (see FIGS. 2 and 3, respectively). These
increases represent practical lifetime improvements by factors of
about 80 to 90, and also make possible the operation of the
semiconductor devices at higher voltages while better resisting
aging due to hot electron effects.
[0026] The invention also can be beneficially practised to form a
concentration of deuterium in an interlevel insulator between
multilevel conductors providing connections between devices in an
integrated circuit, e.g. in an interlevel insulator 25 on which are
formed connections 24 from the source, drain and gate contacts of
the MOS transistor depicted in FIG. 1 to other component
devices(not shown) of the integrated circuit.
[0027] Experimental.
[0028] The devices used in the following examples were fabricated
using currently available 0.35 um 3.3 V CMOS technology
(t.sub.ox=5.5 nm). The wafers were fully processed with four levels
of metallization, nitride sidewall spacers, and SiON capping
layers, prior to annealing in accordance with embodiments of the
present invention. The wafers were subjected to 100% D sintering at
450.degree. C. at several pressures (2 and 6 atm). The annealing
times varied from 10 min to 3 h. One control sample was processed
using a conventional hydrogen forming gas anneal
(H.sub.2:N.sub.2=10:90) at 400.degree. C. for 30 min. As previously
observed, there was no change in the pre-stress electrical
characteristics for devices sintered in deuterium.
[0029] Five devices of a specific annealing condition were
subjected to dc stresses with V.sub.ds=3.5, 3.6, 3.7, 3.8, 3.9,
4.1, and 4.2V and V.sub.gs set to give the maximum substrate
current (I.sub.b,max) Transconductance (G.sub.m), threshold voltage
(V.sub.th), and saturation current (I.sub.d,sat) were monitored at
various times during the entire stress. Lifetimes for each
processing condition were then extracted from the stressed times
showing 100-mV shift in V.sub.th and 10% degradation in G.sub.m and
I.sub.d,sat.
[0030] Deuterium incorporation as a function of pressure was
measured by taking secondary ion mass spectrometry (SIMS) depth
profiles on separate test wafers having 6000 A SiO.sub.2 on top of
Si. D incorporation at the interface was characterized by applying
a 14.5 keV Cs.sup.+ primary ion beam with negative secondary ion
detection in a CAMECA ims-5f system. The secondary ion counts were
converted to concentrations by calculating the relative sensitivity
factors using calibration standards--see J. Lee J. Baker, R.
Wilson, and J. W. Lyding, "SIMS depth profiles of I H and 'H at the
SiO.sub.2/Si interface of deuterium-sintered CMOS devices," in SIMS
XI Proc., 1997, pp. 205-208.
[0031] Results
[0032] During the hot carrier stress, the changes in G.sub.m,
V.sub.th, and I.sub.d,sat were measured and recorded for numerous
biasing conditions. FIG. 2 shows an example of the percentage
change in Gm with four different biasing conditions for CMOS
devices that were sintered at 6 atm for 3 h at 450.degree. C. From
this data, a log(lifetime) versus log(substrate current) graph can
be plotted; the lifetime at a specific substrate current is
extracted by a least squares fit to the measured data. FIG. 3 shows
such a graph for devices that were sintered at 6 atm for 3 h and
for devices sintered in conventional hydrogen forming gas. The
graph clearly shows the lifetime improvement due to the D
annealing. The conventional hydrogen anneal does not improve
reliability lifetime. In fact, it has been observed by many
experiments using wafers from several different manufacturers that
annealing in 100% hydrogen at temperatures up to 480.degree. C. for
several hours at high pressures has no discernible effect on
reliability lifetime. The lifetime improvements as described above,
therefore, can be attributed solely to the presence of deuterium.
The larger slope for the D data in FIG. 3 is consistent with
earlier observations when there is a large isotope effect, see I.
C. Kizilyalli, J. W. Lyding, and K. Hess, "Deuterium post-metal
annealing of MOSFET's for improved hot carrier reliability," IEEE
Electron Device Lett., vol. 18, p. 81, March 1997. It has also
recently been found that the large isotope effect is only observed
for interface state generation by channel hot electrons, and not by
carriers injected into the oxide--see Z. Chen et al, "On the
mechanism for interface trap generation in MOS transistors due to
channel hot carrier stressing," IEEE Electron Device Lett., vol. 21
pp. 24-26, January 2000.
[0033] FIG. 4 shows the extrapolated lifetime improvements found
for each annealing condition at the specific operating substrate
current of 2 .mu.A, derived from the G.sub.m, V.sub.th, and
I.sub.d,sat measurements. The lifetimes were extracted from more
than 15 data points for each condition in a log(lifetime) vs.
log(substrate current) graph. Among the annealing conditions,
450.degree. C. at 6 atm for 3 h exhibited the maximum improvement.
With higher pressure processing, shorter annealing times can
achieve the same magnitude of improvement. This is evident by
comparing the data from the device annealed at 2 atm for 3 h with
the one annealed at 6 atm for 1 h. In both cases, the lifetime
improvements were nearly the same. With the higher pressure, the
processing time was shortened by a factor of three. It is also
interesting to note that the maximum lifetime improvement from
deuterium annealing above atmospheric pressure in accordance with
embodiments of the invention as described in this Experimental, is
slightly higher than what was found in a previous study reported in
I. C. Kizilyalli et al., "Improvement of hot carrier reliability
with deuterium anneals for manufacturing multilevel
metal/dielectric MOS systems," IEEE Electron Device Lett., vol. 19,
pp. 444-446, November 1999. In that previous study, the devices had
oxide sidewall spacers and were annealed at 1 atm for 5 h to
achieve 80.times. improvement. With high pressure annealing,
embodying the present invention, a shorter annealing time was
required to achieve the same result from devices with substantially
greater diffusion barriers imposed by the sidewall spacers and
caps. Longer annealing time at a specific deuterium pressure gives
better lifetime improvement. These factors highlight the
correlation between D incorporation at the gate silicon
oxide/silicon interface and lifetime improvement--see J. Lee et al.
"SIMS characterization of the deuterium sintering process for
enhanced-lifetime CMOS transistors," J. Vac. Sci. Technol., vol.
A16, p.1762,1998.
[0034] To confirm that the measured lifetime improvements correlate
directly with deuterium incorporation, SIMS depth profiles of
hydrogen and deuterium were obtained. FIG. 5 shows SIMS profiles
comparing the deuterium incorporation for sintering at 2 atm for 1
and 3 h and at 6 atm for 20 min. The profiles clearly show that for
both pressures, deuterium is incorporated at the SiO.sub.2/Si
interface and that pressure increases the D incorporation at the
interface and throughout the SiO.sub.2 layer. Note that there is
more D incorporation for the 20 min anneal at 6 atm than for the 3
hour anneal at 2 atm. Since the H profiles in all three samples
were almost identical, only one profile is shown for clarity.
[0035] The beneficial effects of high pressure deuterium annealing
on hot carrier reliability improvements of CMOS transistors has
been disclosed. High pressure deuterium annealing has been shown to
increase the rate of deuterium incorporation at the SiO.sub.2/lSi
(gate oxide/channel) interface. A significant lifetime improvement
(.sup.-90.times.) can be achieved from fully processed wafers (four
metal layers) with nitride sidewall spacers and SiON cap layers,
subjected to the novel deuterium annealing process. The improvement
was determined by comparing to wafers that were annealed in a
conventional hydrogen forming gas anneal. The annealing time to
achieve the same level of improvement can also be significantly
reduced. The increased incorporation of D at high pressure was
confirmed by the secondary ion mass spectrometry characterization.
The above description of embodiments of the invention has
demonstrated the effectiveness of high pressure deuterium annealing
at increasing the D incorporation rate. Even when applied to the
devices with severe diffusion barriers to D, high pressure
annealing improves hot carrier reliability with much shorter
annealing times.
* * * * *