U.S. patent application number 09/988651 was filed with the patent office on 2002-03-14 for method for decreasing chc degradation.
Invention is credited to Harris, George E., Larkin, David L., Smith, William D..
Application Number | 20020030247 09/988651 |
Document ID | / |
Family ID | 22257850 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020030247 |
Kind Code |
A1 |
Larkin, David L. ; et
al. |
March 14, 2002 |
Method for decreasing CHC degradation
Abstract
A method for decreasing CHC degradation is provided. The method
includes providing a semiconductor device (10) having at least one
metal layer (28) completed. Then, a planarizing dielectric layer
(30) is added to the semiconductor device (10). The semiconductor
device (10) is heated in a hydrogen rich environment until hydrogen
completely saturates the semiconductor device (10).
Inventors: |
Larkin, David L.;
(Richardson, TX) ; Harris, George E.; (Garland,
TX) ; Smith, William D.; (Garland, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
22257850 |
Appl. No.: |
09/988651 |
Filed: |
November 20, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09988651 |
Nov 20, 2001 |
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09373215 |
Aug 12, 1999 |
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60096542 |
Aug 13, 1998 |
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Current U.S.
Class: |
257/629 ;
257/324; 257/634; 257/635; 257/E21.194; 257/E21.212; 257/E21.243;
257/E21.262; 257/E21.279; 257/E21.324; 257/E21.576; 257/E29.162;
438/958 |
Current CPC
Class: |
H01L 21/02164 20130101;
Y10S 438/958 20130101; H01L 21/31612 20130101; H01L 21/76801
20130101; H01L 21/022 20130101; H01L 21/02134 20130101; H01L
21/76826 20130101; H01L 21/28176 20130101; H01L 21/324 20130101;
H01L 21/02274 20130101; H01L 29/51 20130101; H01L 21/76825
20130101; H01L 21/02282 20130101; H01L 21/3003 20130101; H01L
21/31051 20130101; H01L 21/02337 20130101; H01L 21/76828 20130101;
H01L 21/3124 20130101 |
Class at
Publication: |
257/629 ;
257/634; 257/635; 438/958; 257/324 |
International
Class: |
H01L 023/58; H01L
029/792 |
Claims
What is claimed is:
1. A method for decreasing CHC degradation, comprising: providing a
semiconductor device having at least one metal layer completed;
applying a planarizing dielectric layer on top of the semiconductor
device; and providing a hydrogen treatment until hydrogen diffuses
throughout the semiconductor device.
2. The method of claim 1, wherein the hydrogen treatment includes
heating the semiconductor device in a hydrogen rich
environment.
3. The method of claim 1, wherein the hydrogen treatment includes
applying hydrogen in situ by introducing hydrogen as a plasma to
the semiconductor device.
4. The method of claim 1, wherein the planarizing dielectric layer
includes a first layer of TEOS, a second layer of HSQ, and a third
layer of TEOS.
5. The method of claim 1, wherein the planarizing dielectric layer
includes a first layer of TEOS applied by PECVD.
6. The method of claim 1, wherein the planarizing dielectric layer
includes a second layer of HSQ applied by coating over a first
layer of dielectric material.
7. The method of claim 1, wherein the planarizing dielectric layer
includes a third layer of TEOS applied by PECVD over two layers of
dielectric material.
8. The method of claim 1, wherein the semiconductor device
undergoes an N.sub.2 bake after an HSQ layer of a multilayer
planarizing dielectric layer is added.
9. The method of claim 1, wherein the semiconductor device
undergoes the hydrogen treatment after a final layer of a
multilayer planarizing dielectric layer is added.
10. A semiconductor device for reducing CHC degradation comprising:
a gate oxide region completely saturated with hydrogen formed
outwardly from a substrate; a gate region formed outwardly from the
gate oxide region; and a dielectric layer formed outwardly from the
substrate, the gate oxide region and the gate region.
11. The semiconductor device of claim 10, wherein the gate oxide
region, the gate region and the dielectric layer are saturated with
hydrogen.
12. A semiconductor device manufactured using the following
process: providing a semiconductor device having at least one metal
layer completed; applying a planarizing dielectric layer on top of
the semiconductor device; and providing a hydrogen treatment until
hydrogen diffuses throughout the semiconductor device.
13. The semiconductor device of claim 12, wherein the hydrogen
treatment includes heating the semiconductor device in a hydrogen
rich environment.
14. The semiconductor device of claim 12, wherein the hydrogen
treatment includes applying hydrogen in situ by introducing
hydrogen as a plasma to the semiconductor device.
15. The semiconductor device of claim 12, wherein the planarizing
dielectric layer includes a first layer of TEOS, a second layer of
HSQ, and a third layer of TEOS.
16. The semiconductor device of claim 12, wherein the planarizing
dielectric layer includes a first layer of TEOS applied by
PECVD.
17. The semiconductor device of claim 12, wherein the planarizing
dielectric layer includes a second layer of HSQ applied by coating
applied over a first layer of dielectric material.
18. The semiconductor device of claim 12, wherein the planarizing
dielectric layer includes a third layer of TEOS applied by PECVD
applied over two layers of dielectric material.
19. The semiconductor device of claim 12, wherein the semiconductor
device undergoes an N.sub.2 bake after an HSQ layer of a multilayer
planarizing dielectric layer is added.
20. The semiconductor device of claim 12, wherein the semiconductor
device undergoes the hydrogen treatment after a final layer of the
planarizing dielectric layer is added.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] This invention relates to the field of semiconductor
manufacturing and more specifically to a method for decreasing CHC
degradation.
BACKGROUND OF THE INVENTION
[0002] The operation of semiconductor devices, such as a
transistor, requires for its operation the flow of carriers from a
source to a drain. Any breakdown in that flow can degrade device
performance. Device performance has been known to be degraded by a
phenomenon commonly known as CHC (channel hot carrier)
degradation.
[0003] In multilevel semiconductor devices, i.e., those that have
multiple metal layers, CHC degradation can occur from a variety of
causes. In a multilevel semiconductor device, a first metal layer
is formed and covered by a dielectric. The dielectric then has
photoresist placed on it and the entire device undergoes
photolithography. The dielectric is then etched in areas where the
photoresist was removed. During processing or handling,
contaminates (such as water, sodium, ions, and metallics) can be
introduced to the semiconductor device. During the lifetime of the
semiconductor device, contaminants can migrate down through the
semiconductor devices and degrade the operation of the
semiconductor device.
[0004] One solution to this problem is to use a dense material for
the dielectric. One proposed material is to use a silane based
oxide. It is theorized that the dense nature of silane based oxide
keeps contaminants from migrating through the semiconductor device,
thus decreasing the chance of performance degradation.
[0005] Unfortunately, silane based oxides have several drawbacks.
First, in order to form silane based oxides, silane gas must be
used. Silane gas is very reactive and special facilities are
required to handle it. Also, silane based oxides have a tendency to
undergo "bread loafing," or uneven application, which can result in
voids in the dielectric.
[0006] Another way of reducing CHC degradation that has been
proposed involves making the transition between the junction region
under a gate and the junction region of the drain more gradual.
This involves implanting the drain region multiple times using
different dopants. This implantation is done with a mask in order
to accurately dope the drain region. One drawback with this
approach is that the process is very costly. Another drawback is
that the procedure tends to decrease the distance between the
source region and the drain region. To compensate for this, larger
transistors are needed which leads to inefficient designs and
higher manufacturing costs.
[0007] It has been theorized that contaminants migrate through the
semiconductor device and encounter "dangling bonds". Some dangling
bonds are the result of incomplete bonding at the
silicon/dielectric interface, the poly gate/dielectric interface,
the poly gate/gate oxide interface, and/or the gate oxide/silicon
interface. It is also theorized that if the bonds can be pacified,
contaminants are less likely to combine with the dangling bonds and
degrade the device.
[0008] Another theory concerning CHC degradation is that
contaminants are small enough to diffuse through the semiconductor
device and accumulate, leading to degradation of performance. It is
theorized that heat can cause an added element to bond to the
contaminant, thus rendering the contaminant too large to diffuse
through the semiconductor device.
[0009] Whatever the exact mechanism of damage, what is needed is a
method for preventing contaminants from causing CHC
degradation.
SUMMARY OF THE INVENTION
[0010] Accordingly, it may be appreciated that a need has arisen
for a method for decreasing CHC degradation in accordance with the
teaching of present invention.
[0011] In one embodiment a method for decreasing CHC degradation is
disclosed. The method includes providing a semiconductor device
having at least one metal layer completed. Then a planarizing
dielectric layer is added to the semiconductor device. The
semiconductor device then undergoes a hydrogen treatment until
hydrogen completely saturates the semiconductor device.
[0012] The present invention provides various technical advantages
over current methods for decreasing CHC degradation. For example,
one technical advantage is that the chemicals used are easy to
handle. Another technical advantage is that CHC degradation is
reduced in an efficient manner. Other technical advantages may be
readily apparent to one skilled in the art from the following
figures, descriptions, and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] For a more complete understanding of the present invention
and the advantages thereof, reference is now made to the following
description taken in conjunction with the accompanying drawings, in
which like reference numbers represent like parts, wherein:
[0014] FIG. 1 illustrates a semiconductor device for decreasing CHC
degradation;
[0015] FIG. 2 illustrates one embodiment of the planarizing
dielectric layer in the semiconductor device; and,
[0016] FIG. 3 illustrates a flow chart of the manufacturing steps
for creating the semiconductor device.
DETAILED DESCRIPTION OF THE INVENTION
[0017] FIG. 1 illustrates a semiconductor device 10. Illustrated is
a substrate layer 12 having junction regions 14 and 16. Also
illustrated is a gate oxide layer 20 which is located underneath a
gate layer 22. A source contact 24 and a drain contact 26 are
illustrated. A first dielectric layer 18 is formed above substrate
12. This is the first layer in a multilayer semiconductor device.
Also illustrated is a metal layer 28. To further process
semiconductor device 10 a planarizing dielectric layer (PDL) 30 is
applied over metal layer 28. After metal layer 28 is in place,
contaminants can be introduced either during processing (such as
when a planarizing dielectric layer 30 is applied) or during
handling.
[0018] Damage to device 10 can occur in areas highlighted by circle
17. This includes a gate oxide layer 20/gate layer 22 interface, a
substrate layer 12/first dielectric layer 18 interface, a gate
layer 22/first dielectric layer 18 interface, and a gate oxide
layer 20/substrate layer 12 interface.
[0019] In the present invention, after planarizing dielectric layer
30 has been added, the entire semiconductor device 10 undergoes a
hydrogen treatment. In one embodiment, a hydrogen treatment
involves placing semiconductor device 10 in a hydrogen rich
environment and heating semiconductor device 10 in that environment
until hydrogen has saturated completely within semiconductor device
10. Other hydrogen treatments include any process that will
introduce hydrogen throughout semiconductor device 10, including
introducing hydrogen in situ using a plasma process. Alternatively,
the hydrogen can be implanted directly using ion implantation. As
previously discussed, this will either pacify any dangling bonds in
semiconductor device 10 and, thus, prevent damage to gate oxide
layer 20, or cause the hydrogen to bond with contaminants, thereby
making the contaminant too large to diffuse through semiconductor
device 10.
[0020] FIG. 2 illustrates one embodiment of planarizing dielectric
layer 30. In this embodiment, planarizing dielectric layer 30
comprises three (3) distinct layers. A first layer 32 includes
tetraethyloxysilicate (TEOS) First layer 32 is applied to
semiconductor device 10 at a temperature of approximately 350
degrees centigrade using plasma enhanced chemical vapor deposition
(PECVD). A second layer 34 includes hydrogen silsequioxane (HSQ).
HSQ is applied as a liquid coating on top of first layer 32.
Semiconductor device 10 is then taken to a furnace and cured until
second layer 34 hardens. After second layer 34 hardens,
semiconductor device 10 undergoes an N.sub.2 pre-bake. The N.sub.2
pre-bake is done to remove moisture from the HSQ of second layer 34
which is hydroscopic (readily absorbs moisture). A third layer 36
includes additional TEOS. Third layer 36 is also applied by PECVD.
Upon formation of third layer 36, semiconductor device 10 undergoes
the H.sub.2 bake as described above. Although these chemicals have
been listed as comprising planarizing dielectric layer 30, this is
not to exclude any other suitable chemicals to be used for the
different layers. It is true, however, that the use of a hydrogen
treatment allows TEOS to be used instead of a silane based oxide in
first layer 32.
[0021] FIG. 3 illustrates a flow chart of the method of
manufacturing semiconductor device 10. In a first step 40, an
integrated circuit with at least one complete metal layer is
provided. In step 42, a TEOS layer is applied using PECVD. Then in
step 44, the TEOS layer is coated with HSQ. The integrated circuit
is then cured until it is hardened. Then in step 46, an N.sub.2
bake is done to remove any moisture collected during the HSQ
coating. In step 48, a second layer of TEOS is applied using PECVD.
In step 50, an H.sub.2 bake is done until H.sub.2 completely
saturates and protects semiconductor device 10.
[0022] Thus, it is apparent that there has been provided, in
accordance with the present invention, a method for decreasing CHC
degradation that satisfies the advantages set forth above. Although
the present invention has been described in detail, it should be
understood that various changes, substitutions, and alterations may
be readily ascertainable by those skilled in the art and may be
made herein without departing from the spirit and scope of the
present invention as defined by the following claims.
* * * * *