U.S. patent application number 09/886552 was filed with the patent office on 2002-02-28 for memory module for preventing skew between bus lines.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Jung, Tae-Sung, Song, Won-Ki.
Application Number | 20020024833 09/886552 |
Document ID | / |
Family ID | 19685656 |
Filed Date | 2002-02-28 |
United States Patent
Application |
20020024833 |
Kind Code |
A1 |
Song, Won-Ki ; et
al. |
February 28, 2002 |
Memory module for preventing skew between bus lines
Abstract
A memory module for preventing skew between bus lines is
provided. The memory module includes a printed circuit board,
memory chips, module tabs and bus lines. The memory chips are
disposed on the printed circuit board, and the module tabs are
disposed at one edge of the printed circuit board. The bus lines
are connected to the module tabs, respectively, and are connected
to the memory chips. Each of the bus lines is formed a closed
circuit loop. Each of the bus lines is connected to the memory
chips through a circuitous or roundabout path which includes first
and second paths of, in general, different lengths. The first and
second paths of the roundabout path branch from each other at a
position on the closed circuit loop. Since each bus line on the
memory module forms a closed loop, skew does not occur between
control signals or output data, which are transmitted through the
bus line.
Inventors: |
Song, Won-Ki; (Suwon-city,
KR) ; Jung, Tae-Sung; (Seoul, KR) |
Correspondence
Address: |
Steven M. Mills, Esq.
Mills & Onello, LLP
Eleven Beacon Street, Suite 605
Boston
MA
02108
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
|
Family ID: |
19685656 |
Appl. No.: |
09/886552 |
Filed: |
June 21, 2001 |
Current U.S.
Class: |
365/63 |
Current CPC
Class: |
H05K 2201/10159
20130101; H05K 1/0248 20130101; G11C 5/063 20130101; H05K
2201/09254 20130101; G06F 13/4234 20130101 |
Class at
Publication: |
365/63 |
International
Class: |
G11C 005/06 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 28, 2000 |
KR |
00-50166 |
Claims
1. A memory module comprising: a printed circuit board; a plurality
of memory chips disposed on the printed circuit board; module tabs
disposed at one edge of the printed circuit board; and a bus line
connected to at least one of the module tabs and connected to the
memory chips, a portion of the bus line connected to the memory
chips being formed as a closed circuit loop.
2. The memory module of claim 1, wherein the bus line is connected
to the memory chips around the closed circuit loop through first
and second paths, one of the first and second paths being longer
than the other of the first and second paths, the first and second
paths branching from each other at a branch position on the closed
circuit loop.
3. A memory module comprising: a printed circuit board; a plurality
of memory chips disposed on the printed circuit board; module tabs
disposed at one edge of the printed circuit board; a buffer
connected to at least one of the module tabs; and a bus line
connected to the output of the at least one buffer and connected to
the memory chips, a portion of the bus line connected to the memory
chips being formed as a closed circuit loop.
4. The memory module of claim 1, wherein the bus line is connected
to the memory chips around the closed circuit loop through first
and second paths, one of the first and second paths being longer
than the other of the first and second paths, the first and second
paths branching from each other at a branch position on the closed
circuit loop.
5. The memory module of claim 3, wherein the buffer increases the
transition speed of signals passing through the bus lines.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a memory module, and more
particularly, to a memory module for preventing skew between bus
lines within the memory module.
[0003] 2. Description of the Related Art
[0004] A memory module is provided with a plurality of memory chips
and is electrically connected to external devices such as a memory
controller and a microprocessor through module tabs which are
inserted into and contact sockets. The memory chips are connected
to each other through bus lines disposed on the memory module. The
bus lines are connected to external bus lines through the module
tabs and carry commands transmitted to the memory chips or data
output from the memory chips.
[0005] FIG. 1 is a diagram illustrating a conventional memory
module. The conventional memory module includes first through
eighth memory chips M1, M2, . . . , M8. The memory chips M1 through
M8 are connected to one another through a bus line 10 which is
connected to an external bus line through a module tab 20. The bus
line has different line loads depending on physical distances to
the memory chips M1 through M8. For example, the waveforms of
signals through a bus line 1 connected to the first memory chip M1,
through a bus line 5 connected to the fifth memory chip M5 and
through a bus line 8 connected to the eighth memory chip M8,
respectively, are as shown in FIG. 2.
[0006] In FIG. 2, the signal waveform on the bus line 5 connected
to the fifth memory chip M5 appears first because the fifth memory
chip M5 is nearest to the bus line 10. Next, the signal waveform on
the bus line 8 connected to the eighth memory chip M8 appears with
a little delay compared to the waveform on the bus line 5. The
signal waveform on the bus line 1 connected to the first bus line
M1 appears last. This is because the bus line 1 is longer than the
bus line 5 and the bus line 8. Therefore, a time delay occurs
between the waveform on the bus line 5 and the waveform on the bus
line 1. This time delay is referred to as skew and is represented
by t.sub.SKEW.
[0007] When a signal transmitted through the bus line 10 is related
to an operating command, such skew t.sub.SKEW causes the memory
chips to operate at different times. As a result, this skew hinders
the high speed data processing between the memory module and an
external memory controller or an external microprocessor.
[0008] Accordingly, a method for reducing skew between bus lines
within a memory module is desired.
SUMMARY OF THE INVENTION
[0009] To solve the above problems, it is an object of the present
invention to provide a memory module for reducing skew between bus
lines.
[0010] Accordingly, to achieve the above object of the invention,
in one embodiment, there is provided a memory module including a
printed circuit board, a plurality of memory chips disposed on the
printed circuit board, module tabs disposed at one edge of the
printed circuit board, and bus lines connected to the module tabs,
respectively, and connected to the memory chips. A portion of the
bus line that is connected to the memory chips is formed as a
closed circuit loop.
[0011] In one embodiment, each of the bus lines is connected to the
memory chips through a circuitous or roundabout path which includes
fist and second paths of, in general, different lengths. The first
and second paths of the roundabout path branch from each other at a
position on the closed circuit loop.
[0012] In another embodiment, there is provided a memory module
including a printed circuit board, a plurality of memory chips
disposed on the printed circuit board, module tabs disposed at one
edge of the printed circuit board, buffers connected to the module
tabs, respectively, and bus lines connected to the outputs of the
buffers, respectively, and connected to the memory chips. A portion
of each of the bus lines that is connected to the memory chips is
formed as a closed circuit loop. The buffers increase the
transition speed of signals passing through the bus lines.
[0013] According to the present invention, each bus line on the
memory module forms a closed loop, so that skew does not occur
between control signals or output data, which are transmitted
through the bus line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The foregoing and other objects, features and advantages of
the invention will be apparent from the following more particular
description of preferred embodiments of the invention, as
illustrated in the accompanying drawings in which like reference
characters refer to the same parts throughout the different views.
The drawings are not necessarily to scale, emphasis instead being
placed upon illustrating the principles of the invention.
[0015] FIG. 1 is a diagram illustrating a conventional memory
module.
[0016] FIG. 2 is a diagram illustrating the waveforms of signals on
the bus lines of FIG. 1.
[0017] FIG. 3 is a diagram illustrating a memory module according
to an embodiment of the present invention.
[0018] FIG. 4 is a diagram illustrating the waveforms of signals on
the bus lines of FIG. 3.
[0019] FIG. 5 is a diagram illustrating a memory module according
to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0020] Hereinafter, the present invention will be described in
detail by describing preferred embodiments of the present invention
with reference to the attached drawings.
[0021] Referring to FIG. 3, which illustrates a memory module
according to an embodiment of the present invention, the memory
module includes a plurality of memory chips M1, M2, M3, M4 and M5
on a printed circuit board 100. Module tabs are disposed at one
side edge of the printed circuit board 100. A bus line 150 is
connected to the module tab 200. In addition, the bus line 150 is
connected to the memory chips M1 through M5. The bus line 150
constructs a single closed circuit. Control signals related to
commands provided from a memory controller or a microprocessor or
data output from the memory chips M1 through M5 are transmitted
through the bus line 150.
[0022] For example, a control signal for the second memory chip M2
and data output from the second memory chip M2 are transmitted
through the bus line 150 which is a closed circuit. More
specifically, a control signal for the second memory chip M2
reaches a position A through the module tab 200 and along the bus
line 150. At the position A, the control signal is transmitted to
the second memory chip M2 along the paths into which the bus line
150 branches at the position A. The paths are denoted by arrow
headed solid lines (.fwdarw.). A circuitous or roundabout path from
the position A to the second memory module M2 is referred to as
line M2b, and a shorter path is referred to as a line M2s. The
control signal charge-shares with the lines M2s and M2b and is
transmitted to the second memory chip M2. The line M2s corresponds
to a bus line through which a control signal is transmitted to the
second memory chip M2 in a conventional memory module.
[0023] Accordingly, the control signal reaches the second memory
chip M2 in the present invention later than in a conventional
memory module. However, control signals for the other memory chips
M1, M3, M4 and M5 in addition to the second memory chips M2 are
transmitted through the bus line which is a closed circuit, so the
control signals reach the memory chips M1 through M5 at
approximately the same time. In particular, the control signals
input for the memory chips M1 through M5 nearly meet at one
transition point, as shown in FIG. 4. Thus, skew does not occur
between control signals transmitted to the memory chips M1 through
M5.
[0024] Thereafter, the output data of the second memory chip M2
operated in response to the control signal is transmitted to the
bus line 150 along paths, into which a line from the second memory
chip M2 branches at a position B, and then transmitted to an
external bus line through the module tab 200. The paths are denoted
by arrow headed dotted lines (.fwdarw.). Here, the output data of
each of the memory chips M1 through M5 is transmitted to the module
tab 200 through the lines M2s and M2b. Therefore, the output data
of the memory chips M1 through M5 reach a memory controller or a
microprocessor, which is connected to the external bus line, nearly
at the same time, so that skew does not occur between the output
data.
[0025] A memory module shown in FIG. 5 is almost the same as the
memory module of FIG. 3, with the exception that a buffer 300 is
further provided on the bus line 150. The buffer 300 is used for
increasing the transition speed of a control signal on the bus line
150 or the transition speed of the output data of memory chips.
Accordingly, a delay in signal transmission due to the load on the
bus line 150 can be reduced. The buffer 300 can be realized as a
typical inverter chain or a driver.
[0026] While this invention has been particularly shown and
described with references to preferred embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made therein without departing from the
spirit and scope of the invention as defined by the following
claims.
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