U.S. patent application number 09/904095 was filed with the patent office on 2002-02-21 for method for forming capacitor of semiconductor device.
Invention is credited to Choi, Hyung Bok.
Application Number | 20020022318 09/904095 |
Document ID | / |
Family ID | 73159648 |
Filed Date | 2002-02-21 |
United States Patent
Application |
20020022318 |
Kind Code |
A1 |
Choi, Hyung Bok |
February 21, 2002 |
Method for forming capacitor of semiconductor device
Abstract
A method for forming a capacitor of a semiconductor device
prevents characteristic of a device from being deteriorated due to
residue resulting from a process step of defining a storage node.
The method for forming a capacitor of a semiconductor device
includes the steps of forming an insulating film having a contact
hole on a substrate, forming a conductive layer within the contact
hole, forming a first metal layer on an entire surface including
the conductive layer, forming a dummy pattern and an etching
barrier film on the first metal layer, selectively etching the
dummy pattern and the etching barrier film to form a lower
electrode formation region, forming a second metal layer in the
lower electrode formation region using the first metal layer as a
seed layer, removing the etching barrier film and the dummy pattern
and performing a wet cleaning process to remove residue resulting
from removing the etching barrier film and the dummy pattern, and
removing the exposed first metal layer to form a lower
electrode.
Inventors: |
Choi, Hyung Bok;
(Kyonggi-do, KR) |
Correspondence
Address: |
MORGAN, LEWIS & BOCKIUS
1800 M STREET NW
WASHINGTON
DC
20036-5869
US
|
Family ID: |
73159648 |
Appl. No.: |
09/904095 |
Filed: |
July 13, 2001 |
Current U.S.
Class: |
438/253 ;
257/E21.009; 257/E21.011; 257/E21.021; 257/E21.168;
257/E21.309 |
Current CPC
Class: |
H01L 21/32134 20130101;
H01L 28/75 20130101; H01L 28/60 20130101; H01L 21/28568 20130101;
H01L 28/55 20130101 |
Class at
Publication: |
438/253 |
International
Class: |
H01L 021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 18, 2000 |
KR |
2000-20740 |
Claims
What is claimed is:
1. A method for forming a capacitor of a semiconductor device
comprising the steps of: forming an insulating film having a
contact hole on a substrate; forming a conductive layer within the
contact hole; forming a first metal layer on an entire surface
including the conductive layer; forming a dummy pattern and an
etching barrier film on the first metal layer; selectively etching
the dummy pattern and the etching barrier film to form a lower
electrode formation region; forming a second metal layer in the
lower electrode formation region using the first metal layer as a
seed layer; removing the etching barrier film and the dummy pattern
and performing a wet cleaning process to remove residue resulting
from removing the etching barrier film and the dummy pattern; and
removing the exposed first metal layer to form a lower
electrode.
2. The method of claim 1, wherein the lower electrode formation
region partially overlaps the conductive layer.
3. The method of claim 1, wherein a cleaning solution that can
react with the residue containing a component of the second metal
layer to remove the residue is used in the wet cleaning
process.
4. The method of claim 3, wherein the wet cleaning process is
performed in such a manner that a mixing ratio of
H.sub.2SO.sub.4:H.sub.2O.sub.2 is maintained at 1:0.1.about.1:100,
a processing temperature is 4.about.100.degree. C. and dipping time
is 2.about.3600 sec.
5. The method of claim 3, wherein the wet cleaning process is
performed in such a manner that diluted H.sub.2SO.sub.4, a mixing
solution of NH.sub.4OH/H.sub.2O.sub.2/H.sub.2O, a mixing solution
of HF/H.sub.2O, and a mixing solution of HF/HN.sub.4F is used
solely or by sequentially combining them.
6. The method of claim 1, wherein the etching barrier film is
removed by a dry etching process and the dummy pattern is removed
by a wet deep-out process.
7. The method of claim 6, wherein the wet deep-out process is
performed using a mixing solution of HF or HF/NH.sub.4F.
8. The method of claim 1, wherein the conductive layer is formed by
sequentially depositing a plug layer, a low resistance contact
layer, and a barrier layer.
9. The method of claim 1, further comprising the step of forming a
surface anti-reflecting film on a surface of the insulating film
other than the contact hole, using a material having high etching
selectivity.
10. The method of claim 1, wherein the first metal layer is formed
at a thickness of 50.about.1000 .ANG. using any one of Pt, Ru, Ir,
Os, W, Mo, Co, Ni, Au and Ag.
11. The method of claim 1, wherein the dummy pattern is formed of a
photoresist or a CVD oxide film.
12. The method of claim 1, wherein the second metal layer is formed
by an ECD process in which current density is within the range of
0.1.about.10 mA/cm.sup.2, and DC power, pulse power or reverse
pulse power is used.
13. A method for forming a capacitor of a semiconductor device
comprising the steps of: sequentially forming an insulating film
and a surface anti-reflecting film on an entire surface including a
cell transistor; sequentially forming a plug layer, a low
resistance contact layer, and a barrier layer within the contact
hole; depositing Pt on the entire surface to form a first metal
layer used as a seed layer; forming a dummy pattern and an etching
barrier film on the entire surface and selectively etching them to
form a lower electrode formation region; forming a second metal
layer using the exposed first metal layer as a seed layer by an ECD
process; removing the etching barrier film and the dummy pattern
and performing a wet cleaning process using a solution that can
react with residue containing a component of the second metal layer
to remove the residue; removing the exposed first metal layer to
form a lower electrode; depositing BST on the entire surface to
form a dielectric layer; depositing Pt on the dielectric layer and
selectively patterning Pt to form an upper electrode.
14. The method of claim 13, wherein the plug layer is formed in
such a manner that a doped polysilicon layer is deposited within
the contact hole by a CVD process and then etched back to have a
recess portion of 500.about.1500 .ANG. at an upper portion of the
contact hole.
15. The method of claim 13, wherein the low resistance contact
layer is formed in such a manner that Ti is deposited on Si at a
thickness of 100.about.300 .ANG. and annealed to form TiSix, and
some of Ti which is not reacted with Si is removed by a wet etching
process.
16. The method of claim 13, wherein the barrier film is formed in
such a manner that any one of TiN, TiSiN, TiAlN, TaSiN, and TaAlN
is deposited on the entire surface by a PVD or CVD process and then
flattened to remain on the low resistance contact film by a CMP
process.
17. The method of claim 13, wherein the dielectric layer is formed
by a CVD process at a thickness of 150.about.500 .ANG. within the
range of a temperature of 400.about.600.degree. C.
18. The method of claim 13, wherein the dielectric layer is
crystallized by an RTP process for 30.about.180 sec under the
ambient of N between 500.degree. C. and 700.degree. C.
19. The method of claim 13, wherein the wet cleaning process is
performed in such a manner that a mixing ratio of
H.sub.2SO.sub.4:H.sub.2O.sub.2 is maintained at 1:0.1.about.1:100,
a processing temperature is 4.about.100.degree. C. and dipping time
is 2.about.3600 sec.
20. The method of claim 13, wherein the wet cleaning process is
performed in such a manner that diluted H.sub.2SO.sub.4, a mixing
solution of NH.sub.4OH/H.sub.2O.sub.2/H.sub.2O, a mixing solution
of HF/H.sub.2O, and a mixing solution of HF/HN.sub.4F is used
solely or by sequentially combining them.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for fabricating a
semiconductor memory device, and more particularly, to a method for
forming a capacitor of a semiconductor device that prevents
characteristic of a device from being deteriorated due to residue
resulting from a process step of defining a storage node.
[0003] 2. Background of the Related Art
[0004] Generally, in a process for fabricating a DRAM capacitor
based on an electro-chemical deposition (ECD) Pt process, a SiON
film is deposited on a dummy pattern layer to improve a profile of
a dummy pattern for defining a storage node.
[0005] The SiON film acts as an etching barrier film to facilitate
a vertical profile of the dummy pattern. To remove the dummy
pattern formed after the ECD Pt process, the SiON film is removed
by a dry etching process.
[0006] A related art method for forming a capacitor of a
semiconductor device will be described with reference to the
accompanying drawings.
[0007] FIGS. 1A to 1E are sectional views illustrating related art
process steps of forming a capacitor of a semiconductor device.
FIG. 2A is a photograph showing a storage node after etch-back of
an etching barrier film, and FIG. 2B is a photograph showing a
storage node after wet deep-out of a dummy pattern.
[0008] As shown in FIG. 1A, an insulating film 11 and a surface
anti-reflecting film 12 are sequentially formed on a semiconductor
substrate (not shown) in which a cell transistor (not shown) is
formed. A contact hole is formed to connect a capacitor with one
electrode of the cell transistor.
[0009] A doped polysilicon layer is deposited within the contact
hole by a chemical vapor deposition (CVD) process. The doped
polysilicon layer is then etched back to form a recess portion, so
that a plug layer 13 is formed. A low resistance contact film 14
and a barrier film 15 are formed in the recess portion so as to
reduce contact resistance between the plug layer 13 and the barrier
film 15 which will be formed later.
[0010] The low resistance contact film 14 is formed in such a
manner that a material such as Ti is deposited on a silicon (Si)
and annealed to form TiSix, and some of Ti which is not reacted
with Si is removed.
[0011] The barrier film 15 is formed on an entire surface including
a portion where the low resistance contact film 14 is formed. The
barrier film 15 is then flattened to remain on the low resistance
contact film 14.
[0012] Subsequently, Pt is deposited on the entire surface to form
a first metal layer 16 used as a seed layer.
[0013] As shown in FIG. 1B, a dummy pattern 17 for patterning of a
storage node and an etching barrier film 18 are formed on the
entire surface. SiON is used as the etching barrier film 18.
[0014] As shown in FIG. 1C, the dummy pattern 17 and the etching
barrier film 18 are selectively etched by a photolithography
process to define a lower electrode formation region 19.
[0015] As shown in FIG. 1D, a second metal layer 20 is formed using
the first metal layer 16 exposed in the storage node formation
region, i.e., in a portion where the dummy pattern 17 is removed,
as a seed layer. The second metal layer 20 is formed by the ECD
process.
[0016] As shown in FIG. 1E, the etching barrier film 18 is removed
by a dry etching process and the dummy pattern 17 is removed by a
wet deep-out process.
[0017] However, in the related art process as above, when SiON used
as the etching barrier film 18 is dry etched, blanket etching is
performed without using a photo mask. At this time, since a dry
etching gas acts on an upper surface of a lower electrode of Pt,
residue containing Pt is generated.
[0018] Such residue remains even after the wet deep-out of the
dummy pattern. In this case, electrical characteristic of the
device may be deteriorated. Photographs showing such residue are
shown in FIGS. 2A and 2B. Referring to FIG. 2B, a large quantity of
the residue generated during etch-back process of the etching
barrier film remains.
[0019] However, the related art method for forming a capacitor of a
semiconductor device has several problems.
[0020] When removing the etching barrier film used to obtain a
vertical profile of the dummy pattern for defining the storage
node, residue is generated. The residue remains even after the
dummy pattern is removed, thereby deteriorating electrical
characteristic of the device. Particularly, unevenness occurs when
a BST dielectric layer is deposited. For this reason, capacitance
between cells becomes uneven and loss of current partially
occurs.
SUMMARY OF THE INVENTION
[0021] Accordingly, the present invention is directed to a method
for forming a capacitor of a semiconductor device that
substantially obviates one or more of the problems due to
limitations and disadvantages of the related art.
[0022] An object of the present invention is to provide a method
for forming a capacitor of a semiconductor device that prevents
characteristic of a device from being deteriorated due to residue
resulting from a process step of defining a storage node.
[0023] Additional advantages, objects, and features of the
invention will be set forth in part in the description which
follows and in part will become apparent to those having ordinary
skill in the art upon examination of the following or may be
learned from practice of the invention. The objects and advantages
of the invention may be realized and attained as particularly
pointed out in the appended claims.
[0024] To achieve these and other advantages and in accordance with
the purpose of the present invention, as embodied and broadly
described, a method for forming a capacitor of a semiconductor
device includes the steps of forming an insulating film having a
contact hole on a substrate, forming a conductive layer within the
contact hole, forming a first metal layer on an entire surface
including the conductive layer, forming a dummy pattern and an
etching barrier film on the first metal layer, selectively etching
the dummy pattern and the etching barrier film to form a lower
electrode formation region, forming a second metal layer in the
lower electrode formation region using the first metal layer as a
seed layer, removing the etching barrier film and the dummy pattern
and performing a wet cleaning process to remove residue resulting
from removing the etching barrier film and the dummy pattern, and
removing the exposed first metal layer to form a lower
electrode.
[0025] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are intended to provide further explanation of
the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The invention will be described in detail with reference to
the following drawings in which like reference numerals refer to
like elements wherein:
[0027] FIGS. 1A to 1E are sectional views illustrating related art
process steps of forming a capacitor of a semiconductor device;
[0028] FIG. 2A is a photograph showing a storage node after
etch-back of an etching barrier film;
[0029] FIG. 2B is a photograph showing a storage node after wet
deep-out of a dummy pattern;
[0030] FIGS. 3A to 3H are sectional views of process steps of
forming a capacitor of a semiconductor device according to the
present invention; and
[0031] FIG. 4 is a photograph showing a storage node after removing
residue using a wet cleaning process according to the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0032] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings.
[0033] In the present invention, it is intended that residue
resulting from a process of forming a storage node is removed by a
wet cleaning process and then later processes are performed. In the
wet cleaning process, a cleaning solution that can react with
residue containing a component of a lower electrode formation
material layer to remove the residue is used.
[0034] The process steps of forming a capacitor of a semiconductor
device according to the present invention will be described with
reference to FIGS. 3A to 3H.
[0035] As shown in FIG. 3A, an insulating film 13 and a surface
anti-reflecting film 32 are sequentially formed on a semiconductor
substrate (not shown) in which a cell transistor (not shown) is
formed. A contact hole is formed to connect a capacitor with one
electrode of the cell transistor. The insulating film 31 is formed
of an oxide film while the surface anti-reflecting film 32 is
formed of a material having high etching selectivity, such as a
nitride film, at a thickness of 300.about.1000 .ANG.. A conductive
layer is formed within the contact hole.
[0036] The process for forming the conductive layer within the
contact hole will be described below.
[0037] First, a doped polysilicon layer is deposited within the
contact hole by a CVD process. The doped polysilicon layer is then
etched back to form a recess portion, so that a plug layer 33 is
formed. The recess portion has a depth of 500.about.1500 .ANG..
[0038] Subsequently, a low resistance contact film 34 and a barrier
film 35 are formed in the recess portion so as to reduce contact
resistance between the plug layer 33 and the barrier film 35 which
will be formed later.
[0039] The low resistance contact film 34 is formed in such a
manner that a material such as Ti is deposited on Si at a thickness
of 100.about.300 .ANG. and annealed by a rapid thermal process
(RTP) to form TiSix, and some of Ti which is not reacted with Si is
removed.
[0040] The barrier film 35 is formed in such a manner that any one
of TiN, a three-component based diffusion barrier film, e.g.,
TiSiN, TiAlN, TaSiN, or TaAlN is deposited on the entire surface
including the low resistance contact film 34 by a physical vapor
deposition (PVD) or CVD process and then flattened by a chemical
mechanical polishing (CMP) process to remain on the low resistance
contact film 34.
[0041] Subsequently, Pt is deposited on the entire surface at a
thickness of 50.about.1000 .ANG. to form a first metal layer 36
used as a seed layer. Any one of Ru, Ir, Os, W, Mo, Co, Ni, Au, and
Ag with excellent etching characteristic may be used as the first
metal layer 36.
[0042] As shown in FIG. 3B, a dummy pattern 37 for patterning of a
storage node and an etching barrier film 38 are formed on the
entire surface. A material having high etching selectivity is used
as the dummy pattern 37 and the etching barrier film 38.
[0043] Preferably, the dummy pattern 37 is formed of a photoresist
or a CVD oxide film at a thickness of 5000.about.10000 .ANG. and
the etching barrier film 38 is formed of SiON at a thickness of
100.about.1000 .ANG.. The dummy pattern 37 and the etching barrier
film 38 are selectively etched to form a lower electrode formation
region 39 as shown in FIG. 3C.
[0044] Subsequently, as shown in FIG. 3D, after a pre-cleaning
process for deposition of Pt by the ECD process is performed, a
second metal layer 40 is formed using the first metal layer 36
exposed in the storage node formation region 39, i.e., in a portion
where the dummy pattern 37 is removed, as a seed layer. The second
metal layer 40 is formed by the ECD process.
[0045] Current density during the ECD process is within the range
of 0.1.about.10 mA/cm.sup.2, and DC power, pulse power or reverse
pulse power is used. The second metal layer 40 is formed in the
lower electrode formation region 39 at a height lower than an upper
surface of the dummy pattern 37.
[0046] As shown in FIG. 3E, the etching barrier film 38 on the
dummy pattern 37 is removed by a dry etching process and the dummy
pattern 37 is removed by a wet deep-out process. A mixing solution
of HF or HF/NH.sub.4F is used in the wet deep-out process. Residue
is generated in the process for removing the etching barrier film
38. The residue is removed by the following processes.
[0047] In the process for removing the etching barrier film 38, a
large quantity of residue containing a component of the second
metal layer 40 is generated. The wet cleaning process is performed
using a cleaning solution that can react with the residue to remove
it.
[0048] Preferably, the wet cleaning process is performed in such a
manner that a mixing ratio of H.sub.2SO.sub.4:H.sub.2O.sub.2 is
maintained at 1:0.1.about.1:100, a processing temperature is
4.about.100.degree. C. and dipping time is 2.about.3600 sec. More
preferably, the wet cleaning process is performed for five minutes
at a mixing ratio of 4:1.
[0049] In addition to H.sub.2SO.sub.4:H.sub.2O.sub.2, diluted
H.sub.2SO.sub.4, a mixing solution of
NH.sub.4OH/H.sub.2O.sub.2/H.sub.2O, a mixing solution of
HF/H.sub.2O, and a mixing solution of HF/HN.sub.4F may be used
solely or by sequentially combining them.
[0050] Subsequently, as shown in FIG. 3F, the first metal layer 36
is removed by the dry etch-back process to form a lower electrode
41.
[0051] As shown in FIG. 3G, a high dielectric material, e.g., BST
is deposited on the entire surface at a thickness of 150.about.500
.ANG. within the range of a temperature between 400.degree. C. and
600.degree. C. by the CVD process, so that a dielectric layer 42 is
formed.
[0052] Subsequently, the dielectric layer 42 is crystallized by the
RTP process for 30.about.180 sec under the ambient of N between
500.degree. C. and 700.degree. C., thereby improving dielectric
characteristic.
[0053] As shown in FIG. 3H, Pt is deposited on the dielectric layer
42 by the CVD process and then selectively patterned to form a
capacitor upper electrode 43.
[0054] In the process for forming a capacitor of a semiconductor
device according to the present invention, after the residue
generated when removing the etching barrier film used to obtain the
vertical profile of the dummy pattern for defining the storage node
is completely removed as shown in FIG. 4, later processes are
formed, thereby improving characteristic of the device.
[0055] The method for forming a capacitor of a semiconductor device
according to the present invention has the following
advantages.
[0056] It is possible to completely remove the residue generated
when removing the etching barrier film used to obtain the vertical
profile of the dummy pattern for defining the storage node. In this
case, in a later process, the BST dielectric layer can uniformly be
deposited and uniform capacitance between cells can be obtained.
Also, partially generated loss of current can be reduced, thereby
improving electrical characteristic. Particularly, since a high
stacked Pt storage node can be formed even in a device of 0.1 .mu.m
or less, characteristic of the capacitor that uses BST as a
dielectric film can be improved.
[0057] The foregoing embodiments and advantages are merely
exemplary and are not to be construed as limiting the present
invention. The present teaching can be readily applied to other
types of apparatuses. The description of the present invention is
intended to be illustrative, and not to limit the scope of the
claims. Many alternatives, modifications and variations will be
apparent to those skilled in the art. In the claims,
means-plus-function clauses are intended to cover the structures
described herein as performing the recited function and not only
structural equivalents but also equivalent structures.
* * * * *