U.S. patent application number 09/813011 was filed with the patent office on 2002-02-21 for gate driver multi-chip module.
This patent application is currently assigned to International Rectifier Corporation. Invention is credited to Jauregui, David.
Application Number | 20020021560 09/813011 |
Document ID | / |
Family ID | 22704238 |
Filed Date | 2002-02-21 |
United States Patent
Application |
20020021560 |
Kind Code |
A1 |
Jauregui, David |
February 21, 2002 |
Gate driver multi-chip module
Abstract
A multi-chip module (MCM) provides power circuitry on a computer
motherboard in a package of reduced size without sacrificing
performance. The MCM co-packages essential power circuit components
on a ball grid array (BGA) substrate. Two power MOSFETs disposed on
the BGA substrate are connected in a half-bridge arrangement
between an input voltage and ground. A MOSFET gate driver is
electrically connected to respective gate inputs of the two power
MOSFETs for alternately switching the power MOSFETs to generate an
alternating output voltage at a common output node between the
power MOSFETs. At least one Schottky diode is disposed on the BGA
substrate and connected between the common output node and ground
to minimize losses during deadtime conduction periods. The input
capacitor of the circuit is contained within the MCM housing and is
located close to the MOSFETs, reducing stray inductance in the
circuit. The MCM package is thin and has dimensions of about 1 cm
by 1 cm or less.
Inventors: |
Jauregui, David; (Downey,
CA) |
Correspondence
Address: |
OSTROLENK FABER GERB & SOFFEN
1180 AVENUE OF THE AMERICAS
NEW YORK
NY
100368403
|
Assignee: |
International Rectifier
Corporation
|
Family ID: |
22704238 |
Appl. No.: |
09/813011 |
Filed: |
March 21, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60191125 |
Mar 22, 2000 |
|
|
|
Current U.S.
Class: |
361/760 |
Current CPC
Class: |
H02M 7/003 20130101;
H01L 2924/13091 20130101; H01L 2924/19105 20130101; H01L 2924/19043
20130101; H02M 1/0009 20210501; H01L 2224/48227 20130101; H01L
2924/181 20130101; H01L 2924/12032 20130101; H01L 2924/19041
20130101; H01L 2924/19042 20130101; H01L 2924/00014 20130101; H01L
2924/01006 20130101; Y02B 70/10 20130101; H01L 2223/6611 20130101;
H01L 24/49 20130101; H01L 24/48 20130101; H01L 2924/30105 20130101;
H01L 2924/01027 20130101; H01L 2224/05554 20130101; H01L 2224/49171
20130101; H01L 2924/01015 20130101; H01L 2224/49111 20130101; H01L
2924/30107 20130101; H01L 2924/01021 20130101; H01L 2924/01023
20130101; H01L 2224/48091 20130101; H02M 3/1588 20130101; H01L
2924/014 20130101; H01L 2924/01082 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2224/49111 20130101; H01L
2224/48227 20130101; H01L 2924/00012 20130101; H01L 2224/49171
20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L
2924/12032 20130101; H01L 2924/00 20130101; H01L 2924/181 20130101;
H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L 2224/45099
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101 |
Class at
Publication: |
361/760 |
International
Class: |
H05K 007/02; H05K
007/06 |
Claims
What is claimed is:
1. A multi-chip module (MCM) for providing power circuitry on a
computer motherboard, comprising: a ball grid array (BGA)
substrate; two power MOSFETs disposed on the BGA substrate and
connected in a half-bridge arrangement between an input voltage and
ground; a MOSFET gate driver disposed on the BGA substrate and
electrically connected to respective gate inputs of the two power
MOSFETs for alternatively switching the power MOSFETs to generate
an alternating output voltage at a common output node between the
power MOSFETs; and at least one diode disposed on the BGA substrate
and connected between the common output node and ground to minimize
losses during deadtime conduction periods; and an input capacitor
disposed on the substrate and connected between the input voltage
and ground.
2. The module of claim 1, further comprising another diode
connected in parallel with the diode connected between the common
output node and between the common output node and ground.
3. The module of claim 1, wherein the substrate has an area of
about 1 cm by 1 cm or less.
4. The module of claim 1, wherein the input capacitor is spaced
from the MOSFETs by less than 1 cm.
5. The module of claim 1, wherein the input capacitor is located
adjacent the first and second MOSFETs.
6. The module of claim 1 which further includes an insulation
housing enclosing the substrate, the MOSFETs, the gate driver and
the at least one diode, the ball grid array being exposed through
the bottom of the housing for mounting to a mother board.
7. The module of claim 6, wherein the housing has an area of about
1 cm by 1 cm or less.
8. The module of claim 6, wherein the input capacitor is located
adjacent the first and second MOSFETs.
Description
[0001] This application claims the benefit of U.S. Provisional
Application Serial No. 60/191,125 filed Mar. 22, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a multi-chip module (MCM).
More specifically, the present invention relates to an MCM power
circuit for a computer motherboard.
[0004] 2. Description of the Related Art
[0005] Power supply circuitry typically occupies a substantial area
on a computer motherboard. It would be desirable to reduce the size
of the power circuitry on a computer motherboard without
sacrificing performance.
SUMMARY OF THE INVENTION
[0006] The present invention provides an MCM which includes a
MOSFET gate driver, two power MOSFETs, and associated passive
elements including an input capacitor all mounted on a ball grid
array (BGA) substrate and packaged in a single chip.
[0007] The power MOSFETs of the MCM of the present invention are
connected in a half-bridge arrangement between an input voltage and
ground. The MOSFET gate driver is connected to respective gate
inputs of the two power MOSFETs, and alternately switches the power
MOSFETs to generate an alternating output voltage at a common
output node between the power MOSFETs. At least one Schottky diode
is disposed on the BGA substrate and connected between a common
output node and ground to minimize losses during deadtime
conduction periods.
[0008] The passive circuit components include an input capacitor
connected between the input voltage and ground which provides input
capacitance for the converter. Advantageously, the input capacitor
is physically close to all other components. Additional components
provide appropriate biasing for the gate driver. All components are
encased in a molding compound to form the MCM package.
[0009] By mounting the input capacitor very close to other
components and within the very small package, a number of
advantages are realized, as follows:
[0010] First, there is a very low stray inductance between the
input capacitor and the MOSFETs which reduces the "ring" that would
be caused in the circuit including the MOSFET parasitic capacitance
C.sub.OSS and the stray inductance L. Reducing the inductance
reduces the circuit ring.
[0011] Second, the location of the input capacitor within the MCM
package provides layout independence for the mother board, which no
longer needs to contain that capacitor (at a distance from the
MOSFETs in the MCM package).
[0012] Third, the capacitor acts as a bypass to conduction of
unintended current (with a high di/dt) through the body diode of
one of the MOSFETs in the package and acts to help clamp the
Q.sub.RR (reverse recovery charge) of the MOSFET.
[0013] The module preferably is enclosed in a package that has side
dimensions of about 11 mm.times.11 mm (i.e., about 1 cm.times.1 cm)
or less. Accordingly, the input capacitor is located less than 1 cm
from the MOSFET.
[0014] The MCM of the present invention advantageously results in a
50% reduction in size with no performance trade off and is printed
circuit board (PCB) independent. The package advantageously
provides a performance increase over the discrete solution.
[0015] Other features and advantages of the present invention will
become apparent from the following description of the invention
which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a plan view drawing of the co-packaged active and
passive components in the MCM of the present invention.
[0017] FIG. 2 is an elevation view drawing of an MCM according to
the present invention.
[0018] FIG. 3 is a circuit schematic of an MCM according to the
present invention.
[0019] FIG. 3A is an equivalent circuit diagram of a portion of
FIG. 3.
[0020] FIG. 4 is a timing diagram for an MCM according to the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Referring to FIG. 1, a diagram of a preferred layout for MCM
2 of the present invention is shown. MCM 2 includes six die mounted
on a BGA substrate 4. A plurality of bonding pads 6 are disposed on
the upper surface of substrate 4.
[0022] Die 8 and 10 are power MOSFETs, preferably IRFC7811A and
IRFC7809A power MOSFETs, respectively, mounted in a half-bridge
configuration. Die 12 is a MOSFET gate driver, preferably a Semtech
SC 1405 High Speed Synchronous Power MOSFET Smart Driver. Die 14,
16, and 18 are Schottky diodes, preferably SKM863 diodes, connected
as shown in the circuit schematic of FIG. 3. The active components
mounted on the upper surface of substrate 4 are connected
electrically to corresponding bonding pads 6 using wire bonds
20.
[0023] The passive components shown in FIG. 1 include resistor R1,
and capacitors C1, C2, C3, and C4, also connected as shown in the
circuit schematic of FIG. 3. The passive components are shown
bonded directly to corresponding pads 6. Significantly, capacitor
C4 is mounted close to MOSFETs 8 and 10.
[0024] Referring to FIG. 2, MCM 2 of the present invention is shown
in elevation. A plurality of solder balls 22 are arranged on the
lower surface of substrate 4. In the finished package, the
components on the upper surface of substrate 4 are encapsulated in
a mold compound 24 such as Nitto HC 100. The dimension of housing 2
is about 1 cm.times.1 cm so it will take very little space on a
mother board.
[0025] Referring to FIG. 3, a circuit schematic of power supply MCM
2 is shown. Power MOSFETs 8 and 10 are mounted in a half-bridge
configuration, connected in series between an input voltage
V.sub.IN and ground P.sub.GND. External circuit capacitance
C.sub.EXT is connected to V.sub.IN. A high-side output gate drive
TG of MOSFET gate driver 12 is connected to a gate input 20 of
high-side power MOSFET 8. A low-side output gate drive BG of MOSFET
gate driver 12 is connected to a gate input 22 of low-side power
MOSFET 10. Gate driver 12 alternately switches the power MOSFETs to
generate an alternating output voltage at a common output node SW
NODE between the power MOSFETs.
[0026] Schottky diodes 16 and 18 are connected between common
output node SW NODE and ground to minimize losses during dead time
conduction periods. An input capacitor C4 is connected between the
input voltage V.sub.IN and ground P.sub.GND. The use of two
parallel diodes 16 and 18 helps in keeping a symmetrical layout of
components. An output inductor 30 generally will be connected to
the SW NODE and to the output voltage terminal V.sub.OUT. An output
capacitor C.sub.OUT is also in the output circuit.
[0027] A supply voltage V.sub.DD is provided to MOSFET gate driver
12 on pin V.sub.CC. A bootstrap circuit, consisting of Schottky
diode 14, and resistor R1/capacitor C2 connected between the
bootstrap pin BST and the DRN pin, is provided to develop a
floating bootstrap voltage for high-side MOSFET 8.
[0028] A TTL-level input signal is provided on line DRV_IN to
MOSFET driver pin CO. Operation of the device is enabled by
providing a minimum of 2.0 volts on enable pin EN of MOSFET driver
12. Status pin P.sub.RDY indicates the status of the +5 V supply
voltage. When the supply voltage is less than 4.4 V, this output is
driven low. When the supply voltage is greater than 4.4 V, this
output is driven high. This output has a 10 mA source and 10 .mu.A
capability. When P.sub.RDY is low, undervoltage circuitry built
into driver 12 guarantees that both driver outputs TG and BG are
low.
[0029] Referring to FIG. 4, a timing diagram for MCM 2 is shown. A
turn on delay t.sub.D(ON) of typically 63 ns exists between the
signal input DRV_IN and output SW NODE of MCM 2. A turn off delay
t.sub.D(OFF) of typically 26 ns exists between the signal input
DRV_IN and output SW NODE of MCM 2. A portion of the delay is
inherent in driver 12.
[0030] The supply voltage can range between 4.2 and 6.0 V. Input
voltages of between 5 and 12 volts can be used, providing an output
voltage range of 0.9-2.0 V. Output current is typically 15 A. The
device operates at frequencies from 300-1,000 kHz.
[0031] The operation of the circuit of FIG. 3 is considerably
enhanced by the inherently close spacing between input capacitor C4
and MOSFET 10.
[0032] First, the removal of capacitor C4 from the mother board
increases layout flexibility for the mother board.
[0033] Second, since the capacitor C4 is very close to MOSFETs 8
and 10, the stray inductance in the circuit is reduced in
comparison to that which would be produced with C4 located outside
the chip, on the mother board. This close location (about one
centimeter or less) substantially reduces the "ring" in the
circuit. More specifically, as shown in FIG. 3, MOSFET 10 has a
parasitic capacitance C.sub.OSS. The circuit including the stray
inductance L and C.sub.OSS tends to ring at its resonant frequency.
By reducing L, the ring is also reduced.
[0034] A third benefit of capacitor C4 is that it clamps Q.sub.RR
(reverse recovery charge) of MOSFET 10 and keeps high di/dt from
flowing out of module 2 and into the mother board. More
specifically, FIG. 3A is an equivalent circuit of portions of FIG.
3 showing in particular the body diode of MOSFET 10. During the
dead time, during which both MOSFETs 8 and 10 are off, conduction
takes place through Schottky diodes 16 and 18 of FIG. 3, but some
"residual" current also is conducted through the body diode of
MOSFET 10. When MOSFET 8 turns on while the body diode of MOSFET 10
is conducting, a reverse recovery current will be fed from the
external capacitor C.sub.EXT with very high di/dt. Capacitor C4,
however, will act as a bypass to this high di/dt. The capacitor C4
of FIG. 3 serves similar purposes.
[0035] Although the present invention has been described in
relation to particular embodiments thereof, many other variations
and modifications and other uses will become apparent to those
skilled in the art.
* * * * *