U.S. patent application number 09/919621 was filed with the patent office on 2002-02-14 for method for manufacturing a dual chip package.
This patent application is currently assigned to Samsung Electronics Co. Ltd. Invention is credited to Moon, Sung-Chun.
Application Number | 20020019073 09/919621 |
Document ID | / |
Family ID | 19683092 |
Filed Date | 2002-02-14 |
United States Patent
Application |
20020019073 |
Kind Code |
A1 |
Moon, Sung-Chun |
February 14, 2002 |
Method for manufacturing a dual chip package
Abstract
The present invention discloses a method of manufacturing a dual
chip package using tape wiring boards. According to the method, an
upper tape wiring board, a lower tape wiring board, and a lead
frame are prepared. Each of the tape wiring boards includes a
polymeric tape having windows patterned therein, metal patterns
formed on the lower surface of the polymeric tape at either sides
of said windows. The metal patterns have pad connection portions
exposed through the window. Lead connection portions extend
outwardly from said polymeric tape. An adhesive layer is formed on
the lower surface of the tape. A lower chip is attached to a lower
surface of the die pad. The lower chip includes an active surface
having a plurality of electrode pads at approximately the center
and a rear surface attached to the lower surface of the die pad. An
upper chip is attached to an upper surface of the die pad. The
upper chip includes an active surface having a plurality of
electrode pads at approximately the center and a rear surface
attached to the upper surface of the die pad. Each of the adhesive
layers of the upper tape wiring board and the lower tape wiring
board is attached to a respective one of the active surfaces of the
upper chip and the lower chip. The windows of the lower and upper
tape wiring boards expose the electrode pads of the lower and upper
chips, respectively. Each of the pad connection portions is
attached to a respective one of the electrode pads. Each of the
lead connection portions is attached to a respective one of the
inner leads. Next, the upper chip, the lower chip, the upper wiring
board, and the lower wiring board are encapsulated to form a
package body.
Inventors: |
Moon, Sung-Chun;
(Chungcheongnam-do, KR) |
Correspondence
Address: |
MARGER JOHNSON & McCOLLOM, P.C.
1030 S.W. Morrison Street
Portland
OR
97205
US
|
Assignee: |
Samsung Electronics Co. Ltd
Suwon-city
KR
|
Family ID: |
19683092 |
Appl. No.: |
09/919621 |
Filed: |
July 30, 2001 |
Current U.S.
Class: |
438/107 ;
257/E21.516; 257/E23.033; 257/E23.034; 257/E23.052; 438/109;
438/111 |
Current CPC
Class: |
H01L 24/32 20130101;
H01L 2924/00013 20130101; H01L 2924/014 20130101; H01L 2224/48463
20130101; H01L 2224/9202 20130101; H01L 2224/06136 20130101; H01L
2924/01047 20130101; H01L 2924/01082 20130101; H01L 24/92 20130101;
H01L 2924/01028 20130101; H01L 24/81 20130101; H01L 2224/451
20130101; H01L 2224/45144 20130101; H01L 24/45 20130101; H01L
2224/78301 20130101; H01L 2924/07802 20130101; H01L 2924/181
20130101; H01L 23/49575 20130101; H01L 2224/16235 20130101; H01L
2224/48599 20130101; H01L 2924/1576 20130101; H01L 2224/2919
20130101; H01L 2924/01006 20130101; H01L 2924/0132 20130101; H01L
24/29 20130101; H01L 2924/01005 20130101; H01L 2224/13099 20130101;
H01L 23/4952 20130101; H01L 2924/0665 20130101; H01L 2224/4826
20130101; H01L 2224/29111 20130101; H01L 2224/48247 20130101; H01L
2224/83194 20130101; H01L 2924/01079 20130101; H01L 2224/04042
20130101; H01L 2924/15747 20130101; H01L 24/50 20130101; H01L
2224/32245 20130101; H01L 2924/01029 20130101; H01L 2924/0105
20130101; H01L 24/48 20130101; H01L 25/0657 20130101; H01L 24/86
20130101; H01L 23/49524 20130101; H01L 24/11 20130101; H01L
2224/45155 20130101; H01L 2924/01033 20130101; H01L 24/16 20130101;
H01L 2224/73215 20130101; H01L 2224/05 20130101; H01L 2224/48091
20130101; H01L 2224/0401 20130101; H01L 24/05 20130101; H01L 24/06
20130101; H01L 2224/1131 20130101; H01L 2224/1134 20130101; H01L
2224/29101 20130101; H01L 25/50 20130101; H01L 2224/45144 20130101;
H01L 2924/00014 20130101; H01L 2224/4826 20130101; H01L 2924/00015
20130101; H01L 2224/48091 20130101; H01L 2924/00014 20130101; H01L
2224/451 20130101; H01L 2924/014 20130101; H01L 2224/73215
20130101; H01L 2224/32245 20130101; H01L 2224/4826 20130101; H01L
2924/00015 20130101; H01L 2924/00013 20130101; H01L 2224/13099
20130101; H01L 2924/0665 20130101; H01L 2924/00 20130101; H01L
2924/0132 20130101; H01L 2924/0105 20130101; H01L 2924/01082
20130101; H01L 2224/29111 20130101; H01L 2924/01082 20130101; H01L
2924/00014 20130101; H01L 2924/3512 20130101; H01L 2924/00
20130101; H01L 2224/2919 20130101; H01L 2924/0665 20130101; H01L
2224/4826 20130101; H01L 2224/48463 20130101; H01L 2924/00
20130101; H01L 2224/48599 20130101; H01L 2924/00 20130101; H01L
2924/07802 20130101; H01L 2924/00 20130101; H01L 2924/181 20130101;
H01L 2924/00012 20130101 |
Class at
Publication: |
438/107 ;
438/109; 438/111 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 14, 2000 |
KR |
2000-046944 |
Claims
What is claimed is:
1. A method of manufacturing a dual chip package using tape wiring
boards, comprising: (A) preparing an upper tape wiring board, a
lower tape wiring board, and a lead frame, wherein each of said
tape wiring boards comprises: a polymeric tape having windows
patterned therein, the polymeric tape having a lower and upper
surfaces; metal patterns formed on the lower surface of the
polymeric tape at either sides of said windows, said metal patterns
having pad connection portions exposed through the window, and lead
connection portions extending outwardly from said polymeric tape;
and an adhesive layer formed on the lower surface of the tape; and
wherein said lead frame comprises: a die pad having a low surface
and an upper surface; a plurality of inner leads extending inwardly
toward the die pad; and a plurality of outer leads integrated with
the inner leads and extending outwardly; (B) attaching a lower chip
to the lower surface of the die pad, said lower chip comprising an
active surface having a plurality of electrode pads at
approximately the center and a rear surface attached to the lower
surface of the die pad; (C) attaching an upper chip to an upper
surface of the die pad, said upper chip comprising an active
surface having a plurality of electrode pads at approximately the
center and a rear surface attached to the upper surface of the die
pad; (D) attaching each of the adhesive layers of the upper tape
wiring board and the lower tape wiring board to a respective one of
the active surfaces of the upper chip and the lower chip, wherein
the windows of the lower and upper tape wiring boards expose the
electrode pads of the lower and upper chips, respectively; (E)
electrically connecting each of the pad connection portions to a
respective one of the electrode pads; and (F) electrically
connecting each of the lead connection portions to a respective one
of the inner leads.
2. The method of claim 1, further comprising: (G) molding the upper
chip, the lower chip, the upper wiring board, the lower wiring
board and the inner leads to form a package body.
3. The method of claim 1, wherein the step (E) comprises
electrically connecting the pad connection portions to the
electrode pads by a ball-bonding method using an Au wire.
4. The method of claim 3, wherein the step (E) comprises the
sub-steps of: (E1) electrically connecting each of the pad
connection portions of the lower tape wiring board to a respective
one of the electrode pads of the lower chip; and (E2) electrically
connecting each of the pad connection portions of the upper tape
wiring board to a respective one of the electrode pads of the upper
chip.
5. The method of claim 1, wherein the step (E) comprises
electrically connecting the pad connection portions to the
electrode pads by a dotting method using an adhesive material.
6. The method of claim 5, wherein the step (E) comprises the
sub-steps of: (E1) electrically connecting each of the pad
connection portions of the lower tape wiring board to a respective
one of the electrode pads of the lower chip; and (E2) electrically
connecting each of the pad connection portions of the upper tape
wiring board to a respective one of the electrode pads of the upper
chip.
7. The method of claim 1, wherein the step (E) comprises
electrically connecting the pad connection portions to the
electrode pads by a thermocompression method.
8. The method of claim 7, wherein the step (E) comprises the
sub-steps of: (E1) electrically connecting each of the pad
connection portions of the lower tape wiring board to a respective
one of the electrode pads of the lower chip; and (E2) electrically
connecting each of the pad connection portions of the upper tape
wiring board to a respective one of the electrode pads of the upper
chip.
9. The method of claim 1, wherein the step (E) comprises
electrically connecting the pad connection portions to the
electrode pads by a screen print method.
10. The method of claim 9, wherein the screen print method of step
(E) comprises the sub-steps of: (i) providing a metal paste on the
upper surface of the tape wiring board; (ii) filling up the window
with the metal paste; and (iii) reflowing the metal paste within
the window.
11. The method of claim 9, wherein the step (E) comprises the
sub-steps of: (E1) electrically connecting each of the pad
connection portions of the lower tape wiring board to a respective
one of the electrode pads of the lower chip; and (E2) electrically
connecting each of the pad connection portions of the upper tape
wiring board to a respective one of the electrode pads of the upper
chip.
12. The method of claim 1, wherein the step (F) comprises
electrically connecting each of the lead connection portions to a
respective one of the inner leads by collectively pressing the lead
connection portions of the upper tape wiring board and the lower
tape wiring board into the inner leads by using a thermocompression
method.
13. The method of claim 1, wherein the polymeric tape is formed of
polyimide.
14. A semiconductor package, comprising: a lead frame including: a
die pad having a low surface and an upper surface; a plurality of
inner leads extending inwardly toward the die pad; and a plurality
of outer leads integrated with the inner leads and extending
outwardly; a lower chip attached to the lower surface of the die
pad, said lower chip comprising an active surface having a
plurality of electrode pads at approximately the center and a rear
surface attached to the lower surface of the die pad; an upper chip
attached to an upper surface of the die pad, said upper chip
comprising an active surface having a plurality of electrode pads
at approximately the center and a rear surface attached to the
upper surface of the die pad; an upper and lower tape wiring boards
each including: a polymeric tape having windows patterned therein,
the polymeric tape having a lower and upper surfaces; metal
patterns formed on the lower surface of the polymeric tape at
either side of said windows, said metal patterns having pad
connection portions exposed from the windows, and lead connection
portions extruding from the polymeric tape; and an adhesive layer
formed overlying the metal patterns on each of the upper tape
wiring board and the lower tape wiring board, the adhesive layer
being attached to a respective one of the active surfaces of the
upper chip and the lower chip, wherein the windows of the lower and
upper tape wiring boards expose the electrode pads of the lower and
upper chips, respectively; each of the pad connection portions
electrically connected to a respective one of the electrode pads;
and each of the lead connection portions electrically connected to
a respective one of the inner leads.
15. The package of claim 14, further comprising a molding resin
encapsulating the upper chip, the lower chip, the upper wiring
board, the lower wiring board and the inner leads.
16. The package of claim 14, wherein the polymeric tape is formed
of polyimide.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for manufacturing
semiconductor device packages and, more particularly, to a method
for manufacturing dual chip packages (DCP) comprising two
semiconductor chips.
[0003] 2. Description of the Related Arts
[0004] Recently, semiconductor packaging technologies have been
developed to satisfy demands for high density, increased capacity
and miniaturization in the semiconductor industry. Particularly,
multi-chip packages containing numerous semiconductor chips have
been introduced and widely employed in assembly processes. One such
approach is a stack package on which plural bare chips are
three-dimensionally stacked in a single package.
[0005] FIG. 1 shows a conventional dual chip package 200 comprising
two semiconductor chips, that is, a lower chip 110 and an upper
chip 120. Herein, a lead frame on which the lower chip 110 is
mounted, is referred to as a lower lead frame 130, and a lead frame
on which the upper chip 120 is mounted, is referred to as an upper
lead frame 140.
[0006] The lower chip 110 and the upper chip 120 are respectively
mounted on and electrically wire-bonded to the lower lead frame 130
and the upper lead frame 140. The lower chip 110 and the upper chip
120 are center pad-type chips having electrode pads at the center
of the active surface. The lower chip 110, the upper chip 120, the
lower lead frame 130, the upper lead frame 140, and electrical
connection portions including the bonding wire are all molded with
a molding resin to form a package body 160.
[0007] Because the dual chip package 200 comprises two vertically
stacked semiconductor chips 110, 120 and two vertically stacked
lead frames 130, 140, its thickness is limited by the vertical
dimension of these elements. It is especially difficult to
manufacture a dual chip package having a thickness of about 1,000
mm. Therefore, the overall thickness of the semiconductor chip and
the lead frame needs to be minimized. However, extreme processing
in the thickness of the semiconductor chip causes cracks in or
damage to the semiconductor chip. Extreme processing in the
thickness of the lead frame reduces the reliability of the wire
bonding due to deformation of terminals of the inner leads. So,
there are limits that the conventional DCP structure can achieve on
reducing the thickness of the semiconductor chip and the lead
frame.
[0008] Since lower bonding wires 156 and upper bonding wires 158
are respectively arranged over the lower surface of the lower lead
frame 130 and the upper surface of the upper lead frame 140, the
conventional DCP 200 has a drawback in that the lower bonding wires
156 and the upper bonding wires 158 easily extrude from the package
body 160.
[0009] The inner leads 142 of the upper lead frame 140 and the
inner leads 132 of the lower lead frame 130 are aligned and
attached to each other by thermocompression method, and therefore
attachment technique having high reliability is required. And, the
lower bonding wires 156 extruding from the lower surface of the
lower chip 110 are easily damaged during the manufacturing
process.
[0010] Further, a step of removing the outer leads (not shown) from
the lower lead frame 130 is further required.
SUMMARY OF THE INVENTION
[0011] Accordingly, an object of the present invention is to
provide a method of manufacturing dual chip packages, which
implements a thinner profile by mounting two chips on both sides of
a single lead frame.
[0012] Another object of the present invention is to prevent
package failures due to bonding wires.
[0013] In order to achieve the foregoing and other objects, the
present invention provides a method of manufacturing a dual chip
package using tape wiring boards.
[0014] According to the method, an upper tape wiring board, a lower
tape wiring board, and a lead frame are provided. Each of the tape
wiring boards includes a polymeric tape having windows patterned
therein, metal patterns formed on the lower surface of the
polymeric tape at either sides of said windows. The metal patterns
have pad connection portions exposed through the window. Lead
connection portions extend outwardly from said polymeric tape. An
adhesive layer is formed on the lower surface of the tape. A lower
chip is attached to a lower surface of the die pad. The lower chip
includes an active surface having a plurality of electrode pads at
approximately the center and a rear surface attached to the lower
surface of the die pad. An upper chip is attached to an upper
surface of the die pad. The upper chip includes an active surface
having a plurality of electrode pads at approximately the center
and a rear surface attached to the upper surface of the die pad.
Each of the adhesive layers of the upper tape wiring board and the
lower tape wiring board is attached to a respective one of the
active surfaces of the upper chip and the lower chip. The windows
of the lower and upper tape wiring boards expose the electrode pads
of the lower and upper chips, respectively. Each of the pad
connection portions is attached to a respective one of the
electrode pads. Each of the lead connection portions is attached to
a respective one of the inner leads. Next, the upper chip, the
lower chip, the upper wiring board, and the lower wiring board are
encapsulated to form a package body.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above objectives and advantages of the present invention
will become more apparent by describing in detail a preferred
embodiment thereof with reference to the attached drawings in
which:
[0016] FIG. 1 is a cross-sectional view showing a conventional dual
chip package;
[0017] FIG. 2 is a cross-sectional view showing a dual chip package
in accordance with an embodiment of the present invention;
[0018] FIG. 3 through FIG. 10 illustrate each step of a method of
manufacturing the dual chip package in accordance with an
embodiment of the present invention;
[0019] FIG. 3 is a plan view showing a lead frame of which an upper
chip is attached to a die pad;
[0020] FIG. 4 is a plan view showing a lead frame on which an upper
wiring board is attached to an active surface of the upper
chip;
[0021] FIG. 5 is a cross-sectional view taken along the line I-I in
FIG. 4, which shows electrically connecting each of electrode pads
of the upper chip to a respective one of the pad connection
portions of the upper tape wiring board by a ball-bonding
method;
[0022] FIG. 6 is a cross-sectional view taken along the line I-I in
FIG. 4, which shows electrically connecting each of electrode pads
of the upper chip to a respective one of the pad connection
portions of the upper tape wiring board by a dotting method;
[0023] FIG. 7 is a cross-sectional view taken along the line I-I in
FIG. 4, which shows electrically connecting each of electrode pads
of the upper chip to a respective one of the pad connection
portions of the upper tape wiring board by a thermo-compression
method;
[0024] FIG. 8 is a cross-sectional view taken along the line I-I in
FIG. 4, which shows electrically connecting each of electrode pads
of the upper chip to a respective one of the pad connection
portions of the upper tape wiring board by a screen print
method;
[0025] FIG. 9 is a cross-sectional view taken along the line II-II
in FIG. 4, which shows electrically connecting each of lead
connection portions of the upper tape wiring board to a respective
one of the inner leads;
[0026] FIG. 10 is a cross-sectional view showing a package body
formed by a molding process; and
[0027] FIG. 11 is a cross-sectional view showing a dual chip
package in accordance with another embodiment of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] Preferred embodiments of the present invention will be
described below with reference to the accompanying drawings.
[0029] FIG. 2 is a cross-sectional view showing a dual chip package
100 in accordance with one embodiment of the present invention. The
dual chip package 100 comprises a lead frame 40, a lower chip 10,
an upper chip 20, a lower tape wiring board 70, an upper tape
wiring board 80, and a package body 60.
[0030] The lead frame 40 comprises a die pad 46, a plurality of
inner leads 42 extending toward, preferably coplanar with, the die
pad 46, and a plurality of outer leads 44 integrated with the inner
leads 42 and extruding from the package body 60. Herein, the outer
leads 44 are preferably bent in a gull-wing shape.
[0031] The lower chip 10 comprises an active surface having a
plurality of electrode pads 12 at approximately the center, and a
rear surface attached to the lower surface of the die pad 46. The
upper chip 20 also comprises an active surface having a plurality
of electrode pads 22 at approximately the center, and a rear
surface attached to the upper surface of the die pad 46. In case of
using the lower chip 10 and the upper chip 20, which are the same
as each other, the lower chip 20 and the upper chip 20 are
symmetrical to each other.
[0032] The lower tape wiring board 70 is attached to the active
surface of the lower chip 10 and electrically connects the
electrode pads 12 of the lower chip 10 to the inner leads 42. The
upper tape wiring board 80 is attached to the active surface of the
upper chip 20 and electrically connects the electrode pads 22 of
the upper chip 20 to the inner leads 42.
[0033] The lower chip 10, the upper chip 20, the lower tape wiring
board 70, the upper tape wring board 80, and the inner leads 46 are
encapsulated with a liquid molding resin to form the package body
60.
[0034] The upper tape wiring board 80 comprises a polymeric tape,
for example, a polyimide tape 82, conductive patterns, e.g., metal
patterns 84, and an adhesive layer 86. A plurality of windows 83
are formed through the polyimide tape 82, so that each of the
windows 83 corresponds to (expose) a respective one of the
electrode pads 22. The metal patterns 84 are formed on the lower
surface of the polyimide tape 82 at either side of the windows 83.
The metal patterns 84 comprise one terminals extending over the
windows 83 and serving as pad connection portions 87 electrically
connected to the electrode pads 22. The other terminals extruding
from the polyimide tape 82 and serving as lead connection portions
85 are attached to the inner leads 42. The adhesive layer 86 is a
non-conductive adhesive and attaches the lower surface of the
polyimide tape 82 to the active surface of the upper chip 20.
Preferably, a double-sided adhesive polyimide tape or a liquid
non-conductive adhesive is used as the adhesive layer 86.
[0035] Each of the pad connection portions 87 exposed through the
window 83 is electrically connected to a respective one of the
electrode pads 22 through a corresponding pad connection terminal
81. The pad connection terminals 81 are preferably made of
conductive materials such as gold (Au), solder, nickel (Ni), or
silver (Ag).
[0036] The lower tape wiring board 70 comprises a polyimide tape
72, metal patterns 74, and an adhesive layer 76. A plurality of
windows 73 are formed through the polyimide tape 72, so that each
of the windows 73 corresponds to (exposes) a respective one of the
electrode pads 12. The metal patterns 74 are formed on the lower
surface of the polyimide tape 72 on either side of the windows 73.
The metal patterns 74 comprise one terminals extending over the
windows 73 and serving as pad connection portions 77 attached to
the electrode pads 12, and the other terminals extending outwardly
from the polyimide tape 72 and serving as lead connection portions
75 attached to the inner leads 42. The adhesive layer 76 is a
nonconductive adhesive and attaches the lower surface of the
polyimide tape 72 to the active surface of the lower chip 10.
Preferably, a double-sided adhesive polyimide tape or a liquid
non-conductive adhesive is used as the adhesive layer 86.
[0037] Each of the pad connection portions 77 exposed from the
window 73 is electrically connected to a respective one of the
electrode pads 12 by a corresponding pad connection terminal 71.
The pad connection terminals 71 are also made of conductive
material such as gold (Au), solder, nickel (Ni), or silver
(Ag).
[0038] In the dual chip package 100, the lower chip 10 and the
upper chip 20 are arranged on the lower surface and the upper
surface of the die pad 46 of a single lead frame 40, respectively.
The electrode pads 12 or 22 of the lower chip 10 or the upper chip
20 are electrically connected to the inner leads 42 through the
lower tape wiring board 70 or the upper tape wiring board 80
instead of bonding wires. Therefore, the minimized package 100 with
a thinner profile can be manufactured by using thinner tape wiring
boards 70, 80. Further, package failures due to damaged bonding
wires can be prevented.
[0039] A method for manufacturing the dual chip package is
described below in reference with FIG. 3 through FIG. 10.
[0040] First, the manufacturing process of the dual chip package
100 starts with preparing the lead frame (40 in FIG. 3) and the
tape wiring board (80 in FIG. 4).
[0041] As shown in FIG. 3, the lead frame 40 comprises the die pad
46, a plurality of inner leads 42 extending toward the die pad 46,
and a plurality of outer leads 44 integrated with the inner leads
42 and extending toward the outside. The die pad 46 is connected to
the side rail 45 by tie bars 43. The inner leads 42 and the outer
leads 44 are connected to each other and supported by dam bars 47
traversing the inner leads 42 and the outer leads 44, and both
terminals of the dam bars 47 are connected to the side rails 45.
Although this embodiment of the present invention discloses the
lead frame 40 having the inner leads 42 arranged at two sides, a
lead frame having inner leads arranged at four sides may be
used.
[0042] The lead frame 40 is preferably made of Fe alloy or Cu alloy
and has a thickness of about 100 mm.
[0043] As shown in FIG. 4, the lower tape wiring board 70 of FIG. 2
and the upper tape wiring board 80 are manufactured by
photolithography. In the upper tape wiring board 80, the metal
patterns 84 and the adhesive layer 86 (not shown) are formed on the
lower surface of the polyimide tape 82. The metal patterns 84 are
formed by patterning a metal foil attached to the lower surface of
the polyimide tape 82. Herein, the metal foil is preferably a Cu
foil. A plurality of the windows 83 are formed through the
polyimide tape 82. The windows 83 correspond to the electrode pads
22 of the upper chip 20 so that the pad connection portions 87 are
exposed from the windows 83. Preferably, the window 83 has a size
greater than that of the electrode pad 22. For example, in case of
electrode pad 22 having a size of 90.about.100
mm.times.90.about.100 mm and a pitch of 200.about.250 mm, the
window 83 has a size of 100.about.110 mm.times.100.about.110 mm and
a pitch of 200.about.250 mm.
[0044] So as to expose the lead connection portions 85 connected to
the inner leads 42, portions of the polyimide tape 82 covering the
lead connection portions 85 are removed. Then, the adhesive layer
(not shown) is formed on the lower surface of the polyimide tape 82
having the metal patterns 84. The adhesive layer is a
non-conductive adhesive and attaches the lower surface of the
polyimide tape 82 to the active surface of the upper chip 20, and
preferably uses a liquid non-conductive adhesive or a double-sided
polyimide tape. It is also preferable that the low thermal adhesive
layer made of solder comprising Sn and Pb in a rate of
approximately 85:15 is formed on the outer surfaces of the lead
connection portions 85 in order to more firmly attach to the inner
leads 42.
[0045] In the tape wiring board 80, the polyimide tape 82 has a
thickness of 50.about.70 mm. The metal patterns 84 has a thickness
of 10.about.20 mm and the adhesive layer has a thickness of
20.about.50 mm. The lower tape wiring board 70 is the same
configuration as the upper tape wiring board 80, thus a
manufacturing process of the upper tape wiring board 70 is
omitted.
[0046] As shown in FIG. 3, the lower chip (10 in FIG. 2) is
attached to the lower surface of the die pad 46 and the upper chip
20 is attached to the upper surface of the die pad 46. The lower
chip 10 and the upper chip 20 are center pad type chips. Herein,
each of the lower chip 10 and the upper chip 20 has a thickness of
approximately 200 mm, each of the electrode pads 12, 22 has a size
of 90.about.100 mm.times.90.about.100 mm and a pitch of
200.about.250 mm. The adhesive layer attaching the lower chip 10
and the upper chip 20 to the die pad 46 has a thickness of
approximately 20 mm, and is preferably made of an Ag-epoxy
adhesive.
[0047] As shown in FIG. 4, the lower tape wiring board (70 in FIG.
2) is attached to the active surface of the lower chip (10 in FIG.
2) and the upper wiring board 80 is attached to the active surface
of the upper chip 20. These attachments between the chip 10, 20 and
the tape wiring board 70, 80 can be carried out separately or
concurrently. Herein, the electrode pads 12, 22 are exposed from
the windows 73 83 and the lead connection portions 75, 85
correspond to the inner leads 42.
[0048] FIG. 5 shows the electrical connections between the
electrode pads 22 of the upper chip 20 and the pad connection
portions 87 of the upper tape wiring board 80 by ball bonding
method using an Au wire 81a. According to the ball bonding method
of the present invention, a capillary 91 is aligned over the window
83 of the upper tape wiring board 80. A ball 81b is then from the
wire 81a exposed from the capillary. The pad connection portions 87
are electrically connected to the electrode pads 22 by a pad
connection terminal 81 in a ball shape.
[0049] After completing the ball-bonding process between the
electrode pads 22 of the upper chip 20 and the upper tape wiring
board 80, the lead frame 40 is reversed, and the ball-bonding
process between the electrode pads 12 of the lower chip 10 and the
lower tape wiring board 70 is carried out.
[0050] FIG. 6 shows the electrical connection between the electrode
pads 22 of the upper chip 20 and the pad connection portions 87 of
the upper tape wiring board 80 by a dotting method using a
conductive material 81c. According to the dotting method of the
present invention, a dispenser 93 containing the conductive
material 81c with a predetermined viscosity, e.g., an about
8,000.about.14,000 cp is aligned over the window 83 of the upper
tape wiring board 80. The conductive material 81c is dotted into
the window 83 to electrically connect the pad connection part 87 to
the electrode pad 22 by the pad connection terminal 81. It is
preferable to use the conductive material 81c with a predetermined
viscosity high enough to prevent shorts among the neighboring
electrode pads 22.
[0051] If an adhesive layer 86 is formed between the neighboring
electrode pads 22, the conductive material 81c has broader
variations in viscosity.
[0052] FIG. 7 shows the electrical connection between the electrode
pads 22 of the upper chip 20 and each of the pad connection
portions 87 of the upper tape wiring board 80 by a
thermocompression method. By the thermocompression method, the pad
connection part 87 exposed from the window 83 of the upper tape
wiring board 80 is heated and pressed by a first bonding tool 95 to
electrically connect the pad connection portions 87 to the
electrode pads 22. Although the pad connection portions 87 are
electrically connected to the electrode pads 22 by the first
bonding tool 95 one by one, a gang bonding tool, which collectively
connects a plurality of the pad connection portions 87 to the
electrode pads 22 may be used.
[0053] FIG. 8 shows the electrical connection between the electrode
pads 22 of the upper chip 20 and the pad connection portions 87 of
the upper tape wiring board 80 by a screen print method. According
to the screen print method of the present invention, a metal paste
81d is provided on the upper surface of the upper tape wiring board
80, filling up the window 83 with the metal paste 81d using a
squeegee 87. The pad connection terminal is formed by reflowing the
metal paste 81d. Herein, Ag-paste is preferably used as the metal
paste 81d.
[0054] After completing the thermocompression method in FIG. 7,
another bonding method in FIG. 5, FIG. 6 or FIG. 7 may be further
carried out.
[0055] As shown in FIG. 9, the lead connection portions 75, 85 of
the lower tape wiring board 70 and the upper tape wiring board 80
are collectively gang bonded to the inner leads 42. The lead
connection portions 75, 85 are electrically connected to the inner
leads 42 by a thermocompression method using a second bonding tool
99. Herein, the thermocompression method is carried out at the
temperature of approximately 250.about.300.degree. C. and the
pressure of approximately 10.about.50 kgf for 1.about.3 sec. At
this time, a low thermal adhesive layer is formed on the lead
connection portions 75, 85, and thereby the lead connection
portions 75, 85 are more firmly connected to the inner leads 42.
Although these electrical connections between the inner leads and
the lead connection portions are collectively achieved, the
electrical connections between the inner leads and the lead
connection portions may be achieved one-by-one.
[0056] As shown in FIG. 10, the package body 60 is formed. In order
to protect the lower chip 10, the upper chip 20, the lower tape
wiring board 70, the upper tape wiring board 80, the inner leads 42
and the die pad 46 from external environment, these elements are
encapsulated within a molding resin by a transfer mold method to
form the package body 60. Preferably, the molding resin is an epoxy
molding compound (EMC), and the molding process is carried out at
the temperature of 170.about.200.degree. C. for 40.about.80
sec.
[0057] In a trimming/forming step, the outer leads 44 extruding
from the package body 60 are bent to be easily mounted on a
substrate, and thereby the dual chip package 100 in FIG. 2 is
manufactured.
[0058] In accordance with a first embodiment of the present
invention, since the dual chip package (DCP) comprises only a
single lead frame and the pad connection terminals in bump type
instead of the bonding wires, it is possible to reduce the overall
thickness of the package. The total thickness of the chips, the
lead frame and tape wiring boards is reduced as a thickness of
740.about.920 mm.
[0059] Although the first embodiment of the present invention
comprises the bonding step of the inner leads 42 and the molding
step, which are carried out separately, the two steps may be
carried out concurrently. As shown in FIG. 11, during the molding
step, lead connection portions 275, 285 are electrically connected
to inner leads 242 by using the pressure and the heat of the upper
and the lower mold die (not shown). For example, the inner leads
bonding step and the molding step are carried out at the
temperature of 170.about.200.degree. C. and the pressure of
80.about.100 ton for 40.about.80 sec. Herein, the lead connection
portions 275, 285 partially extend outwardly from a package body
260. The configurations of other elements of the second embodiment
are the same as those of the first embodiment, and therefore their
detail descriptions are omitted.
[0060] In accordance with the preferred embodiments of the present
invention, two chips are arranged on a single lead frame and the
chips are electrically connected to the inner leads of the lead
frame by tape wiring boards. Therefore, the dual chip package
manufactured by the present invention implements miniaturization by
creating a thinner package profile. Further, since the present
invention employs only a single lead frame instead of two lead
frames, it reduces the production cost.
[0061] Although preferred embodiments of the present invention have
been described in detail hereinabove, it should be understood that
many variations and/or modifications of the basic inventive
concepts herein taught which may appear to those skilled in the art
will still fall within the spirit and scope of the present
invention as defined in the appended claims.
* * * * *