Method for fabricating a capacitor in a semiconductor device

Abstract

A method for fabricating a capacitor of a semiconductor device, comprising the steps of forming a seed layer over a semiconductor substrate, forming multiple oxide layers on the seed layer, wherein wet etching of the multiple oxide layer decreases as the layer go up, forming a first opening exposing the seed layer by selectively dry etching the multiple oxide layer, forming a second opening by wet etching the lateral surface of the first opening where is the width of the first opening is expanded, wherein the lower part of the second opening is larger than the upper part, forming a bottom electrode on the seed layer exposed at the bottom of the second opening, whereby the bottom electrode has an identical shape with the second opening, wherein the bottom electrode is formed with the ECD (Electro-Chemical Deposition) technique, exposing the seed layer by removing the multiple oxide layer, removing the exposed seed layer, forming a dielectric layer on the bottom electrode and forming a top electrode on the dielectric layer.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method for manufacturing a capacitor in a semiconductor device; and, more particularly, a method for fabricating a capacitor having a bottom electrode, of which on upper part is smaller than a lower part.

DESCRIPTION OF THE PRIOR ART

[0002] An ECD (Electro-Chemical Deposition) technique is used to deposit the Pt layer for a bottom electrode of a capacitor, of which size is decreased according to the increase of the integration density of the semiconductor device. To form the Pt layer for the bottom electrode, a Pt seed layer is formed on a semiconductor substrate, on which a predetermined lower structure is formed, and an oxide layer pattern having an opening exposing the Pt seed layer is formed. The Pt layer is deposited on the Pt seed layer exposed in the opening.

[0003] At this time, a profile of a bottom electrode is determined by a profile of the opening in the oxide pattern formed by dry etch. The opening has the profile that the lower part of the opening is relatively smaller than the upper part, by the characteristic of dry etch. As described in FIG. 1, the lower part of the bottom electrode is smaller than the upper part, according to the profile of the opening. Thereby, the electrical characteristics of capacitor are deteriorated, because the step coverage of the dielectric layer and the top electrode, deposited on the bottom electrode, is poor.

SUMMARY OF THE INVENTION

[0004] It is, therefore, an object of the present invention to provide a method for fabricating a capacitor improving an electrical characteristic in a semiconductor device.

[0005] In accordance with an aspect of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a seed layer over a semiconductor substrate; forming multiple oxide layers on the seed layer, wherein wet etching rate of the multiple oxide layer decreases as the layer go up; forming a first opening exposing the seed layer by selectively dry etching the multiple oxide layer; forming a second opening by wet etching the lateral surface of the first opening where is the width of the first opening is expanded, wherein the lower part of the second opening is larger than the upper part; forming a bottom electrode on the seed layer exposed at the bottom of the second opening, whereby the bottom electrode has an identical shape with the second opening, wherein the bottom electrode is formed with the ECD (Electro-Chemical Deposition) technique; exposing the seed layer by removing the multiple oxide layer by wet etching; removing the seed layer by dry etching; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0007] FIGS. 1 to 5 are cross-sectional views showing a capacitor fabricating process of a semiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, a method for fabricating a capacitor of a semiconductor device according to the present invention will be described in detail referring to the accompanying drawings.

[0009] As described in FIG. 1, an insulating layer 12 and a reflecting protection layer 13 are formed on a semiconductor substrate 11, on which a predetermined structure has been formed. The reflecting protection layer 13 is formed with a material of which etching selectivity is higher than the insulating layer 12. The insulating layer 12 is formed with an oxide layer and the reflecting protection layer 13 is formed with an oxide-nitride layer (SION) according to the preferred embodiment of the present invention.

[0010] Next, a contact hole, exposing a predetermined region of the semiconductor, is formed by selectively etching the reflecting protection layer 13 and the insulating layer 12. Therefore, a polysilicon layer is formed on the entire structure, at thickness of 500 .ANG. to 3000 .ANG., and then a polysilicon plug 14 is formed through a blanket etching process until the polysilicon is remained only in the contact hole at depth of 500 .ANG. to 2000 .ANG. from the upper surface of the reflection protecting layer 13.

[0011] A Ti layer is formed on the entire structure, including the polysilicon plug 14, at thickness of 100 .ANG. to 300 .ANG.. A thermal treatment is performed to form TiSi.sub.x 15 layer on the polysilicon plug 14 by the reaction between the surface of the polysilicon plug 14 and the Ti layer. Thereafter, the Ti layer remaining on the reflecting protection layer 13 is removed by a wet etching process.

[0012] A diffusion barrier layer 16 is formed on the entire structure for completely burying the contact hole. The diffusion barrier layer 16 is formed with one of TiN layer, TiSiN layer, TiAlN layer, TaSiN layer or TaAlN layer. A CMP process is performed until the upper surface of the reflecting prevention layer is revealed, thereby the diffusion barrier layer 16 remains only on the TiSix layer 15 in the contact hole.

[0013] A seed layer 17 for forming a Pt layer is formed on the reflecting protection layer 13 and the diffusion barrier layer 16. The seed layer 17 is formed with one of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au or Ag at thickness of 50 .ANG. to 1000 .ANG..

[0014] As described in FIG. 2, a first oxide layer 18 and a second oxide layer 19 are successively formed on the seed layer 17. Even if the oxide layer is formed with double steps according to the preferred embodiment of the present invention, the oxide layer can be formed with multiple layers, such as triple layer and so on.

[0015] In the multiple oxide layers, the wet etching rate of each layer decreases as the layers go up. Namely, in case of forming the double oxide layers according to the preferred embodiment of the present invention, the wet etching rate of the first oxide layer 18 is faster than that of the second oxide layer 19.

[0016] In order to decrease the wet etching rates of the multiple oxide layers, as the layers go up, two methods of forming the multiple oxide layers may be used. One method is to decrease the dopant concentration of multiple oxide layers, as the layers go up. The other method is to increase the deposition temperature of multiple oxide layers, of each layer is doped with an identical dopant, as the layers go up. The multiple oxide layers are doped with at least one of B, P, As or Ga. Total thickness of the multiple oxide layer is 500 .ANG. to 20000 .ANG. in the preferred embodiment of the present invention.

[0017] A first opening 31 exposing the seed layer 17 is formed by selectively dry-etching.

[0018] As shown in FIG. 3, the second oxide layer 19 and the first oxide layer 18 are etched, by using wet etchant, to form a second opening 32, which is larger than the first opening. The first oxide layer 18 is etched more rapidly than the second oxide layer 19 in the etching process, because the etch rate of the first oxide layer 18 is faster than that of the second oxide layer 19. Thereby, it is possible to obtain the second opening 32, of which the lower part is larger than the upper part. The second oxide layer 19 and the first oxide layer 18 are etched with a mixed solution of HF and H.sub.2O, or a mixed solution of NH.sub.4F and H.sub.2O, at temperature of 4.degree. C. to 80 .degree. C., for 1 second to 3600 seconds, according to the preferred embodiment of the present invention. The volume of H.sub.2O is less than 1000 times of the volume of the HF solution, in the mixed solution of HF and H.sub.2O, and the volume of NH4F is less than 500 times of the volume of the mixed solution of NH.sub.4F and HF.

[0019] Subsequently, a first metal layer is formed on the seed layer 17 by using an ECD technique, and the first metal layer is completed with wet etching of the first oxide layer 18 and second oxide layer 19. The first metal layer is formed with one of Ru, Ir, Os, W, Mo, Co, Ni, Au or Ag layer at condition of current density of 0.1 mA/cm.sup.2 to 10 mA/cm.sup.2.

[0020] It is possible to form the bottom electrode, of which lower part is larger than the upper part, by forming the first metal layer in the second opening 32, of which lower part is also larger than the upper part. The bottom electrode of the capacitor fabricated according to the present invention is shown in FIG. 3.

[0021] As described in FIG. 4, the seed layer 17 is exposed by removing the multiple oxide layers and the exposed seed layer 17 is removed for insulation between bottom electrodes.

[0022] As described in FIG. 5, a dielectric layer 21 is formed on the entire structure including the bottom electrode, and a rapid thermal annealing process is implemented for improving a dielectric characteristic. A second metal layer, e.g., Pt layer, is formed on the dielectric layer 21 and a top electrode 22 is formed by patterning the second metal layer. The dielectric layer 21 is formed with a (Ba, Sr)TiO.sub.3 (BST) layer at temperature of 300.degree. C. to 600.degree. C., to thickness of 150 to 500. Also, the rapid annealing process is implemented at nitrogen gas atmosphere of temperature of 500.degree. C. to 700.degree. C. for 30 seconds to 180 seconds in the ambient of nitrogen. The second metal layer is formed by using a CVD technique or a sputtering technique.

[0023] As described in the above, when the dielectric layer and the top electrode are formed on the bottom electrode according to the present invention, the characteristic of the step coverage may be improved and, also, an electrical characteristic of the device may be improved.

[0024] While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

What is claimed is:

1. A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a seed layer over a semiconductor substrate; forming multiple oxide layers on the seed layer, wherein wet etching rate of the multiple oxide layer decreases as the layer go up; forming a first opening exposing the seed layer by selectively dry etching the multiple oxide layer; forming a second opening by wet etching the lateral surface of the first opening where is the width of the first opening is expanded, wherein the lower part of the second opening is larger than the upper part; forming a bottom electrode on the seed layer exposed at the bottom of the second opening, whereby the bottom electrode has an identical shape with the second opening, wherein the bottom electrode is formed with the ECD (Electro-Chemical Deposition) technique; exposing the seed layer by removing the multiple oxide layer by wet etching; removing the seed layer by dry etching; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer.

2. The method as recited in claim 1, wherein the seed layer is formed with a material selected from the group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au and Ag layer.

3. The method as recited in claim 1, wherein the bottom electrode is formed with a material selected from the group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au and Ag layer.

4. The method as recited in claim 1, wherein the bottom electrode is formed at a current density of 0.1 mA/cm.sup.2 to 10 mA/cm.sup.2.

5. The method as recited in claim 1, wherein the multiple oxide layers are formed step by step by decreasing concentration of dopant in each layer of the multiple oxide layers.

6. The method as recited in claim 5, wherein the dopant is a material selected from the group consisting of B, P, As and Ga.

7. The method as recited in claim 1, wherein the wet etching is performed at a temperature of 4.degree. C. to 80.degree. C. for 1 second to 3600 seconds.

8. The method as recited in claim 7, wherein the wet etching is performed by using HF contained solution.

9. The method as recited in claim 8, wherein the wet etching is performed by using mixed solution of the HF solution and H.sub.2O, wherein the volume of H.sub.2O is less than 1000 times of the volume of the HF solution.

10. The method as recited in claim 9, wherein the wet etch is performed by using a mixed solution of the NH.sub.4F solution and HF, wherein the volume of NH.sub.4F is less than 500 times of the volume of the NH.sub.4F/HF solution.

11. The method as recited in claim 1, wherein the multiple oxide layers are formed by increasing, step by step, depositing temperature of each layer of the multiple oxide layers, wherein each layer of the multiple oxide layers have an identical dopant concentration.

12. The method as recited in claim 11, wherein the dopant is a material selected from the group consisting of B, P, As and Ga.

13. The method as recited in claim 12, wherein the wet etching is performed at a temperature of 4.degree. C. to 80.degree. C. for 1 second to 80 seconds.