U.S. patent application number 09/921210 was filed with the patent office on 2002-02-07 for digital ramp generator with output power level controller.
This patent application is currently assigned to Nokia Networks Oy. Invention is credited to Honkanen, Mauri, Vankka, Jouko.
Application Number | 20020014983 09/921210 |
Document ID | / |
Family ID | 8555702 |
Filed Date | 2002-02-07 |
United States Patent
Application |
20020014983 |
Kind Code |
A1 |
Honkanen, Mauri ; et
al. |
February 7, 2002 |
Digital ramp generator with output power level controller
Abstract
Simplifying functions representing raised sine or cosine curves
to functions representing simple sine or cosine curves makes it
possible to implement an electrical equivalent circuit for a ramp
generator. The core of the ramp generator with an output power
level controller is second-order direct-form feedback structure
(60), which forms a digital sinusoidal oscillator. The initial
values of two state variables x.sub.2(n), x.sub.2(n+1) of the
oscillator are chosen so that they both contain a predetermined
first constant value. This first constant value will emerge as the
amplitude value of the pure sine wave generated by the oscillator.
Particularly the first constant value is equal to the desired
nominal level A of the ramp minus the starting level. A second
constant value (A+dc) is added to the oscillator output. The added
result is scaled (66) so that the nominal power level is A. A
multiplexer (67) keeps the power level between the ramps
constant.
Inventors: |
Honkanen, Mauri; (Tampere,
FI) ; Vankka, Jouko; (Helsinki, FI) |
Correspondence
Address: |
Altera Law Group, LLC
6500 City West Parkway - Suite 100
Minneapolis
MN
55343-7701
US
|
Assignee: |
Nokia Networks Oy
Espoo
FI
|
Family ID: |
8555702 |
Appl. No.: |
09/921210 |
Filed: |
August 2, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09921210 |
Aug 2, 2001 |
|
|
|
PCT/FI00/01065 |
Dec 1, 2000 |
|
|
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Current U.S.
Class: |
341/147 |
Current CPC
Class: |
H03B 28/00 20130101 |
Class at
Publication: |
341/147 |
International
Class: |
H03M 001/66 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 3, 1999 |
FI |
19992614 |
Claims
1. A method of producing a curve in a digital ramp generator, the
curve comprising, a rising ramp starting from a base power level dc
and ending at a nominal power level A, the rising ramp being in the
form 20 ( A - d c ) sin ( t 2 T r ) 2 + d c ,where T.sub.r is the
ramp time, a falling ramp starting from the nominal power level A
and ending at the base level dc, the falling ramp being in the form
21 ( A - d c ) cos ( t 2 T r ) 2 + d c ,where T.sub.r is the ramp
time a flat portion between the rising ramp and the failing ramp at
the nominal power level, characterized in steps of: using
trigonometric identities the form of the rising ramp is transformed
into form 22 1 2 ( ( A + d c ) + ( A - d c ) cos ( t T r + ) ) .
,using trigonometric identities the form of the falling ramp is
transformed into form 23 1 2 ( ( A + d c ) + ( A - d c ) cos ( t T
r ) ) ,and providing a digital sinusoidal oscillator for computing
the cosine terms.
2. A method as in claim 1, further comprising the step of realizing
the digital sinusoidal oscillator by a second order direct-form
recursive structure implementing the second-order difference
equation of state variables: x.sub.2(n+2)=2 cos
(2.pi.f.sub.0/f.sub.CLK)x.sub.2(n+1)-x.sub.- 2(n), where f.sub.0 is
the digital sinusoidal oscillator frequency and f.sub.CLK is the
sampling frequency.
3. A method as in claim 1, further comprising the step of providing
an adder for adding the value A+dc and the output signal of the
digital sinusoidal oscillator.
4. A method as in claim 3, further comprising the step of providing
a scaler for scaling the output signal from the adder by the factor
1/2.
5. A method as in claim 1, further comprising the step of providing
means for sustaining the amplitude of the curve at the nominal
power level A between the rising ramp and the falling ramp.
6. A digital ramp generator including means for producing a curve
comprising, a rising ramp having the shape of a raised sine curve,
the rising ramp starting from a base power level and ending at a
nominal power level, a falling ramp having the shape of a raised
cosine curve, the falling ramp starting from the nominal power
level and ending at the base level, a flat portion between the
rising ramp and the falling ramp at the nominal power level,
characterized in that said means for producing the rising ramp and
the falling ramp of the curve comprise a digital sinusoidal
oscillator generating the rising ramp in the form 24 ( A - d c )
cos ( t T r + ) and the falling ramp in the form 25 ( A - d c ) cos
( t T r ) ,where T.sub.r is the ramp time, A is the nominal power
level, and dc is the base power level; and the digital sinusoidal
oscillator is realized by a second order direct-form recursive
structure, within which the cosine terms are computed and which
implements the second-order difference equation of state variables:
x.sub.2(n+2)=2 cos (2.pi.f.sub.0/f.sub.CLK)x.sub.2(n+1)-x.sub.2(n),
where f.sub.0 is the digital sinusoidal oscillator frequency and
f.sub.CLK is the sampling frequency.
7. A digital ramp generator as in claim 6, characterized in that a
second order direct-form recursive structure comprises a first
digital delay element (61) producing state variable x.sub.2(n+1)
and a second digital delay element (62) producing state variable
x.sub.2(n), the delay elements being connected in series, a first
digital two-input adder (65) producing state variable x.sub.2(n+2)
for applying to the input of the first delay element, a first
digital multiplier (63) for multiplying state variable x.sub.2(n+1)
obtained from the output of the first delay element (61) by factor
2 cos (2.pi.f.sub.0/f.sub.CLK), the output of the first multiplier
being connected to one input of the digital two-input adder, a
second digital multiplier (64) for multiplying state variable
x.sub.2(n) obtained from the output of the second delay element
(62) by factor -1, the output of the second multiplier being
connected to another input of the digital two-input.
8. A digital ramp generator as in claim 7, characterized in that
the initial value of the state variable (x.sub.2(n)) at the output
of the second delay element (62) is A-dc and the initial value of
the state variable x.sub.2(n+1) at the input of the second delay
element (62) is (A-dc) cos (2.pi.f.sub.0/f.sub.CLK), wherein the
unit sample response y(n) of the second order direct-form recursive
structure is a digital sinusoidal equal to (A-dc) cos
(n.sub.x2.pi.f.sub.0/f.sub.CLK).
9. A digital ramp generator as in claim 7, characterized in that
the initial value of the state variable x.sub.2(n) at the output of
the second delay element (62) is (A-dc) cos (.phi..sub.0) and the
initial value of the state variable x.sub.2(n+1) at the input of
the second delay element (62) is (A-dc) cos
(2.pi.f.sub.0/f.sub.CLK+.phi..sub.0), where .phi..sub.0 is an
arbitrary initial offset, wherein the unit sample response y(n) of
the second order direct-form recursive structure is a digital
sinusoidal equal to (A-dc) cos (n.sub.x2.pi.f.sub.0/f.sub.CLK+.ph-
i..sub.0).
10. A digital ramp generator as in claim 6, characterized in that
means for producing a curve further comprises a second digital
two-input adder (68), to one input of which is applied the output
signal from the digital sinusoidal oscillator and to another input
of which is applied a constant having value A+dc, wherein value A
determines the nominal power level of the ramps.
11. A digital ramp generator as in claim 10, characterized in that
the output from the second digital two-input adder (68) is
connected to a scaling element (66), which scales the output signal
from the adder so that the maximum power level is nominal power
level A.
12. A digital ramp generator as in claim 10, characterized in that
means for producing a curve further comprises a controllable
holding element (67), which feeds directly to its output the rising
ramp and the falling ramp obtained from the scaling element, but
holds the power level of its output signal at nominal value A
between the rising ramp and the falling ramp, thus forming the flat
portion between the rising ramp and the falling ramp.
13. A digital ramp generator as in claim 6, characterized in that
in the second-order difference equation of state variables the term
2 cos (2.pi.f.sub.0/f.sub.CLK) is rewritten to form 26 2 - 2 - b1 [
2 b1 ( 2 - cos ( 2 f 0 / f CLK ) ) ] , where b1 = [ log 2 1 2 ( 1 -
cos ( 2 f 0 / f CLK ) ] wherein the state variable x.sub.2(n+1) is
multiplied by two parallel multipliers (73, 74) before adding.
14. A digital ramp generator as in claim 6, characterized in that
the ramp generator is adapted to Blackman window of the form 27
0.42 A + 0.5 A cos ( * t ) T r ) + 0.08 A cos ( 2 * t T r ) for the
falling ramp, and 28 0.42 A + 0.5 A cos ( * T ) T r + ) + 0.08 A
cos ( 2 * t T r ) for the rising ramp.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to a transmitter of
a radio system using burst transmission, and particularly to a ramp
generator for shaping the rise and the fall of a burst and for
controlling the power level of the burst.
BACKGROUND OF THE INVENTION
[0002] A burst is the transmission quantum of numerous digital
radio systems based on the principle of time division duplex (TDD),
frequency division duplex (FDD), and code division duplex (CDD).
The transmission takes place during a short time window. Within
this time interval the emission rises from the starting power level
to the nominal power level. The signal is then modulated to
transmit a packet of bits. After that, the power level decreases
until it reaches the minimum power level. The time mask of the
burst, during which the bits are transmitted, is called a useful
part or a payload part. Modulation is performed in the transmitter
analogically or digitally, either at a base band frequency or at an
intermediate frequency (IF). The modulated IF signal is then mixed
up to the radio transmission frequency.
[0003] FIG. 1 depicts the rising portion of the power envelope of a
burst comprising a digitally modulated intermediate frequency
signal. In this example, during the rise of the burst the envelope
should track a raised sine curve. After a predetermined period the
power has reached its selected nominal level, whereupon modulation
starts. This instant is denoted as 0 in the horizontal time axis.
Usually the transmission power is adjustable according to the
requirement of the system concerned. For that reason the nominal
power level value can vary between the maximum power level and the
minimum power level, as shown by the dofted line and the dashed
line in FIG. 1. The nominal power level between those levels can
usually attain one of several discrete power levels. For example,
the downlink dynamic power control in the GSM system uses 16 power
levels with 2 dB separations.
[0004] FIG. 2 depicts the falling portion of the envelope of a
digitally modulated intermediate frequency signal. The signal
envelope during the fall of the transmission burst should track a
raised cosine curve.
[0005] The power level can be controlled burst by burst. Control is
realized by scaling the ramp curve which follows the raised
sine/cosine curve. Hence, the ramp-up curve starts from the minimum
power level, but settles at the level specified by the power level
indication as shown in FIG. 1. At the end of the burst the
ramp-down curve starts from the nominal power level, but settles at
the minimum power level as shown in FIG. 2.
[0006] Conventionally, power ramping and control of the output
power level are performed in the analog domain. One problem with
analog solutions is inaccuracies caused by aging and by variations
in operation temperature and components. Furthermore, the analog
solutions are complex, and stability is a problem.
[0007] Today the tendency is to perform power ramping and output
power level control digitally in order to avoid the afore-mentioned
problems. Some basic solutions are presented below.
[0008] FIG. 3 illustrates in broad outline the formation of a
modulated IF signal into a shape as shown in FIG. 1 and FIG. 2.
Data symbols arrive at digital modulator 31 that carries out
modulation according to the modulation scheme of the system
concerned. A ramp generator in block 32 generates the rising and
falling edges according to the raised sine/cosine curve and a flat
portion between the curves. Digital output signals from the ramp
generator and the modulator are then converted to analog signals in
digital-to-analog converters 33 and 36: For removing the high
frequency sampling components the analog signals are then filtered
in low pass filters 37 and 38, whereupon the analog modulated
signal is multiplied in analog multiplier 35 by the analog ramp
signal in order to smoothen out the rise and fall of the burst. The
output from the multiplier is the analog modulated IF signal with
ramped power.
[0009] FIG. 4 illustrates another digital modulator. Data symbols
arrive at digital modulator 41, which carries out modulation
according to the modulation scheme of the system concerned and
produces I and Q signals. Said signals are then converted into
analog signals by DA converters 43 and 44. For removing the high
frequency sampling components the analog signals are filtered in
low pass filters 410 and 411, whereupon both the analog I signal
and the analog Q signal are transformed into an intermediate
frequency by mixer 45 and mixer 46, accordingly. After mixing the
sum of I signal and Q signal are added up in analog adder 47 to
form the sum signal. A ramp generator in block 42 generates the
ramp signal, i.e. the rising and falling edges according to the
raised sine/cosine curve and the flat portion between them. The
digital ramp signal is then converted into an analog signal in
converter 48. The high frequency sampling components are filtered
in low pass filter 412, whereupon the analog modulated sum signal
is multiplied in multiplier 49 by the analog ramp signal in order
to smooth out the rise and fall of the IF burst. The output from
the multiplier is the analog modulated IF signal.
[0010] Common to both prior art solutions described above are the
performance of both the modulation and the generation of the ramp
signal digitally but conversion of the digital result signals into
the analog domain before multiplying. However, there is a tendency
in the art to carry out all processes within the digital domain. In
order to better understand one possible realization of the digital
ramp generator, a short review of the mathematical background is of
assistance.
[0011] The burst signal can be considered as a product of an
original modulated signal m(t) and a periodical switching signal
sw(t). The spectrum of the burst signal is the convolution of the
spectra of these two signals in the frequency domain.
[0012] For rectangular switching, i.e. without raised cosine/sine
shaping, formula (1) is valid for frequency response: 1 W ( f ) = M
( f - f C ) * Sw ( f ) = K n = - .infin. .infin. M ( f - f C - nf g
) sin nf g nf g ( 1 )
[0013] where
[0014] * denotes convolution,
[0015] f.sub.c is the carrier frequency,
[0016] f.sub.g is the burst gating rate,
[0017] .tau. is the burst length and
[0018] K is a proportional constant.
[0019] For raised cosine/sine switching, i.e. with raised
cosine/sine shaping, formula (2) is valid for frequency response: 2
W ( f ) = H n = - .infin. .infin. M ( f - f C - nf g ) ( - T r )
sin c ( nf g ( - T r ) ) cos ( T r nf g ) 1 - ( 2 T r nf g ) 2 ( 2
)
[0020] where T.sub.r indicates the ramp duration, and H is
proportional constant..
[0021] The spectrum of the periodic burst signal consists of
infinite numbers of secondary spectral lobes having the same shape
as M(f) separated by the burst gating rate f.sub.g, and having
decreasing amplitudes. Since the secondary spectral lobes resulting
from formula (2) decay faster than those resulting from formula
(1), the raised cosine/sine switching is used.
[0022] The following function is used to smooth out the rise of the
burst: 3 ( A - d c ) sin ( t 2 T r ) 2 + d c , ( 3 )
[0023] where
[0024] T.sub.r indicates the ramp duration,
[0025] t is [O T.sub.r],
[0026] A is the envelope of the modulated signal, and
[0027] dc is the dc offset which settles the starting power level
in FIG. 1.
[0028] The following function (4) is used to smooth out the fall of
the burst: 4 ( A - d c ) cos ( t 2 T r ) 2 + d c . ( 4 )
[0029] FIG. 5 illustrates a ramp generator and an output power
controller known in the art which are based on formulas (3) and
(4). The raised sine values of formula (3) or the raised cosine
values of formula (4) are stored in the read only memory (ROM) 51.
Digital multiplier 52 is used to control the amplitude level, i.e.
value (A-dc). Adder 53 sets the dc offset, i.e. the last factor of
formulas. The size of the ROM memory is about
(f.sub.clk.times.T.sub.r).times.outw, where f.sub.clk is the
digital IF modulator clock frequency (sampling frequency), T.sub.r
is the pulse duration and outw is the multiplier input width.
[0030] One drawback of this known ramp generator is that due to the
high clock frequency in the digital IF modulators, the size of the
memory is large. For example, if the clock frequency is 52 MHz and
the ramp duration is 14 .mu.s, then the size of the memory is about
728.times.12 bit. Furthermore, a multiplier is needed as an extra
component to set the output power level.
[0031] Another possible way to implement the ramp generator and
output power controller is to use a FIR-filter (Finite Impulse
Response). The number of the FIR filter taps is
f.sub.clk.times.T.sub.r, where f.sub.clk is the digital IF
modulator clock frequency and T.sub.r is the pulse duration. One
drawback of filter implementation is that due to the high clock
frequency (sampling frequency) in the IF modulators, there are many
taps in the FIR. Therefore, the realization of raised sine and
cosine functions with filters is complex. For example, with the
above mentioned values, i.e. the clock frequency is 52 MHz and the
ramp duration is 14 .mu.s, the number of the FIR filter taps is
728.
SUMMARY OF THE INVENTION
[0032] One objective of the present invention is to devise a
digital ramp generator with an output power controller that is easy
to implement and which requires a minimum number of standard
components, without the need for raised sine and cosine memories or
digital filters.
[0033] A further objective is to devise a digital ramp generator
with an output power controller generating a digital output signal
that can directly multiply the digital modulated signal produced by
a digital modulator.
[0034] Yet a further objective is to devise a digital ramp with
inherent power control, wherein the generator and power control
form a functionally inseparable integrated unit.
[0035] The present invention is based on a further mathematical
explication of the raised sine and cosine curves representing the
rise and fall of the burst. Simplifying functions representing
raised sine/ cosine curves to functions representing simple sine/
cosine curves makes it possible to implement an electrically
equivalent circuit consisting of a few simple basic components
while tracking the raised sine and cosine functions well.
[0036] The core of the electrical equivalent circuit functioning as
a ramp generator wvith an output power level controller is a
second-order direct-form feedback structure forming a digital
sinusoidal oscillator. The structure is well-known as such, and it
produces an output sequence which is the sampled version of the
pure sine wave with an amplitude value. The initial values of two
state variables of the oscillator are chosen so that they both
contain a predetermined first constant value. This first constant
value will emerge as the amplitude value of the pure sine wave
generated by the oscillator. Particularly the first constant value
is equal to the desired nominal level A of the ramp minus a dc
offset, where the dc determines the starting power level of the
rising ramp and the settling power level after the falling ramp.
The dc offset may also be called as a base level.
[0037] A second constant value equal to the desired nominal level
of the ramp plus the above-mentioned dc offset is added to the
oscillator output. Due to the deliberately chosen first and second
constant values, the adding operation causes the rising ramp to
start from level 2.multidot.dc and to end at level 2.multidot.A.
Accordingly, the adding operation causes the falling ramp to start
from level 2.multidot.A and to end at level 2.multidot.dc.
[0038] Finally, the result will be scaled so that the nominal power
level will be A, and the starting level of the rising ramp and the
end level of the falling ramp will be dc.
[0039] After the ramp has risen to the predetermined nominal power
level, the output power level will be kept constant up to the
instant when the ramp starts falling.
[0040] The proposed digital ramp generator and power controller can
be implemented with the aid of two two-input adders, two delays, a
multiplexer, and a fixed multiplier, which can be constructed with
(N-1) adders, where N is the number of non-zero bits in the
coefficient. The proposed ramp generator and output power
controller saves hardware compared to the conventional methods.
Furthermore, since the proposed ramp generator and output power
level controller needs neither a memory nor a multiplier, it can be
easily implemented with standard cells.
BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The invention is described more closely with reference to
the accompanying drawings, in which
[0042] FIG. 1 shows the rising ramp of a burst;
[0043] FIG. 2 shows the falling ramp of a burst;
[0044] FIG. 3 illustrates a prior art modulator and ramp
generator;
[0045] FIG. 4 depicts another prior art modulator and ramp
generator;
[0046] FIG. 5 shows a prior art digital ramp generator;
[0047] FIG. 6 is a block diagram of the invented ramp
generator;
[0048] FIG. 7 is another embodiment of the invented ramp
generator;
[0049] FIG. 8A shows output error when truncation is used;
[0050] FIG. 8B shows output error when rounding is used;
[0051] FIG. 9 depicts a ramp down profile;
[0052] FIG. 10 depicts a ramp up profile;
[0053] FIG. 11 shows a ramp generator adapted to Blackman window,
and
[0054] FIG. 12 depicts a block diagram of another ramp generator
adapted to Blackman window.
DETAILED DESCRIPTION OF THE INVENTION
[0055] The mathematical background of the invented ramp generator
is founded on further development of known formulas for raised
cosine and sine functions.
[0056] Using trigonometric identities, the previously presented
function (3), which is used for smoothing out the rise of the
burst, can be rearranged as follows: 5 1 2 ( ( A + d c ) + ( A - d
c ) cos ( t T r + ) ) . ( 5 )
[0057] At the time instant t=0 the value of the function is dc, and
at the end of ramp time T.sub.r the value of the function is A.
Hence, dc is the offset value which settles the starting power
level, and A is the power level which the ramp reaches at the end
(see FIG. 1). Therefore, the setting of the output power level of
the ramp generator, i.e. the nominal power level of the burst, can
be done by controlling the value of A. It is essential to note that
in equation (5) the cosine term is not raised, so it can be
implemented by a sinusoidal oscillator.
[0058] Accordingly, using trigonometric identities, function (4),
which is used for smoothing out the fall of the burst, can be
rearranged as follows: 6 1 2 ( ( A + d c ) + ( A - d c ) cos ( t T
r ) ) , ( 6 )
[0059] At the time instant t=0 when the ramp begins to fall, the
value of the function is A, and at the end of ramp time T.sub.r the
value of the function is dc. Hence, dc is the offset value which
settles the power level after the ramp, and A is the power level
from which the ramp begins to fall (see FIG. 1). Also in this
equation the cosine term is not raised, so it can be implemented by
a sinusoidal oscillator.
[0060] FIG. 6 depicts a ramp generator with an output power level
controller which realizes the above-mentioned formulas (5) and (6).
The circuit consists of the digital sinusoidal oscillator 60, adder
68, scaler 66, and MUX 67.
[0061] The core of this structure, the digital sinusoidal
oscillator 60, is a second-order direct-form feedback structure
known as such. It produces the cosine term of equations (5) and (6)
and amplitude A-dc of the cosine term. Adder 68 adds the constant
value A+dc to the oscillator output.
[0062] Operation of the oscillator will now be described in more
detail by explaining the mathematical basis of the operation of the
oscillator with reference to the circuit elements in FIG. 6.
[0063] Digital sinusoidal oscillator 60 producing the cosine term
of formulas (5) and (6) is implemented by the following
second-order difference equation:
x.sub.2(n+2)=.alpha.x.sub.2(n+1)-x.sub.2(n). (7)
[0064] FIG. 6 shows the signal flow graph of the second-order
direct-form feedback structure with state variables x.sub.1(n) and
x.sub.2(n). State variable x.sub.1(n) is the input to delay block
62, and state variable x.sub.2(n) is the output from that block.
Delay block 62 can be implemented with registers. As shown, state
variable x.sub.1(n) is also applied to block 63, which multiplies
it by the coefficient .alpha., whereas state variable x.sub.2(n) is
applied to block 64, which takes negation from input signal, i.e.
multiplies it by the coefficient -1. The outputs from blocks 63 and
64 are fed to the two-input adder 65. The added result, which is
the right-hand part of equation 7, is then applied to delay block
61, which can be implemented with registers. The added result is
denoted as x.sub.2(n+2) in FIG. 6.
[0065] As shown in the figure, the two state variables are related
by the equation:
[0066] x.sub.1(n)=x.sub.2(n+1). (8)
[0067] Solving the one-sided z transform of equation (7) for
x.sub.2(n) leads to formula 7 X 2 ( z ) = ( z 2 - z ) x 2 ( 0 ) +
zx 1 ( 0 ) z 2 - z + 1 , ( 9 )
[0068] where x.sub.1(0) is the initial value of state variable
x.sub.1(n), i.e. the input to delay block 62, and x.sub.2(0) is the
initial value of state variable x.sub.2(n), i.e. the output from
delay block 62.
[0069] Identifying the second state variable as output variable
y(n)=x.sub.2(n), (10)
[0070] as shown in FIG. 6, and choosing the denominator coefficient
.alpha. to be
.alpha.=2 cos .theta..sub.0,
.theta..sub.0=.omega..sub.0T=2.pi..function..-
sub.0/.function..sub.clk, (11)
[0071] where f.sub.0 is the oscillator frequency and f.sub.clk is
the sampling frequency, and choosing the initial values of the
state variables to be
x.sub.1(0)=A.sup.* cos .theta..sub.0, x.sub.2(0)=A.sup.*, where
A.sup.*=A-dc (12)
[0072] we obtain from equation (9) a discrete-time sinusoidal
function as the output signal: 8 Y ( z ) = A * ( z 2 - cos 0 z ) z
2 - 2 cos 0 z + 1 ( 13 )
[0073] This output signal Y(z) has complex-conjugate poles at
z=exp(.+-.j.theta..sub.0), (14)
[0074] and a unit sample response
y(n)=A.sup.* cos (n.theta..sub.0), n.gtoreq.0 (15)
[0075] Thus the impulse response of the second-order system with
complex-conjugate poles on the unit circle is a sinusoidal
waveform.
[0076] An arbitrary initial offset .phi..sub.0 can be realized,
namely,
y(n)=A.sup.* cos (.theta..sub.0n+.phi..sub.0) (16)
[0077] by choosing the initial values:
x.sub.1(0)=A.sup.* cos (.theta..sub.0+.phi..sub.0) (17)
x.sub.2(0)=A.sup.* cos (.phi..sub.0). (18)
[0078] The output frequency of the digital oscillator
(.theta..sub.0) could be altered by changing the coefficient
.alpha. in (11) and the initial value in (17). The above derived
formulas show that any real-valued sinusoidal oscillator signal can
be generated by the second-order structure shown in FIG. 6. The
initial phase offsets of the digital oscillator are 0 for the ramp
down and .pi. for the ramp up. The initial values of state
variables x.sub.1(n) and x.sub.2(n) for these phase offsets are
calculated from equations 17 and 18.
[0079] Hence, for the falling ramp ((.phi..sub.0=0) the initial
values are
x.sub.1(0)=(A-dc) cos (.theta..sub.0)
x.sub.2(0)=(A-dc).
[0080] For the rising ramp (.phi..sub.0=.pi.) the initial values
are
x.sub.1(0)=-(A-dc) cos (.theta..sub.0)
x.sub.2(0)=-(A-dc).
[0081] The initial values for the raising ramp are negation of the
initial values for the falling ramp.
[0082] The output sequence y(n) of the ideal oscillator is the
sampled version of a pure sine wave. The angle .theta..sub.0
represented by the oscillator coefficient is given by
.theta..sub.0=2.pi..function..sub.0T, (19)
[0083] where f.sub.0 is the desired frequency in cycles per second.
In actual implemention, the multiplier coefficient 2 cos
.theta..sub.0 is assumed to have b+2 bits. In particular, one bit
is for the sign, one bit for the integer part, and b bits for the
remaining fractional part in fixed-point number representation.
Then the largest value of the coefficient 2 cos .theta..sub.0.
which can be represented is (2-2.sup.-b). This value of the
coefficient gives the smallest value of .theta..sub.min which can
be implemented by a direct form digital oscillator using b bits: 9
min = cos - 1 [ 1 2 ( 2 - 2 - b ) ] . ( 20 )
[0084] Therefore, the smallest frequency which the oscillator can
generate is 10 f min = min 2 f clk , ( 21 )
[0085] where f.sub.clk is the clock frequency (sampling
frequency).
[0086] As an example, let b=25 bits. The largest oscillator
coefficient (2 cos .theta..sub.0) is 67108863/33554432, then
.theta..sub.min=cos.sup.-1 (67108863/67108864).apprxeq.0.00017263.
If clock frequency f.sub.clk is 52 MHz and b=25, then
f.sub.min.apprxeq.1.43 kHz.
[0087] The ramp duration could be altered by changing the output
frequency of the digital oscillator. During the ramp period the
phase change in equations 5 and 6 is .pi., and therefore the
required output frequency is 11 f 0 = 1 2 T r . ( 22 )
[0088] The smallest frequency f.sub.min, should be below f.sub.0.
For T.sub.r=14 .mu.s, f.sub.0.apprxeq.35.71 kHz.
[0089] Referring to FIG. 6 the cosine term in formulas 5 and 6 is
implemented by the sinusoidal oscillator, which solves the second
order difference equation. Value A.sup.* of the digital oscillator
amplitude is selected to be same as A-dc, where A is the desired
nominal power level of the ramp signal and dc is the level from
which the rising ramp starts and to which the falling ramp ends.
The initial phase offsets of the digital oscillator are 0 when
forming the ramp down, and .pi. when forming the ramp up. Hence, it
is worth noting, that by choosing the value A-dc from a table of
values the desired power level of the digital ramp signal is
selected. By setting the initial phase offset of the digital
oscillator to 0, the oscillator generates the ramp down signal, and
by setting the initial phase offset to .pi., the oscillator
generates the ramp up signal.
[0090] The digital output signal of the oscillator is (A-dc) cos
(n.theta..sub.0+.phi..sub.0). However, in order to fulfill
requirements of formulas 5 and 6, a factor A+dc should be added up
said digital output signal. That's why the output signal and a
signal having the value A+dc are applied to the two-input adder 68
(see FIG. 6). By adding, a ramp signal is produced with an
amplitude which is twice as high as required. For that reason the
ramp signal is applied to scaler 66, which performs binary shift
2.sup.-1 to the incoming digital ramp signal. The scaler can be
implemented with wiring.
[0091] Finally, the digital ramp signal is fed to block 67. The
purpose of that block is to maintain the achieved power level of
the ramp signal exactly at the desired nominal level A during the
modulation period. Block 67 can be formed by a multiplexer (MUX),
the output signal of which is locked to the input signal during the
rise and fail periods of the ramp. Hence, when the ramps start to
rise, selection signal SEL holds the MUX in a state which allows a
signal incoming from scaler 66 to appear at the output port of the
MUX. After the rising ramp has reached nominal power level A,
selection signal SEL changes the state. In response to the change,
a signal fed back from the output port to the input port of the
multiplexer is directed again to the output port, whereby signal
OUT remains constant. Accordingly, when the falling ramp starts,
selection signal SEL changes its state again, whereupon the falling
ramp is directed to the output port of MUX 67.
[0092] Power control is realized by scaling the ramp curve within
the oscillator. The amplitude of the sinusoidal is controlled by
factor A. For example, the downlink dynamic power control in GSM
900/DCS 1800 uses 16 power levels with 2 dB separation. The power
control range is 0 . . . -32 dB, where 0 dB level is the nominal
maximum power. The additional 2 dB range is reserved for gain
stabilization of the transmitter analog parts. Furthermore, power
control fine tuning step (0.25 dB) is introduced for this purpose.
Therefore, the range of the initial amplitude value A.sup.* is from
0.0251 to 0.999.
[0093] If the ramp time is variable, then a fully parallel
multiplier is needed. For applications with fixed ramp time, a
fully parallel multiplier is not required, and it would indeed be a
waste of silicon area. Multiplication by a fixed binary number can
be accomplished with N-1 adders, where N is the number of nonzero
bits in the coefficient.
[0094] If the clock frequency is 52 MHz, the output frequency of
the oscillator is 35.71 kHz and b is 25, then the coefficient 2 cos
(2.pi.f.sub.0/f.sub.clk) is 1.99998137757162
(011111111111111110110001111- ).sub.2. This requires 22 adders.
[0095] FIG. 7 shows the block diagram of a modified ramp generator
and output power controller. In comparison with FIG. 6, it includes
an extra two-input adder 78 and block 73, which multiplies variable
x1(n) with coefficient 2. In blocks 74 and 75 the multiplication
coefficients are 2(1- cos .theta.) and 1, respectively. In order to
reduce the hardware complexity of the direct-form digital
oscillator, we can write:
2 cos(.theta.)=2-2.sup.-b1.left brkt-bot.2.sup.b1(2-2 cos
(.theta.)).right brkt-bot., 12 where b1 = [ log 2 1 2 ( 1 - cos ) ]
, ( 23 )
[0096] and [r] is the smallest integer greater than or equal to r.
The coefficient (2-2 cos (2.pi.f.sub.0/f.sub.clk)) is 0.00001862
(000000000000000001001110000).sub.2. The total number of adders to
implement the coefficient 2 cos(2.pi.f.sub.0/f.sub.clk) is reduced
from 22 to 4. The coefficient is formed by multiplying the small
fraction (2-2 cos (2.pi.f.sub.0/f.sub.clk)) by the factor 2.sup.b1,
where b1 is 16. This reduces hardware complexity by reducing the
maximum word length needed in adders. The output of the adders must
be multiplied by 2.sup.-b1, to keep the overall gain unchanged. The
number of adders could be reduced further using the Canonic Signed
Digit (CSD) numbers.
[0097] The error at the invented ramp generator output consists of
two components
e(n)=e.sub.1(n)+e.sub.2(n), (24)
[0098] where e.sub.1(n) is the error due to the ramp generator
output quantization, e.sub.2(n) is the error that has been
accumulated as a result of the recursive computations in the
digital oscillator.
[0099] The bounds for e.sub.1(n) are given by
-2.sup.-c<e.sub.1.ltoreq.0, (25)
[0100] for truncation and 13 - 2 - c 2 < e 1 2 - c 2 , ( 26
)
[0101] for rounding and c is the fractional bits in the ramp
generator and power level controller.
[0102] In the digital oscillator, besides the zero-input response
y(n) of the second-order system, we get a zero-state response
y.sub.err(n) due to to the random sequence e.sub.2(n) acting as an
input signal. From equation (7) is obtained
y(n+2)=.alpha.y(n+1)-y(n)+e.sub.2(n+2), (27)
[0103] and by z transformation
Y(z)=Y.sub.ideal(z)+Y.sub.err(z), (28)
[0104] with Y.sub.ideal(z) due to (9). The z transform of the
output error Y.sub.err(n) is given by 14 Y err ( z ) = z 2 E 2 ( z
) - z 2 e 2 ( 0 ) - ze 2 ( 1 ) z 2 - 2 cos 0 z + 1 , ( 29 )
[0105] with E.sub.2(z) being the z transform of the quantization
error signal e.sub.2(n). Transforming Y.sub.err(z) back into the
time domain results in an output error sequence 15 y err ( n ) = 1
sin 0 k = 2 n e 2 ( k ) sin ( 0 ( n - k + 1 ) ) , for n 2 , ( 30
)
[0106] when e.sub.2(0) and e.sub.2(1) are assumed to be zero.
[0107] Equation (30) shows that output error is inversely
proportional to sin.theta..sub.0. Thus output error increases with
decreasing digital oscillator frequency. If truncation is used, the
right-hand side of equation (30) is negative since e.sub.2(k) is
negative, (see equation (25)) and sin (.theta..sub.0(n-k+1)) is
positive, because the digital oscillator generates only half of the
sine wave period. Therefore truncation results in very high output
errors as shown in FIG. 8A.
[0108] The fact that error is a deterministic signal forces us to
investigate the worst case, which corresponds to the case where
every truncation suffers from the maximum absolute error value.
Thus the upper limit for the error becomes 16 y max err ( M ) = e
max sin 0 k = 2 M sin ( 0 ( M - k + 1 ) ) - 2 - b sin 0 sin ( 0 / 2
) - 2 - b + 1 0 2 , , ( 31 )
[0109] where e.sub.max=-2.sup.-b is the worst case truncation
error, b is fractional bits in the digital oscillator,
0<.theta..sub.0<<1, M=[.pi./.theta..sub.0], and [r] is the
smallest integer greater than or equal to r.
[0110] FIG. 8B shows the error if rounding is used. The e.sub.2(k)
gets positive and negative values, so the output error sequence
gets lower values than in the case of truncation. Simulations
indicate the accumulated error is below output quantization error
when rounding is used, b is 25, and c is 12.
[0111] FIG. 9 and FIG. 10 show ramp up and ramp down profiles for
transmitted time slots. Dashed lines show the time mask for the
burst by burst power ramping. The curves fully satisfy the GSM
900/DCS 1800 masks. The power measured due to switching transients,
which determines allowed spurious responses originated from the
power ramping before and after the bursts, shall not exceed the
limits shown in table I. The exact limits are given in GSM
specification 05.05. The simulated power levels are well below the
limits as shown in Table I.
1 Simulated Simulated Maximum power Maximum Power Maximum limit
(dBc) (dBc) with Raised Power (dBc) Offset DCS Cosine/Sine with
Blackman (kHz) GSM 900 1800/1900 Window Window 400 -60 -53 -71.20
-71.28 600 -70 -61 -78.09 -79.69 1200 -77 -69 -84.97 -86.35 1800
-77 -69 -86.23 -89.13
Table I. Spectrum due to switching transients
[0112] The oscillator can be implemented in various ways. The fixed
co-efficient multiplier in the sinusoidal oscillator in FIG. 5
could be replaced by a fully parallel multiplier, allowing the
output frequency of the sinusoidal oscillator to be changed and the
ramp duration time to be variable.
[0113] The ramp generator and power level controller according to
the invention can also support a Blackman window.
[0114] FIG. 11 shows a ramp generator adapted to Blackman window.
In that window equations (5) and (6) presented previously are of
the form: 17 0.42 A + 0.5 A cos ( * t ) T r ) + 0.08 A cos ( 2 * t
T r ) ( 32 )
[0115] for the Blackman falling ramp, and 18 0.42 A + 0.5 A cos ( *
t ) T r + ) + 0.08 A cos ( 2 * t T r ) ( 33 )
[0116] for the Blackman rising ramp.
[0117] The frequency response of the burst signal with Blackman
window is 19 W ( f ) = V n = - .infin. .infin. M ( f - f C - nf g )
[ ( - T r ) sin c ( nf g ( - T r ) ) cos ( T r nf g ) 1 - ( 2 T r
nf g ) 2 - 4 T r sin c ( nf g T r ) cos ( nf g ( - T r ) ) 25 ( 1 -
( T r nf g ) 2 ) ] ( 34 )
[0118] where V is a proportional constant. This equation gives more
attenuation of switching transients than raised cosine/sine
switching (2).
[0119] The extra cosine term in equations (32) (33) requires one
more digital oscillator in the ramp generator and power level
controller as shown in FIG. 11.
[0120] Recursive parts (see FIGS. 7 and 11) of the ramp generator
and output power level controller determine the maximum sample
rate. The clock frequency of the IF modulator is high so the
multiplier is required to be fast. The idea of the implemented
poly-phase ramp generator structure is to generate the desired
sinusoidal oscillating signal with two oscillators, one of which
spawns the odd samples and the other the even samples. This way
both the odd and even oscillators can be operated at half the clock
frequency. This means that four oscillators are needed to generate
Blackman ramps.
[0121] FIG. 12 depicts a structure for generating Blackman ramps
with four oscillators. The odd and even oscillator outputs are
alternately selected with a 2-to-1 MUX, the select signal of which
is the divided clock. The initial values of the poly-phase ramp
generator are calculated by choosing first the same initial values
as in the normal case and calculating the next two values using the
difference equation (7) and choosing the odd samples for the odd
oscillators and the even samples for the even oscillators.
* * * * *