U.S. patent application number 09/431181 was filed with the patent office on 2002-01-31 for method of embedding contact hole by damascene method.
Invention is credited to ABE, KAZUHIDE.
Application Number | 20020013057 09/431181 |
Document ID | / |
Family ID | 12574693 |
Filed Date | 2002-01-31 |
United States Patent
Application |
20020013057 |
Kind Code |
A1 |
ABE, KAZUHIDE |
January 31, 2002 |
METHOD OF EMBEDDING CONTACT HOLE BY DAMASCENE METHOD
Abstract
A carbon film is formed over an insulating film and a contact
hole is defined therein by patterning. Copper is formed over an
entire surface including the contact hole and polished by chemical
mechanical polishing. The polishing of the copper is terminated
with the carbon film as an etching stopper thereby to allow the
copper to remain in the contact hole alone, whereby an embedded
interconnection made up of the copper is formed by a damascene
method.
Inventors: |
ABE, KAZUHIDE; (TOKYO,
JP) |
Correspondence
Address: |
JONES VOLENTINE STEINBERG AND WHITT LLP
SUITE 150
12200 SUNRISE VALLEY DRIVE
RESTON
VA
20191
|
Family ID: |
12574693 |
Appl. No.: |
09/431181 |
Filed: |
November 1, 1999 |
Current U.S.
Class: |
438/690 ;
257/E21.27; 257/E21.304; 257/E21.577; 257/E21.583; 438/691 |
Current CPC
Class: |
H01L 21/76802 20130101;
H01L 21/3212 20130101; H01L 21/7684 20130101; H01L 21/3146
20130101 |
Class at
Publication: |
438/690 ;
438/691 |
International
Class: |
H01L 021/302; H01L
021/461 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 18, 1999 |
JP |
040220/99 |
Claims
What is claimed is:
1. A method of embedding a contact hole by a damascene method,
comprising the following steps: a step for forming an insulating
film over an underbed having a plug contact hole; a step for
forming a stopper film over an entire surface including said
insulating film; a step for etching said stopper film and said
insulating film thereby to define the contact hole which reaches
said plug contact hole; a step for forming copper over an entire
surface including said contact hole thereby to embed said contact
hole; and a step for polishing the copper by chemical mechanical
polishing and terminating the polishing by said stopper film.
2. The method according to claim 1, wherein said stopper film is a
film selected from C, BC and CN.
3. A method of embedding a contact hole by a damascene method,
comprising the following steps: a step for forming an insulating
film over an underbed having a plug contact hole; a step for
successively forming a stopper film and a protective film over an
entire surface including said insulating film; a step for etching
said protective film, said stopper film and said insulating film
thereby to define the contact hole which reaches said plug contact
hole; a step for side etching said stopper film alone; a step for
forming copper over an entire surface including said contact hole
and said side-etched stopper film thereby to embed said contact
hole; and a step for polishing the copper by chemical mechanical
polishing and terminating the polishing by said stopper film.
4. The method according to claim 2 and 3, wherein said stopper film
is a film selected from C, BC, CN.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a method of forming an
interconnection used in a semiconductor device, and particularly to
a method of forming an embedded interconnection by a damascene
method using copper.
[0003] 2. Description of the Related Art
[0004] Attention has been given to Cu as the next-generation wiring
material as an alternative to an aluminum wire or interconnection.
This is because excellent electromigration resistance is obtained
while it has of course a low resistance of 1.69.times.10.sup.-6
ohmcm. Two processing methods: Chemical Mechanical Polishing
(hereinafter called "CMP") and Reactive Ion Etching are considered
to form a Cu interconnection. Since, however, it is difficult to
apply the conventional RIE method to the formation of the Cu
interconnection because Cu halide is low in vapor pressure, the
formation of a damascene interconnection using CMP is now
mainstream.
[0005] However, CMP used for Cu has a big problem in that 1) a dent
or recess defined in a wired portion by chemical etching through an
oxidizing agent in a polishing solution, 2) thinning of an
interconnection, which is developed due to the cutting of an
insulating film, which is called "dishing", and 3) etc. occur. The
recess described in the paragraph 1) can be improved by the
optimization of the ratio of mixture of a slurry and an oxidizing
agent. The thinning described in the paragraph 2) can be improved
by selecting the optimal abrasive cloth. However, the trouble
described in the paragraph 3) results from the fact that since the
polishing speed of Cu within a wafer surface is non-uniform, Cu and
an interlayer insulating film must be overpolished at their given
portions. It was therefore difficult to solve such a problem.
SUMMARY OF THE INVENTION
[0006] The present invention provides a method of depositing Cu and
a C (carbon) film having a high selection ratio over an interlayer
insulating film and thereafter defining a contact hole therein,
forming Cu over an entire surface including the contact hole,
polishing Cu by CMP, terminating the polishing of Cu by a stopper
film of the C film, and forming an embedded interconnection in the
contact hole.
[0007] An object of the present invention is to deposit Cu and a
material having a high selection ratio over an interlayer
insulating film thereby to restrain the occurrence of thinning of
Cu upon CMP and provide a damascene Cu interconnection processed
with high accuracy.
[0008] Typical ones of various inventions of the-present
application have been shown in brief. However, the various
inventions of-the present application and specific configurations
of these inventions will be understood from the following
description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] While the specification concludes with claims particularly
pointing out and distinctly claiming the subject matter which is
regarded as the invention, it is believed that the invention, the
objects and features of the invention and further objects, features
and advantages thereof will be better understood from the following
description taken in connection with the accompanying drawings in
which:
[0010] FIG. 1 is a process diagram showing a first embodiment of
the present invention, for forming an embedded interconnection by a
damascene method;
[0011] FIG. 2 is a process diagram illustrating a second embodiment
of the present invention, for forming an embedded interconnection
by the damascene method;
[0012] FIG. 3 is a process diagram showing a third embodiment of
the present invention, for forming an embedded interconnection by
the damascene method; and
[0013] FIG. 4 is a process diagram showing a fourth embodiment of
the present invention, for side-etching a stopper film when an
embedded interconnection is formed by the damascene method.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0014] Preferred embodiments of the present invention will
hereinafter be described in detail with reference to the
accompanying drawings.
[0015] A first embodiment of the present invention will first be
explained with reference to FIG. 1.
[0016] An intermediate insulating film 102 is formed over a
semiconductor substrate 101 (see FIG. 1A). An intermediate
insulating film 103 is polished a predetermined amount by CMP to
globally flatten a cell portion and its peripheral portion. A
contact hole 104 is formed by the known lithography and etching
techniques under a layout corresponding to a pattern to be formed
(see FIG. 1B).
[0017] Next, a Ti (titanium) film 105 having a film thickness of
700 .ANG. and a TiN (titanium nitride) film 106 having a film
thickness of 500 .ANG. are continuously grown and formed in a
vacuum by sputtering for enhancing directivity. For example, the Ti
film is formed on condition that power is 1 KW and film-forming
pressure is 2 mTorr while an Ar (argon) gas is being introduced,
whereas the TiN film is formed on condition that power is 5 KW and
film-forming pressure is 9 mTorr while an N2 (nitrogen) gas is
being introduced. After the TiN film 106 has been subjected to
rapid thermal nitridation (RTN) at a temperature of 650.degree. C.
for 30 seconds, a W (tungsten) film 107 is deposited over the
intermediate insulating film 102 by 6000 .ANG. by CVD. Next,
unnecessary W other than the contact hole 104 is removed by
etchback thereby to form a W plug (see FIG. 1C).
[0018] After the formation of the W plug, an interlayer insulating
film 109 having a thickness of 7000 .ANG. is deposited by CVD and a
C film 110 having a thickness of 200 .ANG. is deposited by
sputtering. The sputter C (carbon) film is formed on condition that
power is 3 KW and film-forming pressure is 5 mTorr while the Ar gas
is being introduced. A groove 111 is defined in an underbed having
the interlayer insulating film 109 and the C film 110 formed
therein by the known lithography and etching techniques according
to a layout corresponding to a pattern to be formed (see FIG. 1D).
In a resist removal process subsequent to etching, however, a
resist is removed by an organic releasant or the like without
having to use ashing. This processing is done to prevent the C film
110 from being removed together with the resist by ashing.
[0019] Next, an insulating film 112 having a thickness of 300 .ANG.
is grown by CVD. Etchback processing is effected on only side wall
portions of the groove to leave behind the insulating film 112.
Since the specific resistivity of a bulk C ranges from 4 to
7.times.10.sup.-5 ohmcm, it is necessary to isolate the
subsequently-formed interconnection from its adjacent
interconnection by side walls of the insulating film when the bulk
C is left behind. Thereafter, a Ti film 113 having a film thickness
of 100 .ANG. and a TiN film 114 having a film thickness of 400
.ANG. are continuously grown in a vacuum by sputtering.
[0020] Next, a Cu film 115 is deposited by 6000 .ANG. as a thin
film by sputtering. Power at sputtering is set to 8 KW and Ar
pressure is set to 0.8 mTorr. An underbed having the Cu thin film
115 formed therein is heat-treated in an ultrahigh vacuum
(corresponding to a vacuum of about 1.times.10.sup.-10 torr in the
present embodiment) without being taken out from a film-forming
chamber of a sputter device. Cu reflows owing to the heat
treatment, so that Cu can be embedded into the groove 111 (see FIG.
1E).
[0021] Next, the unnecessary Cu film, TiN film and Ti film other
than the groove portion are removed by CMP. A slurry to be used is
based on Al.sub.2O.sub.3 and the slurry and H.sub.2O.sub.2 are
mixed together in the proportions of 3:1. A downforce of a carrier
is defined as 3 psi and carrier and table speeds are respectively
set to 30 rpm. At this time the Cu film can be cut away or shaved
on the order of 4000 .ANG. by one-minute polishing, whereas the C
film can be cut by a few .ANG.. Thus, an abrasive selection ratio
between Cu and C results in 1000 or more. As compared with the
conventional abrasive selection ratio 100 between Cu and the
interlayer insulating film, it is understood that an improvement in
the abrasive selection ratio reaches ten times or more the
conventional abrasive selection ratio. When the unnecessary Cu
film, TiN film and Ti film have been removed, a desired Cu
interconnection 116 is obtained (see FIG. 1F). According to the
first embodiment as described above, since the C film serves as a
stopper even if overpolishing is done, a high-accuracy Cu
interconnection can be formed.
[0022] A second embodiment of the present invention will next be
described with reference to FIG. 2.
[0023] After the same process steps (their description will be
omitted) as those up to FIG. 1C have been completed, an interlayer
insulating film 201 having a thickness of 7000 .ANG. and a C film
202 having a thickness of 200 .ANG. are deposited from a lower
layer by CVD and sputtering respectively in FIG. 2A. A groove 203
is defined in an underbed having the interlayer insulating film 201
and the C film 202 formed therein by the known lithography and
etching techniques according to a layout corresponding to a pattern
to be formed (see FIG. 2B). In a resist removal process step
subsequent to etching, however, a resist is removed by an organic
releasant or the like without having to use ashing. This processing
is performed to prevent the C film 202 from being removed by ashing
together with the resist.
[0024] The process steps shown in FIGS. 1D through 1F are
subsequently effected in the same manner as described above thereby
to obtain a desired Cu interconnection 204. Next, since C of a bulk
has specific resistivities of 4 to 7.times.10.sup.-5 ohmcm, the C
film 202 is removed by downflow ashing (see FIG. 2C). A combination
of the downflow ashing and ultrasonic cleaning makes it possible to
restrain the resistance of the Cu interconnection 204 from
increasing. According to the second embodiment as described above,
since the C film serves as a stopper even if overpolishing is done,
a high-accuracy Cu interconnection can be formed. It is also
unnecessary to cover the C film whose in-groove side walls are
bare, with a insulating film, so that the process is
simplified.
[0025] A third embodiment of the present invention will next be
described with reference to FIG. 3.
[0026] After the same process steps (their description will be
omitted) as those up to FIG. 1C have been completed, an interlayer
insulating film 301, a C film 302 and a TiN film 303 are
respectively deposited by 7000 .ANG., 200 .ANG. and 150 .ANG. from
a lower layer in FIG. 3A. A groove 304 is defined in an underbed
formed with a multilayered film of the interlayer insulating film
301, the C film 302 and the TiN film 303 by the known lithography
and etching techniques according to a layout corresponding to a
pattern to be formed (see FIG. 3B).
[0027] In the structure according to the present embodiment, since
the surface of the C film is covered with the TiN film 303, it is
protected from an oxygen plasma at ashing. Therefore, the ashing
can be used in a resist removing process step subsequent to etching
as conventional. Next, the process steps shown in FIGS. 1D through
1F are similarly effected to obtain a desired Cu interconnection
305. Subsequently, ultrasonic surface cleaning is performed after
the C film 302 has been removed by downflow ashing (see FIG.
3C).
[0028] According to the third embodiment as described above, since
the C film serves as a stopper even if overpolishing is done, a
high-accuracy Cu interconnection can be formed. Further, the use of
a TiN film/C film multilayered structure allows the use of the
conventional etching process for the resist removing process step,
thereby making it possible to remove a thermally-transformed resist
and a deposited film at etching.
[0029] A fourth embodiment of the present invention will next be
explained with reference to FIG. 4.
[0030] After the same process steps as those up to FIG. 1C have
been completed, an interlayer insulating film 401, a C film 402 and
a TiN film 403 are respectively deposited by 7000 .ANG., 200 .ANG.
and 150 .ANG. from a lower layer in FIG. 4A. Thereafter, a resist
is exposed according to a formed groove pattern by a
photolithography technique. Next, the TiN film 403 is etched, the C
film 402 make dents in its side walls by isotropic etching using
the known etching gas, e.g., a CHF.sub.3/CH.sub.4/Ar gas, and the
interlayer insulating film 401 is etched, thereby defining a groove
404 (see FIG. 4B).
[0031] Next, the process steps shown in FIGS. 1D through 1F are
similarly executed to thereby obtain a desired Cu interconnection
405. Subsequently, ultrasonic surface cleaning is carried out after
the C film 402 has been removed by downflow ashing (see FIG. 4C).
According to the present embodiment as described above, since the C
film is dented or recessed in a TiN film/C film multilayered
structure, the damascene Cu interconnection and the C film do not
make contact with each other and both are isolated from each other
by an interlayer insulating film to be deposited next. It is
therefore possible to omit the C film removing process step.
Further, the C films employed in the first through fourth
embodiments may be carbon compounds such as CN, BC, etc.
[0032] According to the present invention as described above, the
deposition of a C film over an interlayer insulating film permits
implementation of a high-polishing selection ratio between Cu and
C. Since the C film serves as a stopper even if overpolishing is
done, a thinning-free damascene Cu interconnection can be
formed.
[0033] While the present invention has been described with
reference to the illustrative embodiments, this description is not
intended to be construed in a limiting sense. Various modifications
of the illustrative embodiments, as well as other embodiments of
the invention, will be apparent to those skilled in the art on
reference to this description. It is therefore contemplated that
the appended claims will cover any such modifications or
embodiments as fall within the true scope of the invention.
* * * * *