U.S. patent application number 09/898073 was filed with the patent office on 2002-01-24 for drive control circuit of charged pump circuit.
Invention is credited to Sugimura, Naoaki.
Application Number | 20020008568 09/898073 |
Document ID | / |
Family ID | 16857151 |
Filed Date | 2002-01-24 |
United States Patent
Application |
20020008568 |
Kind Code |
A1 |
Sugimura, Naoaki |
January 24, 2002 |
Drive control circuit of charged pump circuit
Abstract
There is provided a drive control circuit of a charged pump
circuit which has a power source voltage detecting circuit for
detecting a power source voltage, a control circuit for changing
the number of the drive steps of the charged pump circuit in
accordance with the detected output of the power source voltage
detecting circuit, and a by-pass circuit for allowing an output at
the last step to be by-passed towards an output side of the drive
steps in accordance with a change in the number of drive steps of
the charged pump circuit.
Inventors: |
Sugimura, Naoaki;
(Minato-ku, JP) |
Correspondence
Address: |
JONES VOLENTINE, P.L.L.C.
12200 SUNRISE VALLEY DRIVE, SUITE 150
RESTON
VA
20191
US
|
Family ID: |
16857151 |
Appl. No.: |
09/898073 |
Filed: |
July 5, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09898073 |
Jul 5, 2001 |
|
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|
09362500 |
Jul 30, 1999 |
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Current U.S.
Class: |
327/536 |
Current CPC
Class: |
H02M 3/073 20130101 |
Class at
Publication: |
327/536 |
International
Class: |
G05F 001/10 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 11, 1998 |
JP |
10-227205 |
Claims
What is claimed is:
1. A drive control circuit of a charge pump circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a power source voltage
detecting circuit for detecting said power source voltage; a
control circuit for changing the number of drive steps of said
charge pump circuit in accordance with the output detected by the
power source voltage detecting circuit; and a by-pass circuit for
allowing the final output of the drive steps to be by-passed
towards said output terminal in accordance with the change in the
number of drive steps.
2. A drive control circuit according to claim 1, wherein the number
of drive steps of said charged pump circuit is decreased in
accordance with an increase in the output detected by said power
source voltage detecting circuit.
3. A drive control circuit of the charge control circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a current detecting
circuit for detecting current flowing to said Zener diodes; a
control circuit for changing the number of drive steps of said
charge pump circuit in accordance with the output detected by the
power source voltage detecting circuit; and a by-pass circuit for
allowing the final output of the drive steps to be by-passed
towards said output terminal in accordance with the change in the
number of drive steps.
4. A drive control circuit of the charged pump circuit according to
claim 3, wherein the number of drive steps of said charged pump
circuit is decreased in accordance with an increase in the output
detected by said current detecting circuit.
5. A drive control circuit of a charge pump circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a power source voltage
detecting circuit for detecting said power source voltage; a
control circuit for changing the number of drive steps of said
charge pump circuit in accordance with the output detected by the
power source voltage detecting circuit; and a by-pass circuit for
allowing said power source voltage to be by-passed in such a manner
as to be supplied to the input side of the first step of the drive
steps in accordance with the change in the number of drive
steps.
6. A drive control circuit of the charged pump circuit according to
claim 5, wherein the number of drive steps of said charged pump
circuit is decreased in accordance with the output by said power
source voltage detecting circuit.
7. A drive control circuit of the charge control circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a current detecting
circuit for detecting current flowing to said Zener diodes; a
control circuit for changing the number of drive steps of said
charge pump circuit in accordance with the output detected by the
power source voltage detecting circuit; and a by-pass circuit for
allowing said power source voltage to be by-passed in such a manner
as to be supplied to the input side of the first step of the drive
steps in accordance with the change in the number of drive
steps.
8. A drive control circuit according to claim 7, wherein the number
of drive steps of said charged pump circuit is decreased in
accordance with an increase in the value detected by said current
detecting circuit.
9. A drive control circuit of the charge control circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a constant current
source circuit for generating a constant current having a negative
power source voltage dependency constant; an oscillation circuit
which is driven by the constant current having a negative power
source voltage dependency constant generated by the constant power
source circuit, for generating a pulse signal of a frequency having
a negative power source voltage dependency constant; and a clock
signal supply circuit for creating said two types of clock signal
on the basis of the pulse signal output from the oscillation
circuit and supplying said two types of clock signal to the charge
pump circuit.
10. A drive control circuit of the charge control circuit having: a
plurality of diodes connected in series between an input terminal
and an output terminal; a plurality of capacitors one end of each
of which is connected to each node of said plurality of diodes and
to the other end of each of which is supplied a clock signal; Zener
diodes for use in an output voltage clamp connected between said
output terminal and an earth; wherein said drive control circuit of
a charge pump circuit has a plurality of drive steps which raise
the power source voltage supplied to said input terminal to a
predetermined voltage by supplying two types of clock signals which
change levels in a compensating manner so that high level periods
do not overlap each other to each of said other terminals of
adjacent capacitors in each of said plurality of capacitors and
then output the power source voltage, and said drive control
circuit of a charge pump circuit comprises: a current detecting
circuit for detecting current flowing to said Zener diodes; a
constant current source circuit for fetching the output detected by
the current detecting circuit and generating a constant current in
reverse proportion to the value of the current flowing to said
Zener diodes; an oscillation circuit driven by the constant current
source circuit for generating a pulse frequency of a frequency in
reverse proportion to the value of the current flowing to said
Zener diodes; and a clock signal supply circuit for creating said
two types of clock signal on the basis of the pulse signal output
from the oscillation circuit and supplying the two types of clock
signal to the charge pump circuit.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a drive control circuit of
a charged pump circuit for raising a voltage inside an LSI in a
semiconductor integrated circuit, and more particularly to a drive
control circuit of a charged pump circuit for inhibiting an
increase in consumed current caused by an excess of ability of the
charged pump at the time of an increase in the voltage of an
operating power source of the LSI and, and at the same time for
compensating for a reduction in the ability of the output of the
increased voltage of the charged pump at the time of a reduction in
the operating power source.
[0003] 2. Description of the Related Art
[0004] No document has been found which describes a technique with
respect to a charged pump circuit which increases the voltage
inside an LSI in a semiconductor integrated circuit, or a technique
for preventing an increase in the consumed current caused by an
excess of ability of the charged pump at the time of an increase in
the operating power source voltage and compensating for a reduction
of output ability in the increased voltage of the charged pump at
the time of a reduction in the operation power source voltage.
[0005] FIG. 12 shows a structure of a general charged pump circuit.
In FIG. 12, NMOS diodes ND1 through NDn (n in an integer) and NDout
are connected in series between an input terminal 100 and an output
terminal 200. To each of the nodes N1 through Nn of the NMOS diodes
ND1 through NDn, one end of n capacitors C1 through Cn is connected
respectively. To the other end of the capacitor C(2(m-1)+1) (m<n
and m is an integer not less than 1) out of n capacitors C1 through
Cn, a clock .phi.1 is supplied via inverters INV1, INV3, . . .
INV(n-1).
[0006] Furthermore, a clock .phi.2 is supplied to the other end of
the capacitor C(2m) via inverters INV2, INV4, . . . , INVn.
[0007] Furthermore, a power source voltage VDD is applied to the
input terminal 100. As shown in FIG. 13B, clocks .phi.1 and .phi.2
are clock signals which change in levels in a compensating manner
at a timing at which high level periods do not overlap each other.
The amplitude thereof is the VDD. The operation of the charged pump
circuit shown in FIG. 12 will be briefly explained. When the
threshold voltage of NMOS diodes ND1 through NDn and ND out is set
to VD, the potential of node 1 is set to VDD-VD when the clock
.phi.1 is on a low level. When the clock .phi.1 is on a high level
and the clock .phi.2 is on a low level, current flows from the node
N1 to the node N2, from the node N3 to the node N4, . . . , and
from the node N(n-1) to the node Nn, and the potential of the node
N(2m) becomes higher than the potential of the node N(2m+1) by the
threshold voltage VD of the NMOS diode (for reference, m is either
0 or an integer not less than 1).
[0008] Next, when the clock .phi.1 falls to a low level, the
potentials of the nodes N1, N2, . . . , N2m, . . . , Nn tend to
fall by the amount of the VDD because of the coupling of
capacitors. However, current is supplied from the left side, and
the potentials are raised to a higher level than when the clock
.phi.1 was previously on a low level. Next, when the clock .phi.2
is raised to a high level, a current is supplied from the node
N(2m-1) to the node N(2m). When the clock .phi.2 is brought back to
the low level, a current is supplied from the node N(2m-2) to the
node N(2m-1) so that the potential of the node N(2m-1) is raised to
a higher level than the potential thereof at the time of the
previous cycle.
[0009] When the capacity of the capacitors C1 through Cn is denoted
by C, the frequency of the clocks .phi.1 and .phi.2 is denoted by
f, the output amplitude voltage of the inverters INV1 through INVn
is denoted by VDD, and the output average current value at an
output terminal 200 of the charged pump circuit is denoted by Iout,
the potential of each node is raised by the amount
(VDD-VD-Iout/(C.multidot.f)) as shown in FIG. 13A as compared with
the potential of the node by the adjacent input terminal 100. Here,
Iout/(C.multidot.f) denotes a charging and discharging voltage in
the capacitors C1 through Cn. In other words, since the output
voltage Vout at an output terminal of the charged pump circuit
shown in FIG. 12 is raised by the amount
(VDD-VD-Iout/(C.multidot.f)) for each one step of the NMOS diode,
the following mathematical formula is established.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (1)
[0010] The average consumed current IDD of this charged pump
circuit excluding a through current of the inverters (consumed
current at the time of ON and OFF inside the inverters) is the sum
total of the current values at which each of the inverters INVL
through INVn charges and discharges the capacitors C1 through Cn at
the output average current value Iout, and the following
mathematical formula is established.
IDD=n.multidot.Iout (2)
[0011] In order to set the output voltage Vout at the output
terminal 200 to a constant level, the output average current value
Iout 1 of the charged pump circuit becomes equal to the sum total
of the output average current value Iout and a Zener current Iz in
the case where Zener diodes ZD 1 and ZD 2 are connected between the
output terminal 200 and an earth as shown in FIG. 14. If the output
voltage of the charged pump circuit shown in FIG. 14 which circuit
is clamped at the Zener diodes ZD 1 and ZD 2 is denoted by Vz, the
following mathematical formula is established.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD=Vout.multidot.n.mul-
tidot.Iz/(C.multidot.f) (3)
[0012] From the mathematical formulae (1), (2) and (3), the Zener
current Iz, and the average consumed current IDD is established in
the following manner.
Iz=(Vout-Vz)/n.multidot.C.multidot.f (4)
IDD=n.multidot.(Iout+Iz) (5)
[0013] When the output average current value Iout is at a constant
level, the output voltage Vout increases as seen from the
mathematical formula (1) at the time when the power source voltage
VDD increases, and the Zener current Iz and the average consumed
current IDD increase according to the mathematical expressions (4)
and (5). FIGS. 15A and 15B show operating waveforms of a charged
pump circuit having the structure shown in FIG. 14.
[0014] In a conventional charged pump circuit, since the number of
steps of the NMOS diodes, namely the number of steps n of the
charged pump circuit and the capacity C of the capacitors (1-Cn)
which are connected to each of the nodes of the NMOS diodes, are
fixed values which are determined at the time of the circuit
design, there arises a problem that an unutilized Zener current Iz
which flows to the Zener diodes for use in the output voltage clamp
increases and the average consumed current IDD of the inverters
increases with an increase of the power source voltage VDD in the
case where the output average current value Iout of the charged
pump circuit is constant.
SUMMARY OF THE INVENTION
[0015] The present invention has been made in view of the
aforementioned circumstances, and an object of the present
invention is to provide a drive control circuit of a charged pump
circuit which circuit is capable of inhibiting an increase of the
average consumed current IDD of the inverters at the time of the
increase in the power source voltage VDD in the case where the
output average current value Iout is constant.
[0016] In order to attain the aforementioned object, according to a
first aspect of the present invention, there is provided a drive
control circuit of a charge pump circuit having:
[0017] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0018] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0019] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0020] a power source voltage detecting circuit for detecting said
power source voltage;
[0021] a control circuit for changing the number of drive steps of
said charge pump circuit in accordance with the output detected by
the power source voltage detecting circuit; and
[0022] a by-pass circuit for allowing the final output of the drive
steps to be by-passed towards said output terminal in accordance
with the change in the number of drive steps.
[0023] According to the first aspect of the present invention, the
power source voltage VDD is detected with the power source voltage
detecting circuit, the number of the drive steps of the charged
pump circuit is changed by the control circuit in accordance with
the detected output of the power source voltage VDD, and the output
of the last step of the drive steps can be allowed to be by-passed
towards the output terminal of the charged pump circuit in
accordance with the change in the number of drive steps of the
charged pump circuit by the by-pass circuit with the result that
the number of drive steps of the charged pump circuit can be
changed in accordance with increases and decreases in the VDD
voltage.
[0024] Consequently, in the case where the output average current
(load current) value Iout is constant as in the conventional
charged pump circuit, it is possible to inhibit an increase in
unutilized Zener current Iz which flows through the Zener diodes
for use in the output voltage clamp at the time of an increase in
the power source voltage VDD, and to inhibit an increase in the
average consumed current IDD as a result of an increase in this
Zener current Iz.
[0025] According to a second aspect of the present invention, there
is provided a drive control circuit of the charge control circuit
having:
[0026] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0027] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0028] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0029] a current detecting circuit for detecting current flowing to
said Zener diodes;
[0030] a control circuit for changing the number of drive steps of
said charge pump circuit in accordance with the output detected by
the power source voltage detecting circuit; and
[0031] a by-pass circuit for allowing the final output of the drive
steps to be by-passed towards said output terminal in accordance
with the change in the number of drive steps.
[0032] According to the second aspect of the present invention,
there is provided a current detecting circuit for detecting current
flowing through the Zener diodes for use in the output voltage
clamp connected between the output terminal of the charged pump
circuit and the earth, the control circuit for changing the number
of drive steps of the charged pump circuit in accordance with the
detected output of the current detecting circuit, and the by-pass
circuit for allowing the output of the last step of the drive steps
to be by-passed towards the aforementioned output terminal in
accordance with the change in the number of drive steps with the
result that the number of drive steps of the charged pump circuit
can be changed in accordance with increases and decreases in the
Zener current Iz which flows through the Zener diodes for use in
the output voltage clamp.
[0033] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit an increase in unutilized
Zener current Iz which flows through the Zener diodes for use in
the output voltage clamp at the time of an increase in the power
source VDD, and to inhibit an increase in the average consumed
current IDD as a result of an increase in this Zener current
Iz.
[0034] Furthermore, according to the second aspect of the
invention, since the unutilized Zener current Iz which flows
through the Zener diodes for use in the output voltage clamp is
detected with a current detecting circuit, and the number of drive
steps of the charged pump circuit is changed in accordance with
increases and decreases in the Zener current Iz, it is possible to
prevent unutilized Zener current from increasing along with the
change in the output average current (load current) value Iout in
the charged pump circuit, and to prevent the average consumed
current IDD from increasing as a result of an increase in this
Zener current Iz.
[0035] According to a third aspect of the present invention, there
is provided a drive control circuit of a charge pump circuit
having:
[0036] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0037] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0038] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0039] a power source voltage detecting circuit for detecting said
power source voltage;
[0040] a control circuit for changing the number of drive steps of
said charge pump circuit in accordance with the output detected by
the power source voltage detecting circuit; and
[0041] a by-pass circuit for allowing said power source voltage to
be by-passed in such a manner as to be supplied to the input side
of the first step of the drive steps in accordance with the change
in the number of drive steps.
[0042] According to the third aspect of the present invention,
since the present invention has a control circuit for changing the
number of drive steps of the charged pump circuit in accordance
with the detected output of the power source detecting circuit, and
the by-pass circuit for allowing the power source voltage to be
bypassed so that the power source voltage is supplied to the input
side of the first step of the drive steps in accordance with the
change in the number of drive steps of the charged pump circuit
with the result that the number of drive steps of the charged pump
can be changed in accordance with increases and decreases of the
power source voltage.
[0043] Consequently, in the case where the output average current
(load current) value Iout is constant as in the conventional
charged pump circuit, it is possible to inhibit unutilized Zener
current Iz which flows through the Zener diodes for use in the
output voltage clamp from increasing at the time of an increase in
the power source voltage VDD, and to prohibit the average current
IDD from increasing as a result of the increase in this Zener
current Iz.
[0044] According to a fourth aspect of the present invention, there
is provided a drive control circuit of the charge control circuit
having:
[0045] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0046] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0047] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0048] a current detecting circuit for detecting current flowing to
said Zener diodes;
[0049] a control circuit for changing the number of drive steps of
said charge pump circuit in accordance with the output detected by
the power source voltage detecting circuit; and
[0050] a by-pass circuit for allowing said power source voltage to
be by-passed in such a manner as to be supplied to the input side
of the first step of the drive steps in accordance with the change
in the number of drive steps.
[0051] According to the fourth aspect of the invention, since the
present invention has a current detecting circuit for detecting the
current flowing through the Zener diodes for use in the output
voltage clamp connected between the output terminal of the charged
pump circuit and the earth, a control circuit for changing the
number of drive steps of the charged pump circuit in accordance
with at least one of the detected output of the current detecting
circuit and the power source voltage, and a by-pass circuit for
allowing the power source voltage to be by-passed in such a manner
that the power source voltage is supplied to the input side of the
first step of the drive steps in accordance with the change in the
number of drive steps of the charged pump circuit, the number of
steps of the charged pump circuit which are actually operated can
be changed in accordance with increases and decreases of the power
source voltage VDD.
[0052] Consequently, in the case where output average current (load
current) value Iout in the conventional charged pump circuit is
constant, it is possible to inhibit unutilized Zener current which
flows through Zener diodes for use in the output voltage clamp from
increasing at the time of an increase in the power source voltage
VDD, and to inhibit the average consumed current from increasing as
a result of an increase of this Zener current Iz.
[0053] Furthermore, according to the fourth aspect of the
invention, since the unutilized Zener current Iz which flows
through Zener diodes for use in the output voltage clamp is
detected with the Zener current detecting circuit and the number of
drive steps of the charged pump is changed in accordance with
increases and decreases in the Zener current Iz, it is possible to
prevent the unutilized Zener current Iz from increasing along with
the change in the output average current (load current) value in
the charged pump circuit, and to prevent the average consumed
current IDD from increasing as a result of an increase in this
Zener current Iz.
[0054] According to a fifth aspect of the present invention, there
is provided a drive control circuit of the charge control circuit
having:
[0055] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0056] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0057] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0058] a constant current source circuit for generating a constant
current having a negative power source voltage dependency
constant;
[0059] an oscillation circuit which is driven by the constant
current having a negative power source voltage dependency constant
generated by the constant power source circuit, for generating a
pulse signal of a frequency having a negative power source voltage
dependency constant; and
[0060] a clock signal supply circuit for creating said two types of
clock signal on the basis of the pulse signal output from the
oscillation circuit and supplying said two types of clock signal to
the charge pump circuit.
[0061] According to the fifth aspect of the invention, the constant
current having a negative power source voltage dependency constant
is generated by the constant current source generating circuit, and
a pulse signal of a frequency having a negative power source
voltage dependency constant is generated, and the charged pump
circuit is driven by a clock having the frequency by the clock
signal supplying circuit with the result that the operating
frequency of the charged pump circuit can be changed in accordance
with increases and decreases in the power source voltage VDD.
[0062] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit unutilized Zener current Iz
which flows through the Zener diodes for use in the output voltage
clamp from increasing at the time of an increase in the power
source voltage VDD, and to inhibit the average consumed current IDD
from increasing as a result of an increase in this Zener current
Iz.
[0063] According a sixth aspect of the invention, there is provided
a drive control circuit of the charge control circuit having:
[0064] a plurality of diodes connected in series between an input
terminal and an output terminal;
[0065] a plurality of capacitors one end of each of which is
connected to each node of said plurality of diodes and to the other
end of each of which is supplied a clock signal;
[0066] Zener diodes for use in an output voltage clamp connected
between said output terminal and an earth; wherein said drive
control circuit of a charge pump circuit has a plurality of drive
steps which raise the power source voltage supplied to said input
terminal to a predetermined voltage by supplying two types of clock
signals which change levels in a compensating manner so that high
level periods do not overlap each other to each of said other
terminals of adjacent capacitors in each of said plurality of
capacitors and then output the power source voltage, and said drive
control circuit of a charge pump circuit comprises:
[0067] a current detecting circuit for detecting current flowing to
said Zener diodes;
[0068] a constant current source circuit for fetching the output
detected by the current detecting circuit and generating a constant
current in reverse proportion to the value of the current flowing
to said Zener diodes;
[0069] an oscillation circuit driven by the constant current source
circuit for generating a pulse frequency of a frequency in reverse
proportion to the value of the current flowing to said Zener
diodes; and
[0070] a clock signal supply circuit for creating said two types of
clock signal on the basis of the pulse signal output from the
oscillation circuit and supplying the two types of clock signal to
the charge pump circuit.
[0071] According to a sixth aspect of the invention, the current
which flows through the Zener diodes for use in the output voltage
clamp connected between the output terminal of the charged pump
circuit and the earth is detected with the current detecting
circuit; the detected output of the current detecting circuit is
fetched; the constant current which is in inverse proportion to the
value of the current flowing through the aforementioned Zener
diodes is generated by the constant current source circuit; a pulse
signal of the frequency is generated with an oscillation circuit
which is driven by the constant current source circuit, the
frequency being in inverse proportion to the value of the current
flowing through the Zener diodes; and the two kinds of clock
signals are prepared by the clock signal supply circuit on the
basis of the pulse signal which is output from the oscillation
circuit with the result that an operating frequency of the charged
pump circuit can be changed in accordance with increases and
decreases in the Zener current Iz.
[0072] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit unutilized Zener current Iz
which flows through the zener diodes for use in the output voltage
clamp from increasing at the time of an increase in the power
source voltage VDD, and to inhibit the average consumed current IDD
from increasing as a result of the increase in this Zener current
Iz.
[0073] Furthermore, according to the sixth embodiment of the
present invention, since the unutilized Zener current Iz which
flows through the Zener diodes for use in the output voltage clamp
is detected with the Zener current detecting circuit, and the
operating frequency of the charged pump circuit is changed in
accordance with increases and decreases in the Zener current Iz, it
is possible to prevent the unutilized Zener current Iz from
increasing along with the change in the output average current
(load current) in the charged pump circuit, and to prevent the
average consumed current IDD from increasing as a result of the
increase in this Zener current Iz.
BRIEF DESCRIPTION OF THE DRAWINGS
[0074] FIG. 1 is a circuit diagram showing a structure of a drive
control circuit of a charged pump circuit according to a first
embodiment of the invention.
[0075] FIG. 2 is a circuit diagram showing a specific structure of
a comparator shown in FIG. 1.
[0076] FIG. 3 is a circuit diagram showing a structure of the drive
control circuit of the charged pump circuit according to a second
embodiment of the invention.
[0077] FIG. 4 is a circuit diagram showing a specific structure of
the comparator shown in FIG. 3.
[0078] FIG. 5 is a circuit diagram showing a structure of the
charged pump circuit according to a third embodiment of the
invention.
[0079] FIG. 6 is a circuit diagram showing a structure of a level
conversion circuit shown in FIG. 5.
[0080] FIG. 7 is a circuit diagram showing a structure of the drive
control circuit of the charged pump circuit according to a fourth
embodiment of the invention.
[0081] FIG. 8 is a circuit diagram showing a structure of the drive
control circuit of the charged pump circuit according to a fifth
embodiment of the invention.
[0082] FIG. 9 is a circuit diagram showing a structure of the
charged pump circuit according to a sixth embodiment of the
invention.
[0083] FIG. 10 is a circuit diagram showing a specific structure of
the constant current source circuit shown in FIG. 9.
[0084] FIG. 11 is a circuit diagram showing a specific structure of
a drive clock generating circuit of the charged pump according to
each of the embodiments.
[0085] FIG. 12 is a circuit diagram showing one example of a
structure of the conventional charged pump circuit.
[0086] FIGS. 13A, 13B are waveform views showing an operating state
of the charged pump circuit shown in FIG. 12.
[0087] FIG. 14 is a circuit diagram showing another example of a
structure of the conventional charged pump circuit.
[0088] FIGS. 15A and 15B are waveform views showing an operating
state of the charged pump circuit shown in FIG. 14.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0089] Embodiments of the present invention will be explained in
detail hereinbelow by referring to the drawings.
[0090] First Embodiment of the Invention
[0091] The structure of a drive control circuit of a charged pump
circuit according to a first embodiment of the present invention is
shown in FIG. 1. In FIG. 1, the charged pump 10 has NMOS diodes ND1
through NDn (n is an integer), NDout, and n capacitors C1 through
Cn. NMOS diodes ND1 through NDn (n is an integer) and NDout are
connected in series between an input terminal 100 and an output
terminal 200. To each of the nodes ND1 through NDn of the NMOS
diodes ND1 through NDn, one end of each of the capacitors C1
through Cn is connected while the other end of n capacitors C1
through Cn is connected to an output terminal of NAND gates NA1
through NAn, respectively. Both input terminals of the NAND gate NA
1 out of the NAND gates NA1 through NAn are connected in common so
that a clock signal .phi..phi.1 is supplied from the charged pump
drive clock generating circuit 20 for preparing clock signals
.phi.1 and .phi.2 for driving the charged pump circuit 10.
[0092] Furthermore, to one of the input terminals of one of the
NAND gates NA3, NA5, . . . , NAn-1, the clock signal is supplied
while to one of the input terminals of the NAND gates NA2, NA4, . .
. , NAn the clock signal .phi.2 is supplied from a circuit 20 for
generating a clock for driving the charged pump. The other of the
input terminals of the NAND gates NA2, NA3, . . . , NAn-1, NAn is
connected to each of the output terminals of the comparators
CMP2-CMPn which will be described later.
[0093] Specifically, for example, the circuit 20 for generating a
clock for driving the charged pump is formed by connecting
inverters 21, 24 through 27 as shown in FIG. 11 and NOR gates 22
and 23 as shown in the drawings. A clock pulse having a constant
frequency which is generated with an oscillation circuit (not
shown) is supplied to the charged pump circuit 10 by generating two
kinds of clock signals .phi.1 and .phi.2 (refer to FIG. 13(B))
having high level periods which do not overlap each other, and the
clock pulse is supplied to the charged pump circuit 10.
[0094] The drive control circuit of the charged pump circuit
according to the first embodiment comprises a voltage dividing
circuit 15 comprising voltage dividing resistors R1, R2 and R3
connected in series between an input terminal 100 of the charged
pump circuit 10 and an earth for detecting a power source voltage
value, comparators CMP2 through CMPn for fetching a voltage across
both terminals of the voltage dividing resistor R2 (a divided
voltage value of the power source voltage VDD) and comparing the
voltage across both terminals of the resistor R2 with the input
offset voltage, NAND gates NA1 through NAn, and NMOS diodes MN1
through MNn-1 connected between each of the nodes N1 through Nn of
the NMOS diodes ND1 through NDn, and the output terminal 200 of the
charged pump circuit 10. The voltage dividing circuit 15
corresponds to a power source voltage detecting circuit of the
present invention, the comparators CMP2 through CMPn and the NAND
gates NA1 through NAn correspond to the control circuit of the
invention, and the NMOS diodes MN1 through MNn-1 correspond to the
by-pass circuit of the invention.
[0095] An example of the structure of the comparators CMP1 through
CMPn is shown in FIG. 2. In FIG. 2, the comparator CMPi (i=2
through n) comprises a differential amplifying circuit 16
comprising PMOS transistors P1 and P2, NMOS transistors N1 and N2,
an offset resistor Ra and a constant current source 22, and a
buffer comprising PMOS transistor PMOS 3 connected to an output
side of the differential amplifying circuit 16 and a constant
current source 24. A reversed input terminal of the comparator CMPi
is connected to a connection point of the voltage dividing
resistors R1 and R2, and a non-reversed input terminal is connected
to a connection point of the voltage dividing resistors R2 and
R3.
[0096] In the comparators CMP2 through CMPn, an offset resistor Ra
for setting an input offset voltage is connected between a source
of the NMOS transistor N1 having a gate connected to the reversed
input terminal and point A which constitutes an imaginary earthing
point of the differential amplifying circuit 16. A resistance value
of the offset resistor Ra is set to a different value in each of
the comparators CMP2 through CMPn as described later. In other
words, when the resistance value of each of the offset resistors Ra
of the comparators CMP2 through CMPn is set to Ra2, Ra3, . . . ,
Ran-1, Ran respectively, the resistance value of each of the offset
resistors is set to a value so that the following relation will be
established.
[0097] Ran<Ran-1< . . . <Ra3<Ra2 (6)
[0098] In the aforementioned structure, the input voltage which is
applied to a portion between the non-reversed input terminal and
the reversed input terminal of each of the comparators CMP2 through
CMPn is the voltage across both ends of the voltage dividing
resistor R2 in the voltage dividing circuit 15. When the voltage
across both ends of the voltage dividing resistor R2 is denoted by
VR2, the input voltage VR2 will be defined in accordance with the
following mathematical formula.
VR2=(R2/(R1+R2+R3)).multidot.VDD (7)
[0099] On the other hand, as has been already described above, the
comparators CMP2 through CMPn have an input offset voltage because
the offset resistor Ra is connected between a source of the NMOS
transistor N1 having a gate connected to the reversed input
terminal and an imaginary earth point A of the differential
amplifying circuit 16. Furthermore, since the resistance value of
the offset resistor Ra is set to a different value in each of the
comparators CMP2 through CMPn, the comparators CMP2 through CMPn
have different offset voltages, respectively. When the constant
current value which flows into the constant current source 22 of
the comparators CMP2 through CMPn is denoted by Ia and the input
offset voltages of the comparators CMP2 through CMPn by Vio2
through Vion, the following mathematical formula is established. 1
Vio2 = Ra2 Ia Vion = Ran Ia ) ( 8 )
[0100] In each of the comparators CMP2 through CMPn, when the input
voltage VR2 which is applied to a portion between the non-reversed
input terminal and the reversed input terminal becomes larger than
the input offset voltage possessed by each of the comparators, the
output voltage level changes from a high level to a low level.
Consequently, the condition under which the output of each of the
comparators change from the high level to the low level, the
following condition is established from the mathematical formulae
(7) and (8). 2 Output change condition of the comparator CMP2 ( R2
/ ( R1 + R2 + R3 ) ) VDD > Ra2 Ia Output change condition of the
comparator CMPn ( R2 / ( R1 + R2 + R3 ) ) VDD > Ran Ia ) ( 9
)
[0101] Since the values of the offset resistors Ra2 through Ran of
the comparators CMP2 through CMPn are dictated by the relation of
Ran<Ra(n-1)< . . . <Ra2 as shown in the mathematical
formula (6), the comparators CMP2 through CMPn are operated in such
a manner that the output of the comparators CMP2 through CMPn
changes from a high level to a low level in an order of
[0102] CMPn.fwdarw.CMP(n-1).fwdarw. . . . .fwdarw.CMP2
[0103] with an increase in the power source voltage VDD from the
mathematical expression (9).
[0104] When the power source voltage VDD is set as a value within
the range of a normal voltage level, in other words, when the
voltage VR2 across both terminals of the voltage dividing resistors
R2 falls within the relation of VR2<Ran.multidot.Ia, the NMOS
transistor N2 and the PMOS transistor P3 shown in FIG. 2 are turned
on in all of the comparators CMP2 through CMPn so that the output
of each of the comparators is set to a high level.
[0105] When the output of all the comparators CMP2 through CMPn is
set to a high level, the charged pump circuit 10 shown in FIG. 1 is
operated from the first step up to the nth step, and is operated in
the same manner as the conventional charged pump circuit shown in
FIG. 14 with the result that the output voltage of the charged pump
circuit 10, a Zener current which flows through the Zener diodes
ZD1 and ZD2, and the average consumed current IDD will be defined
in the following manner.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (10)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (11)
IDD=n.multidot.(Iout+Iz) (12)
[0106] Here, Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (13)
[0107] When the output of the comparator CMPn changes from the high
level to the low level along with the increase in the power source
voltage VDD, the nth step of the charged pump circuit 10 serves as
one of the inputs of the NAND gate NAn for driving the nth step of
the output of the comparator CMPn, the output of the NAND gate NAn
continues to be set to a high level irrespective of the clock
signal .phi.2 with the result that the operation of the nth step of
the charged pump circuit 10 is suspended. At this time, the first
step to the (n-1)th step of the charged pump circuit are operated,
the potential at the node Nn-1 becomes higher than the potential at
the output terminal 200, and the NMOS diode MNn-1 is by-passed in
order to provide a conducting state with the result that the output
voltage at the (n-1)th step of the charged pump circuit 10 is
output to the output terminal 200 of the charged pump circuit 10
via the NMOS diode MN(n-1).
[0108] The threshold voltage of the NMOS diode (MN1 through MNn-1)
is set to VD which is the same as the threshold voltage of the NMOS
diode ND1 through NDn and NDout, the output voltage Vz of the
charged pump circuit 10 in the case of the suspension of the
operation of the nth step, the Zener current Iz which flows through
the Zener diodes ZD1 and ZD2 and the average consumed current IDD
will be defined in the following manner in the charged pump circuit
10.
Vz=VDD+(n-1).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (14)
Iz=(Vout-Vz)/(n-1)C.multidot.f (15)
IDD=(n-1).multidot.(Iout+Iz) (16)
[0109] Here, Vout will be defined in the following manner.
Vout=VDD+(n-1).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (17)
[0110] Furthermore, when the output of the comparator CMP (n-1)
changes from a high level to a low level along with the increase in
the power source voltage VDD, the operation of the (n-1) th step of
the charged pump circuit 10 is suspended after the nth step thereof
with the result that the output voltage Vz of the charged pump
circuit 10, the Zener current Iz which flows through the Zener
diodes ZD1 and ZD2 and the average consumed current IDD will be
defined in the following manner.
Vz=VDD+(n-2).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (18)
Iz=(Vout-Vz)/(n-2).multidot.C.multidot.f (19)
IDD=(n-2).multidot.(Iout+Iz) (20)
[0111] Here, Vout will be defined in the following manner.
Vout=VDD+(n-2).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (21)
[0112] In this manner, the output of the comparator CMP2 through
CMPn changes from a high level to a low level in an order of
[0113] CMP(n).fwdarw.CMP(n-1).fwdarw. . . . .fwdarw.CMP2
[0114] with an increase in the power source voltage VDD, and the
operation of the charged pump circuit 10 is suspended in an order
of
[0115] nth step.fwdarw.(n-1)th step.fwdarw. . . . .fwdarw.second
step.
[0116] As a consequence, the nth item representing the number of
steps of the charged pump can be changed as n.fwdarw.(n-1).fwdarw.
. . . .fwdarw.2 with an increase in the power source voltage VDD so
that the number of steps of the charged pump circuit which are
actually operated can be decreased with an increase in the power
source voltage VDD.
[0117] The relation between a value of the power source voltage VDD
and the number of steps of the charged pump circuit which are
actually operated can be freely set by selecting a resistance ratio
of the voltage dividing resistors R1, R2, and R3 of the voltage
dividing circuit, a value of an offset resistance Ra of each of the
comparators, and a constant current value Ia of the constant
current source 15.
[0118] In the drive control circuit of the charged pump circuit
according to the first embodiment of the present invention, the
power source voltage VDD is detected with the voltage dividing
circuit which serves as a detecting circuit of the power source
voltage, the number of drive steps of the charged pump circuit is
changed with the comparators CMP2 through CMPn and the NAND gates
NA1 through NAn which serve as control circuits in accordance with
the detected value of the power source voltage VDD, and the output
of the last step out of the drive steps of the charged pump circuit
is by-passed to the side of the output terminal of the charged pump
circuit in accordance with the change in the number of drive steps
of the charged pump circuit with the NMOS diodes MN1 through
MN(n-1) which serve as the by-pass circuit with the result that the
number of drive steps of the charged pump circuit can be changed in
accordance with increases and decreases in the VDD voltage.
[0119] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit an increase in the
unutilized Zener current Iz which flows through the Zener diodes
for use in the output voltage clamp at the time of an increase in
the power source voltage VDD, and an increase in the average
consumed current IDD as a result of an increase in this Zener
current Iz.
[0120] Furthermore, in the first embodiment of the invention, the
number of steps of the charged pump circuit which are actually
operated can be changed by steps in accordance with an increase and
a decrease of the power source voltage VDD with the result that the
power source voltage during the operation of the circuit is
constant and is effective in the case where the scope of the
operation insurance power source voltage of the charged pump
circuit is large.
[0121] Second Embodiment of Invention
[0122] The structure of the charged pump circuit according to a
second embodiment of the present invention is shown in FIG. 3. The
drive control circuit of the charged pump circuit according to the
second embodiment of the present invention is different in
structure from the drive control circuit of the charged pump
circuit according to the first embodiment of the present invention
in that the Zener current detecting circuit 30 for detecting the
Zener current flowing through Zener diodes for use in the output
voltage clamp is provided so that the number of drive steps of the
charged pump circuit 10 is changed with the comparators CMP2
through CMPn and the NAND gates NA1 through NAn in accordance with
the detected output of this Zener current detecting circuit 30.
Because the rest of the structure is the same for both an
explanation thereof is omitted. Note that the structure of the
comparators CMP2 through CMPn is different from the first
embodiment as will be described later, and the resistance value of
the offset resistor for setting the input offset voltage is
structured so that the resistance value thereof can be changed
over.
[0123] The Zener current detecting circuit 30 has a current
detecting resistor R4 connected between an anode of the Zener diode
ZD1 connected in series between the output terminal 200 of the
charged pump circuit 10 and an earth, and a cathode of the Zener
diode ZD2, NMOS transistors N3, N4 and N5, and constant current
sources 32 and 34. With the NMOS transistor N3, a gate is connected
to a connection point between the Zener diode ZD1 and the current
detecting resistor R4, a drain is connected to the cathode of the
Zener diode ZD1, and a source is connected to the drain of the NMOS
transistor N6, respectively. The NMOS transistor N6 is connected to
the diodes, and the drain thereof is connected to the source of the
NMOS transistor N3. The source thereof is earthed via the constant
current source 32.
[0124] The drain of the NMOS transistor N4 is connected to the
drain of the NMOS transistor N3. The gate is connected to a
connection point of the current detecting resistor R4 and the Zener
diode ZD2, and the source thereof is connected to the drain of the
NMOS transistor N5 by means of diodes, respectively. The source of
the NMOS transistor N5 is grounded via the constant current source
34. Devices are selected in such a manner that the characteristics
of the NMOS transistors N3 and N4 are the same, and, at the same
time, the characteristics of the NMOS transistors N5 and N6 are the
same. The constant number of each of the devices in the Zener
current detecting circuit 30 is selected so that the constant
current Ic flows into the constant current sources 32 and 34.
[0125] The reversed input terminals of the comparators CMP2 through
CMPn are connected in common and are connected to a connection
point of the source of the NMOS transistor N6 and the constant
current source 32. The non-reversed input terminals of the
comparators CMP2 through CMPn are connected in common, and are
connected to a connection point of the source of the NMOS
transistor N5 and the constant current source 34. Each of the
output terminals of the comparators CMP2 through CMPn is connected
to one of the NAND gates NA2 through NA(n-1) for supplying a clock
signal to each of the drive steps of the charged pump circuit
10.
[0126] Furthermore, the F input terminal of each of the comparators
CMP2 through CMP(n-1) is connected to the output terminal of the
comparators CMP3 through CMPn at the adjacent rear step thereof.
The B input terminal of each of the comparators CMP3 through CMPn
is connected to the output terminal of the comparators CMP2 through
CMP(n-1) at the adjacent front step thereof. The F input terminal
of the comparator CMPn is grounded, and the B input terminal of the
comparator CMP2 is connected to the power source line for supplying
the power source voltage VDD.
[0127] A concrete structure of the comparators CMP2 through CMPn is
shown in FIG. 4. In FIG. 4, the comparator CMPi (i=2 through n)
comprises a differential amplifying circuit 22 comprising PMOS
transistors P4 and P5, NMOS transistors N7 and N8, offset resistors
Ra, Rn and Rc, PMOS transistors P7 through P10 which serve as a
switch, and constant current source 50, a buffer 24 comprising a
PMOS transistor P6 connected to the output side of the differential
amplifying circuit 22 and a constant current source 52; and a
decoder 40 comprising NAND gates 42, 44, 46 and 48 for changing
over the input offset voltage of the differential amplifying
circuit 22.
[0128] In the comparator CMPi (i=2 through n), the offset resistors
Ra, Rb and Rc for setting an input offset voltage are connected in
series between the source of the NMOS transistor N7 having a gate
connected to the reversed input terminal of the comparator CMPi,
and the source of the NMOS transistor N8 having a gate connected to
the non-reversed input terminal thereof, each of the connection
points A, B, C, and D is connected to the sources of the PMOS
transistors P7, P8, P9 and P10 respectively, and the drains of the
PMOS transistors P7 through P10 are commonly connected and grounded
via the constant current source 50. The gates of the PMOS
transistors P7 through P10 are connected to each of the output
terminals of the NAND gates 42, 43, 44, 46 and 48 of the decoder
40.
[0129] The output of the comparator itself and the control data
which is input from the F input terminal and the B input terminal
are input to the decoder 40.
[0130] The sources of the PMOS transistors P4, P5 and P6 are
connected to the power source line for supplying a power source
voltage VDD. The structure of the comparator CMPi is basically the
same as the comparator shown in FIG. 2 except for the fact that the
offset resistors Ra, Rb and Rc are constituted in such a manner
that the resistors Ra, Rb and Rc can be switched over with the
output from the decoder 40.
[0131] In the aforementioned structure, as has been already
described above, the characteristics of the NMOS transistors N3 and
N4 of the Zener current detecting circuit 30 are the same, and the
characteristics of the NMOS transistors N5 and N6 are the same so
that a drain current Id of the NMOS transistors N3 and N6 is a
value of the constant current Ic of the constant current source 32,
and a drain current Id of the NMOS transistors N4 and N5 is a value
of the constant current Ic of the constant current source 34. Since
the value of the constant current Ic of the constant current source
32 and the value of the constant current Ic of the constant current
source 34 are the same, the voltage Vgs between the gate and the
source of the NMOS transistors N3 and N4 becomes the same and the
voltage Vgs between the gate and the source of the NMOS transistors
N5 and N6 becomes the same. Consequently, the voltage value between
the source of the NMOS transistor N5 and the source of the NMOS
transistor N6 becomes equal to the voltage between the terminals of
the current detecting resistors R4. In other words, the input
voltage which is applied to a portion between the reversed input
terminal and the non-reversed input terminal of the comparators
CMP2 through CMPn is a voltage between terminals of the current
detecting resistor R4. When the voltage is set to VR4, the current
which flows through the current detecting resistor R4 is (Iz-21c)
(Iz is Zener current) with the result that the voltage VR4 between
terminals of the current detecting resistor R4 is defined in the
following manner with the resistance value of the current detecting
resistor R4 being set to R4.
VR4=R4.multidot.(Iz-2.multidot.Ic) (22)
[0132] Furthermore, the comparators shown in FIG. 4 are constituted
in such a manner that the offset resistors Ra, Rb and Rc are
connected in series between the source of the NMOS transistor N7
and the source of the NMOS transistor N8, the imaginary earth
points are changed from point A to point D by turning on and off
the PMOS transistors 42, 44, 46 and 48 so that the setting of the
input offset voltage can be changed. In the case where the constant
current value of the constant current source constituting a
differential amplifying circuit of the comparator is set to Ia and
the resistance values of the offset resistors Ra, Rb and Rc are set
to a state represented by the mathematical expression of
Ra>Rb+Rc, the offset voltages Vioa through Viod will be defined
in the following mathematical expression when each of the points A,
B, C and D is defined as imaginary points by referencing to the
reversed input terminal depending on the ON and OFF state of the
POS transistors P7, P8, P9 and P10. 3 At P7 = ON , P8 - P10 = OFF :
Vioa = - ( Ra + Rb + Rc ) Ia At P8 = ON , P7 , P9 , P10 = OFF :
Viob = ( Ra - Rb - Rc ) Ia At P9 = ON , P7 , P8 , P10 = OFF : Vioc
= ( Ra + Rb - Rc ) Ia At P10 = ON , MP7 - MP9 = OFF : Viod = ( Ra +
Rb + Rc ) Ia ) ( 23 )
[0133] The ON and OFF states of the PMOS transistors P7 through P10
are determined by the output of the comparator (described as F
input for the sake of convenience), the control data (simply
described as F input) which is input from the F input terminal, and
the output of the decoder 40 with the control data which is input
to the B input terminal serving as an input. The mathematical
expressions (23) will be defined in the following manner when the
mathematical expression (23) is summarized for each state of the
CMP output, the F input and the B input in accordance with the
decoder logic of the decoder 40. 4 At F input = H , CMP output = H
, B input = H : Viod = ( Ra + Rb + Rc ) Ia At F input = L , CMP
output = H , B input = H : Vioc = ( Ra + Rb - Rc ) Ia At F input =
L , CMP output = L , B input = H : Viob = ( Ra - Rb - Rc ) Ia At F
input = L , CMP output = L , B input = L : Vioa = ( Ra + Rb + Rc )
Ia ) ( 24 )
[0134] In the state in which the output voltage Vz of the charged
pump circuit 10 is lower than the sum of the Zener voltages Vz1 and
Vz2 of the Zener diodes ZD1 and ZD2 at the time of the start of the
operation of the charged pump circuit, and the Zener current Iz
hardly flows, namely, in the state in which the voltage VR4 between
terminals of the current detecting resistor R4 is set to a relation
of VR4.apprxeq.OV, the output voltage of all the comparators CMP2
through CMPn is set to a high level, and each of the offset
voltages Vio2 through Vion of the comparators CMP2 through CMPn at
that time can be set in accordance with the following mathematical
expression. 5 Vio2 = ( Ra + Rb + Rc ) Ia Vio ( n - 1 ) = ( Ra + Rb
+ Rc ) Ia Vion = ( Ra + Rb - c ) Ia ) ( 25 )
[0135] At this time, the input offset voltage Vion of the
comparator CMPn is set to a value smaller than the input offset
voltage Vio2 through Vio(n-1) of the other comparators CMP2 through
CMP(n-1). The output of each of the comparators changes from a high
level to a low level when the input voltage VR4 applied to a
portion between the non-reversed input terminal and the reversed
input terminal becomes larger than the input offset voltage Vio
which is set in each of the comparators.
[0136] Since the input offset voltage Vion of the comparator CMPn
has become smaller than the input offset voltage Vio2 through
Vio(n-1) of the other comparators CMP2 through CMP(n-1) is the
state described by the mathematical expression (25), the Zener
current Iz increases with an increase in the power source voltage
VDD and a decrease in the output average current Iout. In the case
where the input voltage VR4 of each of the comparators increases,
the output of the comparator CMPn changes from a high level to a
low level in the very beginning.
[0137] All the outputs of the comparators CMP2 through CMPn are set
to a high level until the output of the comparator CMPn changes
from a high level to a low level, and the charged pump circuit 10
is operated all from the first step to the nth step, and can be
operated in the same manner as the conventional charged pump
circuit shown in FIG. 14 with the result that the output voltage Vz
of the charged pump circuit 10, the Zener current Iz which flows
through the Zener diodes ZD1 and ZD2, and the average consumed
current IDD will be defined in the following manner.
Vz=VDD+n.multidot.(VDD-VD(Iout+Iz)/(C.multidot.f))-VD (26)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (27)
IDD=n.multidot.(Iout+Iz) (28)
[0138] Here, the Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (29)
[0139] When the voltage between both terminals of the current
detecting resistor R4 increases and the state represented by the
mathematical expressions of VR4>Vion (VR4=R4.multidot.(Iz-2Ic),
and Vion=(Ra+Rb+Rc).multidot.Ia), the output of the comparator CMPn
changes from a high level to a low level.
[0140] At the nth step of the charged pump circuit 10, the clock
signal .phi.2 is supplied from a circuit 20 for generating a clock
for driving the charged pump. Since the output (on a low level) of
the comparator CMP(n) serves as the other input of the NAND gate
NAn, the operation of the nth step is suspended. At this time,
since the first step to the (n-1)th step of the charged pump
circuit 10 is operated, the output voltage at the (n-1)th step is
output to the output terminal 200 of the charged pump circuit 10
via the NMOS diode MN(n-1). When the threshold voltage of the NMOS
diodes NMOS diodes MN1 through MN(n-1) is set to VD which is the
same as the threshold voltage of the NMOS diodes ND1 through NDn
and the NDout, the output voltage Vz of the charged pump circuit
10, the Zener current Iz which flows through the Zener diodes ZD1
and ZD2 and the average consumed current IDD will be defined in the
following manner when the operation of the nth step is suspended in
the charged pump circuit 10.
Vz=VDD+(n-1).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (30)
Iz=(Vout-Vz)/(n-1).multidot.C.multidot.f (31)
IDD=(n-1).multidot.(Iout+Iz) (32)
[0141] Here, Vout will be defined in the following manner.
Vout=VDD+(n-1).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (33)
[0142] In this case, since the output of the comparator CMPn
changes from a high level to a low level, the input offset voltage
Vion of the comparator CMPn changes.
[0143] Furthermore, since the F input of the comparator CMP(n-1)
has changed from a high level to a low level, the input offset
voltage Vio(n-1) of the comparator CMP(n-1) also changes.
Consequently, the input offset voltages Vio2 through Vion of the
comparators CMP2 through CMPn change in the following manner in
accordance with the mathematical expressions (23) and (24). 6 Vio2
= ( Ra + Rb + Rc ) Ia Vio ( n - 2 ) = ( Ra + Rb + Rc ) Ia Vio ( n -
1 ) = ( Ra + Rb - Rc ) Ia Vion = ( Ra - Rb - Rc ) Ia ) ( 34 )
[0144] The input offset voltage Vio(n-1) of the comparator CMP(n-1)
is smaller than the input offset voltages Vio2 through Vio(n-2) of
the other comparators CMP2 through CMP(n-2) excluding the
comparator CMPn, and furthermore, the input offset voltage Vion of
the comparator CMPn is smaller than the input offset voltage
Vio(n-2) of the comparator CMP (n-1). This state continues in the
case where the relation between the input voltage VR4 of each of
the comparators CMP2 through CMPn, the input offset voltage Vion of
the comparator CMPn, and the input offset voltage Vio(n-1) of the
comparator CMP(n-1) is defined by the mathematical expression of
Vion(=(Ra+Rb+Rc).multidot.Ia)<VR4(=R4.multidot.(Iz-2Ic))-
<Vio(n-1)(=(Ra+Rb+Rc).multidot.Ia).
[0145] Supposing that the state represented by the mathematical
expression of VR4(=R4
(Iz-2Ic))<Vio(n-1)(=(Ra-Rb-Rc).multidot.Ia) is established, the
output of the comparator CMPn changes from a low level to a high
level with the result that the relation between the output voltage
of the charged pump circuit 10 and the output current thereof is
brought back to the state represented by the mathematical
expressions (26) through (29) and the input offset voltage Vio2
through Vion of the comparators CMP2 through CMPn is brought back
to the state represented by the mathematical expression (25).
[0146] Contrary to this, when the voltage VR4 across both terminals
of the current detecting resistor R4 increases and the state
represented by the mathematical expression of
Vio(n-1)(=(Ra+Rb+Rc).multidot.Ia)<VR4(=R4 (Iz-2Ic)) is
generated, the output of the comparator CMP(n-1) changes from a
high level to a low level. In the (n'1)th step of the charged pump
circuit 10, the clock signal .phi.1 is supplied via one of the
input terminals of the NAND gate NA(n-1) from the circuit 20 for
generating a clock for driving the charged pump. However, since the
output (on a low level) of the comparator CMP(n-1) serves as
another input of the NAND gate NA(n-1), the operation of the
(n-1)th step itself is suspended. At this time, since the first
step to (n-2) step of the charged pump circuit 10 itself is
operated, the output voltage at the (n-2)th step is output to the
output terminal 200 of the charged pump circuit 10 via the NMOS
diode MN(n-2).
[0147] In the charged pump circuit 10, the output voltage Vz of the
charged pump circuit 10, the Zener current Iz which flows through
the Zener diodes ZD1 and ZD2 and the average consumed current IDD
will be defined in the following manner in the case where the
operation of the (n-1)th step is suspended.
Vz=VDD+(n-2).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (35)
Iz=(Vout-Vz)/(n-2).multidot.C.multidot.f (36)
IDD=(n-2).multidot.(Iout+Iz) (37)
[0148] Here, Vout will be defined in the following manner.
Vout=VDD+(n-2).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (38)
[0149] In this case, since the output of the comparator CMP(n-1)
has changed from a high level to a low level, the input offset
voltage Vio(n-1) of the comparator CMP(n-1) changes. Furthermore,
since the F input of the comparator CMP(n-2) has changed from a
high level to a low level, the input offset voltage Vio(n-2) of the
comparator CMP(n-2) also changes.
[0150] Furthermore, the B input of the comparator CMPn has changed
from a high level to a low level, the input offset voltage Vion of
the comparator CMPn further changes.
[0151] Consequently, the input offset voltage Vio2 through Vion of
the comparators CMP2 through CMPn changes in the following manner
in accordance with the aforementioned mathematical expressions (23)
and (24). 7 Vio2 = ( Ra + Rb + Rc ) Ia Vio ( n - 3 ) = ( Ra + Rb +
Rc ) Ia Vio ( n - 2 ) = ( Ra + Rb - Rc ) Ia Vio ( n - 1 ) = ( Ra -
Rb - Rc ) Ia Vion = - ( Ra + Rb + c ) Ia ) ( 39 )
[0152] The input offset voltage Vio(n-2) of the comparator CMP(n-2)
becomes smaller than the input offset voltage Vio2 through Vio(n-3)
of the other comparators CMP2 through CMP(n-3) excluding the
comparator CMP(n-1), and, furthermore, the input offset voltage
Vio(n-1) of the comparator CMP(n-1) becomes smaller than the input
offset voltage Vio(n-2) of the comparator CMP(n-2). The input
offset voltage Vion of the comparator CMPn becomes a negative input
offset voltage when the reversed input terminal serves as a
reference. This state continues in the case where the relation
between the input voltage VR4 of each of the comparators, the input
offset voltage Vio(n-1) of the comparator CMP(n-1) and the input
offset voltage Vio(n-2) of the comparator CMP(n-2) is set to a
state represented by the mathematial expression of
Vio(n-1)(=(Ra-b-Rc).multidot.Ia)<VR4(=R4.multidot.(Iz-21c))<Vio(n-2-
)(=(Ra+Rb-Rc).multidot.Ia)
[0153] Supposing that a state represented by the mathematical
expression of
VR4(=R4.multidot.(Iz-21c))<Vio(n-1)(=(Ra-Rb-Rc).multidot.Ia) is
generated, the output of the comparator CMP(n-1) changes from a low
level to a high level so that the relation between the output
voltage of the charged pump circuit and the output current thereof
is brought back to a state represented by the mathematical
expressions (30) through (33) and the input offset voltage Vio2
through Vion of the comparators CMP2 through CMPn is brought back
to a state represented by the mathematical expression (34).
[0154] Contrary to this, when the voltage VR4 across both terminals
of the current detecting resistor R4 increases and the state
represented by the mathematical expression of
Vio(n-2)(=(Ra+Rb-Rc)<VR4(=R4.multidot.(Iz-2- 1C), the comparator
CMP(n-2) changes from a high level to a low level. As a
consequence, the operation of the (n-2)th step of the charged pump
circuit 10 is suspended.
[0155] As has been explained above, the output of each of the
comparators CMP2 through CMPn changes from a high level to a low
level in accordance with an increase in the Zener current Iz which
flows into the Zener current detecting circuit 30 in an order of
CMPn.fwdarw.CMP (n-1).fwdarw. . . . .fwdarw.CMP2 with the result
that the operation of the charged pump circuit 10 is suspended in
an order of the nth step.fwdarw.the (n-1)th step.fwdarw. . . .
.fwdarw.the second step.
[0156] Consequently, the nth item representing the number of steps
of the charged pump in the relation expression (26) between the
output voltage of the charged pump circuit 10 and the output
current thereof can be changed in an order of
n.fwdarw.(n-1).fwdarw. . . . 2 in accordance with an increase in
the zener current Iz, and the number of steps of the charged pump
which are actually operated can be changed so that the number is
decreased in accordance with an increase in the Zener current Iz.
The relation between the current value of the Zener current Iz and
the number of steps of the charged pump which are actually operated
can be freely set with a resistance ratio of the current detecting
resistor R4 of the Zener current detecting circuit 30 as against
the offset resistors Ra, Rb and Rc of the each of the comparators
(CMP2 through CMPn) and the constant current value Ia of the
constant current source 50 of each of the comparators.
[0157] Since the drive control circuit of the charged pump circuit
according to the second embodiment of the invention has a Zener
current detecting circuit 3 which serves as a current detecting
circuit for detecting a current which flows through the Zener
diodes for use in the output voltage clamp connected between an
output terminal of the charged pump circuit and an earth,
comparators CMP2 through CMPn and NAND gates NA1 through NAn which
serve as a control circuit for changing the number of the drive
steps of the charged pump circuit in accordance with the detected
output of the Zener current detecting circuit 30, and NMOS diodes
MN1 through MN(n-1) which serve as a bypass circuit for allowing
the output of the last step out of the drive steps to be bypassed
to the side of the aforementioned output terminal in accordance
with a change in the number of drive steps with the result that the
number of the drive steps of the charged pump circuit can be
changed in accordance with an increase and a decrease in the Zener
current Iz which flows through the Zener diodes for use in the
output voltage clamp.
[0158] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit an increase in an unutilized
Zener current Iz which flows through Zener diodes for use in the
output voltage clamp at the time of an increase in the power source
voltage VDD, and an increase in the average consumed current IDD as
a result of an increase in this Zener current Iz.
[0159] Furthermore, according to the second embodiment of the
invention, since the unutilized current Iz which flows through
Zener diodes for use in the output voltage clamp is detected with
the Zener current detecting circuit, and the number of drive steps
of the charged pump circuit is changed in accordance with an
increase and a decrease in the charged pump circuit, it is possible
to prevent an increase in the unutilized Zener current Iz increases
along with a change in the output average current (load current)
value Iout in the charged pump circuit, and an increase in the
average consumed current IDD as a result of an increase in this
Zener current Iz.
[0160] Furthermore, according to the second embodiment of the
invention, the number of drive steps of the charged pump circuit
can be changed in steps in accordance with a change in a value of
the current which flows through Zener diodes for use in the output
voltage clamp with the result that the output load current of the
charged pump circuit is changed in accordance with the operation
power source voltage and is effective is the case where the scope
of the operation insurance power source voltage is large.
[0161] Third Embodiment of the Invention
[0162] A structure of the drive control circuit of the charged pump
circuit according to a third embodiment of the invention is shown
in FIG. 5. The drive control circuit of the charged pump circuit
according to the third embodiment of the invention comprises a
voltage dividing circuit 15 comprising voltage dividing resistors
R1, R2 and R3 connected in series between the input terminal 100 of
the charged pump circuit 10 and the earth for detecting a power
source voltage value, comparators CMP1 through CMP(n-1) for
fetching a voltage (a divided voltage value of the power source
voltage VDD) across both terminals of the voltage dividing resistor
R2 and comparing the voltage across both terminals of the voltage
dividing resistor R2 with and the input offset voltage, NAND gates
NA1 through NAn, PMOS transistors MP1 through MP(n-1) connected
between each of the nodes N1 through N(n-1) of the NMOS diodes ND1
through NDn and the input terminal 100 of the charged pump circuit
100, and a level converter 60-1 through 60-(n-1) for converting in
level a high level output of the comparators CMP1 through CMP(n-1)
into a level of the output voltage Vz of the charged pump
circuit.
[0163] In each of the PMOS transistors MP1 through MP(n-1), the
drain is connected to the side of each of the nodes N1 through
N(n-1) of the NMOS diodes ND1 through NDn, the source is connected
to the input terminal 100 to which the power source voltage VDD is
supplied, and the gate is connected to the output terminal of each
of the level converters 60-1 through 60-(n-1) Furthermore, in each
of the PMOS transistors MP1 through MP(n-1), the source and the
substrate are short-circuited.
[0164] The voltage dividing circuit 15 corresponds to a power
source voltage detecting circuit of the inventrion, the comparators
CMP1 through CMP(n-1) and the NAND gates NA1 through NAn correspond
to the control circuit of the invention, the PMOS diodes MP1
through MP(n-1) and the level converters 60-1 through 60-(n-1)
correspond to a by-pass circuit of the invention, respectively.
[0165] A structure of the charged pump circuit 10, and the circuit
20 for generating a clock for driving the charged pump is the same
as the first embodiment of the invention shown in FIG. 1. The third
embodiment is the same as the first embodiment in that the Zener
diodes ZD1 and ZD2 for use in the output voltage clamp are
connected between the output terminal 200 of the charged pump
circuit 10 and the earth. Furthermore, a concrete structure of the
comparators CMP1 through CMP(n-1) is shown in FIG. 2 in the same
manner as the first embodiment of the invention, and overlapped
explanation thereof will be omitted.
[0166] A concrete structure of the level converters 60-1 through
60-(n-1) will be shown in FIG. 6. In FIG. 6, the sources of the
PMOS transistors P12 and P13 are commonly connected, and the output
voltage Vz of the charged pump circuit 10 is supplied to the source
thereof. The drains of the PMOS transistors P12 and P13 are
connected respectively to the drains of the NMOS transistors N10
and Nil. The sources of the NMOS transistors N10 and N11 are
grounded, the gate of the NMOS transistor N10 is connected to the
input terminal 110 to which the output of the comparator is input,
and the gate of the NMOS transistor N10 is connected to the output
terminal of the inverter 62 via the input terminal 100 and the
inverter 62. To the inverter 62, the power source voltage VDD is
supplied.
[0167] Furthermore, the gate of the PMOS transistor P12 is
connected to the drain of the NMOS transistor N11, the gate of the
PMOS transistor P13 is connected to the drain of the NMOS
transistor N10, respectively. The drain of the NMOS transistor N11
is connected to the output terminal 120. The output terminal 120 of
each of the level converters 60-1 through 60-(n-1) is connected to
each of the gates of the PMOS transistors MP1 through MP(n-1).
[0168] In the aforementioned structure, when the resistance values
Ra1 through Ra(n-1) of the offset resistor Ra of the comparators
CMPi through CMP (n-1) are set to a value represented by the
mathematical expression of Ra(n-1)>Ra(n-2) . . . >Ra1, the
output of the comparators CMP1 through CMP(n-1) is changes from a
high level to a low level in an order of CMP1.fwdarw. . . .
.fwdarw.CMP(n-2).fwdarw.CMP(n-1) with an increase in the power
source voltage VDD contrary to the explanation given in the first
embodiment.
[0169] All the outputs of the comparators CMP1 through CMP(n-1) are
set to a high level, and, furthermore, each of the level converters
60-1 through 60-(n-1) converts a high level output signal (a high
level signal having VDD voltage as a reference) of the comparators
CMP1 through CMP(n-1) to a high level at the output voltage value
Vz of the charged pump circuit 10 with the result that all the PMOS
transistors MP1 through MP(n-1) inserted between the input terminal
100 to which the power source voltage VDD is supplied and each of
the nodes N1 through N(n-1) of the NMOS diodes ND1 through NDn are
set to an OFF state. Consequently, the charged pump circuit 10 is
operated in all of the first step through nth step and is operated
in the same manner as the conventional charged pump circuit shown
in FIG. 14 with the result that the output voltage Vz of the
charged pump circuit 10, the Zener current Iz which flows through
Zener diodes ZD1 and ZD2, and the average consumed current IDD will
be defined in the following manner.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (40)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (41)
IDD=n.multidot.(Iout+Iz) (42)
[0170] Here, Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (43)
[0171] When the output of the comparator CMP1 changes from a high
level to a low level with an increase in the power source voltage
VDD, the first step of the charged pump circuit 10 is constituted
in such a manner that the output of the CMP1 is input to one of the
input terminals of the NAND gate NA1 for driving the first step
with the result that the operation of the circuit is suspended
irrespective of the clock signal .phi.1 which is input to the other
input terminal of the NAND gate NA1.
[0172] Furthermore, since the low level signal output from the
comparator CMP1 is input to the gate of the PMOS transistor MP1 via
the level converter 60-1, the PMOS transistor MP1 is set to an OFF
state at this time. As a consequence, since the power source
voltage VDD is supplied to the node N1 via the PMOS transistor MP1,
the charged pump circuit 10 is operated from the second step
through nth step. When it is assumed that the voltage fall of the
power source voltage VDD which is generated in the PMOS transistor
MP1 cannot be ignored, the output voltage Vz of the charged pump
circuit 10 in the case of the suspension of the first step, the
Zener current Iz which flows through the Zener diodes ZD1 and ZD2,
and the average consumed current IDD will be defined in the
following manner.
Vz=VDD+(n-1).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (44)
Iz=(Vout-Vz)/(n-1).multidot.C.multidot.f (45)
IDD=(n-1).multidot.(Iout+Iz) (46)
[0173] Here, Vout will be defined in the following manner.
Vout=VDD+(n-1).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (47)
[0174] Furthermore, when the output of the comparator CMP2 changes
from a high level to a low level with an increase in the power
source voltage VDD, the operation of the second step is suspended
next to the first step, and the output voltage Vz of the charged
pump circuit 10, the Zener current Iz which flows through the Zener
diodes ZD1 and ZD2, and the average consumed current IDD will be
defined in the following manner.
Vz=VDD+(n-2).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (48)
Iz=(Vout-Vz)/(n-2).multidot.C.multidot.f (49)
IDD=(n-2).multidot.(Iout+Iz) (50)
[0175] Here, Vout will be defined in the following manner.
Vout=VDD+(n-2).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (51)
[0176] In this manner, the output of the comparator CMP1 through
CMP(n-1) changes from a high level to a low level in an order
of
[0177] CMP1.fwdarw.CMP2.fwdarw. . . . .fwdarw.CMP(n-1)
[0178] with an increase in the power source voltage VDD with the
result that the operation of the charged pump circuit 10 is
suspended in an order of the
[0179] first step.fwdarw.the second step.fwdarw. . . .
.fwdarw.(n-1)th step.
[0180] As a consequence, the n item representing the number of
steps of the charged pump can be changed in an order of
n.fwdarw.(n-1).fwdarw. . . . .fwdarw.2 along with an increase in
the power source voltage VDD, and the number of steps of the
charged pump which are actually operated can be decreased along
with an increase in the power source voltage VDD.
[0181] The relation between the value of the power source voltage
VDD and the number of steps of the charged pump which are actually
operated can be freely set by selecting a resistance ratio of the
voltage dividing resistors R1, R2 and R3 of the voltage dividing
circuit 15, a value of the offset resistance Ra of each of the
comparators, and the constant current value Ia of the constant
current source 15.
[0182] The drive control circuit of the charged pump circuit
according to the third embodiment of the invention has a voltage
dividing circuit 15 which serves as a power source detecting
circuit for detecting the power source voltage VDD, comparators
CMP1 through CMP(n-1) and the NAND gates NA1 through NAn which
serve as a control circuit for changing the number of drive steps
of the charged pump circuit in accordance with the detected output
of the voltage dividing circuit 15, PMOS transistors MP1 through
MP(n-1) which serve as a by-pass circuit for allowing the
aforementioned power source voltage to be by-passed in such a
manner that the voltage is supplied to the input side at the first
step out of the drive steps in accordance with a change in the
number of drive steps of the charged pump circuit and level
converters 60-1 through 60-(n-1) with the result that the number of
drive steps of the charged pump can be changed in accordance with
the increase and decrease of the power source voltage VDD.
[0183] Consequently, in the case where the output average current
(load current) value Iout in the conventional charged pump circuit
is constant, it is possible to inhibit an increase in an unutilized
Zener current Iz which flows through the Zener diodes for use in
the output voltage clamp at the time of an increase in the power
source voltage VDD, and an increase in the average consumed current
IDD as a result of an increase of this Zener current Iz.
[0184] In the case where all the steps of the charged pump circuit
are operated in the drive control circuit of the charged pump
circuit according to the first embodiment of the invention, a high
voltage is applied to a portion between the source and the drain of
the NMOS transistor MN1 which constitutes a by-pass circuit with
the result that it becomes necessary to take measures to provide a
large area which is grounded from the device periphery of the NMOS
transistor MN1 so that NPN bipolar transistor which the NMOS
transistor MN1 has in a parasitic manner is not turned on with a
substrate leak of the NMOS transistor MN1.
[0185] On the other hand, according to the third embodiment, in the
case where all the steps of the charged pump circuit are operated,
it is the PMOS transistor MP(n-1) that a high voltage is applied to
a portion between the drain and source thereof. In this manner,
there is an advantage in that it cease to happen that the parasitic
NPN bipolar transistor is turned on and operated with the substrate
leak simply because it is the PMOS transistor that a high voltage
is applied to a portion between the drain and the source. Thus, the
third embodiment is advantageous in the case where an endurance
against pressure in the NMOS transistor is not sufficient against
the output voltage of the charged pump circuit.
[0186] Fourth Embodiment of the Invention
[0187] A structure of the drive control circuit of the charged pump
circuit according to a fourth embodiment of the invention is shown
in FIG. 7. The drive control circuit of the charged pump according
to the fourth embodiment of the invention has a Zener current
detecting circuit 30 for detecting a Zener current which flows
through the Zener diodes for use in the output voltage clamp,
comparators CMP1 through CMP(n-1) for comparing the detected output
of the Zener current detecting circuit 30 and the input offset
voltage, NAND gates NA1 through NAn, PMOS transistors MP1 through
MP(n-1) connected between each of the nodes N2 through Nn of the
NMOS diodes ND2 through NDn and the input terminal 100 of the
charged pump circuit 10, and level converters 60-1 through 60-(n-1)
for converting the high level output of the comparators CMP1
through CMP(n-1) to a level of the output voltage Vz of the charged
pump circuit 10.
[0188] In each of the PMOS transistors MP1 through MP(n-1), the
drain is connected to the side of each of the nodes N2 through Nn
of the NMOS diodes ND1 through NDn, and the source is connected to
the input terminal 100 to which the power source voltage VDD is
supplied, and the gate is connected to the output terminal of each
of the level converters 60-1 through 60-(n-1). Furthermore, in each
of the PMOS transistors MP1 through MP(n-1), the source and the
substrate thereof are short-circuited.
[0189] Each of the output terminals of the comparators CMP1 through
CMP(n-1) is connected to one of the input terminals of the NAND
gates NA1 through NA(n-1). To the other input terminals, either the
clock signal .phi.1 or the clock signal .phi.2 is supplied from the
circuit 20 for generating a clock for driving the charged pump.
[0190] The structures of the charged pump circuit 10, and the
circuit 20 for generating a clock for driving the charged pump are
the same as the counterparts of the first embodiment. The structure
of the fourth embodiment is the same as the counterpart of the
first embodiment in that the zener diodes ZD1 and ZD2 for use in
the output voltage clamp are connected between the output terminal
200 of the charged pump circuit 10 and the earth. Therefore,
overlapped explanation thereof will be omitted.
[0191] Furthermore, concrete structures of the Zener current
detecting circuit 30 and the comparators CMP1 through CMP(n-1) are
the same as the counterparts of the second embodiment. At the same
time, since the structure of level converters 60-1 through 60-(n-1)
is the same as the counterpart of the third embodiment, the
structure of the Zener current detecting circuit 30 is the same as
the structure shown in FIG. 3, the structure of the comparators
CMP1 through CMP(n-1) is the same as the counterpart shown in FIG.
4, and the structure of level converters 60-1 through 60-(n-1) is
the same as the counterpart shown in FIG. 6, the same components
are denoted by the same reference numerals, and overlapped
explanation thereof will be omitted.
[0192] The structure of the comparators CMP1 through CMP(n-1) is
the same as the structure shown in FIG. 4. However, in that in each
of the comparators according to the fourth embodiment, the
connection relation between the B input terminal and the F input
terminal to which control data is input for switching over the
resistance values of the offset resistors for setting the input
offset voltage is different from the drive control the third
embodiment of the invention shown in FIG. 3. In other words, in the
drive control circuit according to the fourth embodiment, as shown
in FIG. 7, each of the B input terminals of the comparators CMP1
through CMP(n-2) is connected to the output terminal of the
comparators CMP2 through CMP(n-1) at the adjacent rear steps. Each
of the F input terminals of the comparators CMP1 through CMP(n-1)
is connected to the output terminal of the comparators CMP1 through
CMP(n-2) at the adjacent front step. The F input terminal of the
comparator CMP1 is grounded. The B input terminal of the comparator
CMP(n-1) is connected to the power source line for supplying the
power source voltage.
[0193] The comparators CMP1 through CMP(n-1) are constituted in
such a manner that the output state changes in accordance with at
least one of the detected output of the Zener current detecting
circuit 30 and the power source voltage thereof.
[0194] The Zener current detecting circuit 30 corresponds to the
current detecting circuit of the invention, the comparators CMP1
through CMP(n-1) and the NAND gates NA1 through NA(n'1) correspond
to the control circuit of the invention, and the PMOS transistors
MP1 through MP(n-1) and the level converters 60-1 through 60-(n-1)
correspond to the by-pass circuit of the invention,
respectively.
[0195] In the aforementioned structure, in the same manner as the
Zener current detecting circuit 30 according to the second
embodiment of the invention, the input voltage which is applied to
a portion between the reversed input terminal and the non-reversed
input terminal of the comparators CMP1 through CMP(n-1) is a
voltage between both terminals of the current detecting resistor
R4, and the input voltage VR4 of the comparator CMP1 through
CMP(n-1) will be defined in the following manner when the input
voltage is denoted by VR4.
VR4=R4.multidot.(Iz-2.multidot.Ic) (52)
[0196] At the time of the start of the operation, the output
voltage Vz of the charged pump circuit 10 is lower than the sum of
the Zener currents Vz1 and Vz2 of the Zener diodes ZD1 and ZD2. In
the state in which the Zener current Iz hardly flows, namely, in
the state state in which the voltage VR4 across both terminals of
the current detecting resistor R4 is represented by the
mathematical expression of VR4.apprxeq.0V, the output voltage of
all the comparators CMP1 through CMP(n-1) is set to a high level,
and each of the input offset voltages Vio1 through Vio(n-1) of the
comparators CMP1 through CMP(n-1) at that time will be defined in
the following manner. 8 Vio1 = ( Ra + Rb - Rc ) Ia Vio ( n - 2 ) =
( Ra + Rb + Rc ) Ia Vio ( n - 1 ) = ( Ra + Rb + Rc ) Ia ) ( 53
)
[0197] At this time, since the input offset voltage Vio1 of the
comparator CMP1 is set to a value smaller than the input offset
voltages Vio2 through Vio(n-1) of other comparators CMP2 through
CMP(n-1). When the input voltage VR4 which is applied to a portion
between the non-reversed input terminal and the reversed input
terminal becomes larger than the input offset voltage Vio set in
each of the comparators, the output of each of the comparators
changes from a high level to a low level.
[0198] In the state represented by the mathematical expression
(53), the input offset voltage Vio1 of the comparator CMP1 becomes
smaller than the input voltage Vio2 through Vio(n-1) of the other
comparators CMP2 through CMP(n-1) with the result that the output
of the comparator CMP1 changes from a high level to a low level in
the very beginning in the case where the Zener current Iz has
increased and the input voltage VR4 of each of the comparators has
increased as a result of an increase in the power source voltage
VDD and a decrease in the output average current Iout.
[0199] Until the output of the comparator CMP1 changes from a high
level to a low level, the output of the comparators CMP1 through
CMP(n-1) is all set to a high level. Furthermore, each of the level
converters 60-1 through 60-(n-1) convert the high level output
voltage (high level signals which references the VDD voltage) of
the comparators CMP1 through CMP(n-1) to a high level at the output
voltage value with the result that the PMOS transistors MP1 through
MP(n-1) which are inserted between the input terminal to which the
power source voltage VDD is supplied and each of the nodes N2
through Nn of the NMOS diodes ND2 through NDn are all set to an off
state. Consequently, the charged pump circuit 10 is operated all
from the first step to the nth step. The charged pump circuit 10 is
operated in the same manner as the conventional charged pump
circuit shown in FIG. 14 with the result that the output voltage Vz
of the charged pump circuit 10, the Zener current Iz which flows
through the Zener diodes ZD1 and ZD2 and the average consumed
current IDD will be defined in the following manner.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (54)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (55)
IDD=n.multidot.(Iout+Iz) (56)
[0200] Here, Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (57)
[0201] The voltage VR4 across both terminals of the current
detecting resistor VR4 which is an input voltage of the comparators
CMP1 through CMP (n-1) increases to be set to a state represented
by the mathematical expression of VR4>Vio1
(VR4=R4.multidot.(Iz-2Ic), and Vio1=(Ra+Rb+Rc).multidot.Ia), the
output of the comparator CMP1 changes from a high level to a low
level.
[0202] At the first step of the charged pump circuit 10, a clock
signal .phi.1 is supplied via one of the input terminals of the
NAND gate NA1 from the circuit 20 for generating a clock for
driving the charged pump. However, since the output (on a low
level) of the comparator CMP1 serves as the other input of the NAND
gate NA1, the operation of the first step of charged pump circuit
10 is suspended.
[0203] Furthermore, since the output (on a low level) of the
comparator CMP1 is input to the gate of the PMOS transistor PM1 via
the level converter 60-1, the PMOS transistor MP1 is turned on at
this time. As a consequence, since the power source voltage VDD is
supplied to the node N2 of the NMOS diode ND2 via the PMOS
transistor MP1, the operation of the charged pump circuit is
suspended from the second step to the nth step. When it is assumed
that the voltage fall of the power source voltage VDD which is
generated at the PMOS transistor MP1 can be ignored, the output
voltage Vz of the charged pump circuit 10, the Zener current Iz,
and the average consumed current IDD will be defined in the
following manner in the case where the operation of the first step
is suspended.
Vz=VDD+(n-1).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (58)
Iz=(Vout-Vz)/(n-1).multidot.C.multidot.f (59)
IDD=(n-1).multidot.(Iout+Iz) (60)
[0204] Here, Vout will be defined in the following manner.
Vout=VDD+(n-1).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (61)
[0205] In this case, since the output of the comparator CMP1 has
changed from a high level to a low level, the input offset voltage
Vio1 of the comparator CMP1 changes.
[0206] Furthermore, since the F input of the comparator CMP2 has
changed from a high level to a low level, the input offset voltage
Vio2 of the comparator CMP2 also changes. Consequently, the input
offset voltages Vio1 through Vio(n-1) of the comparator CMP1
through CMP(n-1) change in the following manner as shown below in
accordance with the mathematical expressions (23) and (24). 9 Vio (
n - 1 ) = ( Ra + Rb + Rc ) Ia Vio3 = ( Ra + Rb + Rc ) Ia Vio2 = (
Ra + Rb - Rc ) Ia Vio1 = ( Ra - Rb - Rc ) Ia ) ( 62 )
[0207] The input offset voltage Vio2 of the comparator CMP2 becomes
smaller than the input offset voltage Vio3 through Vio(n-1) of the
other comparators CMP3 through CMP(n-1) excluding the comparator
CMP1, and, at the same time, the input offset voltage Vio1 of the
comparator CMP1 becomes smaller than the input offset voltage Vio2
of the comparator CMP2. This state continues in the case where the
relation between the input voltage VR4 of the comparators CMP1
through CMP(n-1), the input offset voltage Vion of the comparator
CMP1, and the input offset voltage Vio2 of the comparator CMP2
stands in a relation of
Vio1(=(Ra-Rb-Rc).multidot.Ia)<VR4(=R4.multidot.(Iz-2Ic))<Vio2(=(Ra+-
Rb-Rc).multidot.Ia).
[0208] Supposing that the state represented by he mathematical
expression of
VR4=(R4.multidot.(Iz-2Ic))<Vio1(=(Ra-Rb-Rc).multidot.Ia) is
generated, the output of the comparator CMP1 changes from a low
level to a high level with the result that the relation between the
output voltage of the charged pump circuit 10 and the output
current thereof is brought back to a state represented by the
mathematical expressions (54) through (57) and the input offset
voltage Vio2 through Vion of the comparators CMP2 through CMPn is
brought back to a state represented by the mathematical expression
(53).
[0209] Contrary to this, when the voltage VR4 across both terminals
of the current detecting resistor R4 increases so that the state
represented by the mathematical expression of
Vio2(=(Ra+Rb-Rc).multidot.Ia)<VR4(=R4.m- ultidot.(Iz-2Ic)) is
generated, the output of the comparator CMP2 changes from a high
level to a low level. To the second step of the charged pump
circuit 10, the clock signal .phi.2 is supplied via one of the
input terminals of the NAND gate NA2 from the circuit 20 for
generating a clock for driving the charged pump. However, since the
output (on a low level) of the comparator CMP2 serves as the other
input of the NAND gate NAN2, the operation of the second step is
suspended. At this time, since the output (on a low level) of the
comparator CMP2 is input to the gate of the PMOS transistor MP2 via
the level converter 60-2, the PMOS transistor MP2 is turned off. As
a consequence, since the power source voltage VDD is supplied to
the third to nth steps of the charged pump circuit 10, the third to
nth steps of the charged pump circuit 10 is set to a state of
operation.
[0210] Supposing that the voltage fall of the power source voltage
VDD which is generated in the PMOS transistor MP2 can be ignored,
the output voltage Vz, the Zener current Iz which flows through the
Zener diodes ZD1 and ZD2, and the average consumed current IDD of
the charged pump circuit 10 will be defined in the following manner
in the case where the operation of the second step of the charged
pump circuit 10 is suspended.
Vz=VDD+(n-2).multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (63)
Iz=(Vout-Vz)/(n-2).multidot.C.multidot.f (64)
IDD=(n-2).multidot.(Iout+Iz) (65)
[0211] Here, Vout will be defined in the following manner.
Vout=VDD+(n-2).multidot.(VDD-VD-Iout/(C.multidot.f))-VD (66)
[0212] In this case, since the output of the comparator CMP2 has
changed from a high level to a low level, the input offset voltage
Vio2 of the comparator CMP2 changes. Furthermore, since the F input
of the comparator CMP3 has changed from a high level to a low
level, the input offset voltage Vio3 of the comparator CMP3 also
changes.
[0213] Furthermore, since the B input of the comparator CMP1 has
changed from a high level to a low level, the input offset voltage
Vio1 of the comparator CMP1 further changes as well.
[0214] Consequently, the input offset voltages Vio1 through
Vio(n-1) of the comparators CMP1 through CMP(n-1) change as shown
in the following mathematical expressions in accordance with the
mathematical expressions (23) and (24). 10 Vio ( n - 1 ) = ( Ra +
Rb + Rc ) Ia Vio4 = ( Ra + Rb + Rc ) Ia Vio 3 = ( Ra + Rb - Rc ) Ia
Vio 2 = ( Ra - Rb - Rc ) Ia Vio1 = - ( Ra + Rb + Rc ) Ia ) ( 67
)
[0215] The input offset voltage Vio3 of the comparator CMP3 becomes
smaller than the input offset voltages Vio4 through Vio(n-1) of the
other comparators CMP4 through CMP(n-1) excluding the comparators
CMP1 and CMP2, and, furthermore, the input offset voltage Vio2 of
the comparator CMP2 becomes smaller than the input offset voltage
Vio3 of the comparator CMP3. The input offset voltage Vio1 of the
comparator CMP1 becomes a negative input offset voltage when the
non-reversed input terminal of the comparator serves as a
reference. This state continues in the case where the relation
between the input offset voltage VR4 of each of the comparators,
the input offset voltage Vio2 of the comparator CMP2 and the input
offset voltage Vio3 of the comparator CMP3 is defined in the
following mathematical expression of
Vio2(=(Ra-Rb-Rc).multidot.Ia)<VR4-
(=R4.multidot.(Iz-2Ic))<Vio3(=Ra+Rb-Rc).multidot.Ia)
[0216] Supposing that the state represented by the mathematical
expression of
VR4(=R4.multidot.(Iz-2Ic))<Vio2(=(Ra-Rb-Rc).multidot.Ia) is
generated, the output of the comparator CMP2 changes from a low
level to a high level so that the relation between the output
voltage of the charged pump circuit 10 and the output current
thereof is brought back to the state represented by the
mathematical expressions (58) through (61), and the input offset
voltages Vio1 through Vio(n-1) of the comparators CMP1 through
CMP(n-1) are brought back to the state represented by the
mathematical expression (62).
[0217] Contrary to this, the voltage across both terminals of the
current detecting resistor R4 increases so that the state
represented by the mathematical expression of
Vio3(=(Ra+Rb-Rc).multidot.Ia)<VR4(=R4.multi- dot.(Iz-2Ic)) is
generated, the comparator CMP3 changes from a high level to a low
level. As a consequence, the operation of the third step of the
charged pump circuit 10 is also suspended.
[0218] As has been explained above, the output of the comparators
CMP1 through CMP(n-1) changes from a high level to a low level in
an order of CMP1.fwdarw.CMP2.fwdarw. . . . .fwdarw.CMP(n-1) in
accordance with an increase in the Zener current Iz which flows
through the Zener current detecting circuit 30, and the operation
of the charged pump circuit 10 is suspended in an order of the
first step.fwdarw.the second step.fwdarw. . . . .fwdarw.(n-1)th
step.
[0219] Consequently, the nth item which represents the number of
steps of the charged pump in the relation expressions (54) through
(57) between the output voltage of the charged pump circuit 10 and
the output current thereof can be changed from
n.fwdarw.(n-1).fwdarw. . . . .fwdarw.2 so that the number of the
steps of the charged pump which are actually operated can be
changed in such a manner that the number is decreased with an
increase in the Zener current Iz. The relation between the current
value of the Zener current detecting circuit 30 and the number of
steps of the charged pump circuit 10 which are actually operated
can be freely set with the offset resistance ratio of the offset
resistors Ra, Rb and Rc of each of the comparators (CMP1 through
CMP(n-1)) and the constant current value Ia of the constant current
source 50 of each of the comparators.
[0220] The drive control circuit of the charged pump circuit
according to the fourth embodiment of the invention has a Zener
current detecting circuit 30 which serves as a current detecting
circuit for detecting a current which flows through the Zener
diodes for use in the output voltage clamp connected between the
output terminal of the charged pump circuit and the earth,
comparators CMP1 through CMP(n-1) and NAND gates NA1 through NAn
which serve as a control circuit for changing the number of drive
steps of the charged pump circuit in accordance with at least one
of the detected output of the Zener current detecting circuit 30
and the power source voltage, and NMOS transistors MP1 through
MP(n-1) and level converters 60-1 through 60-(n-1) which serve as a
by-pass circuit for allowing the aforementioned power source
voltage to be by-passed in such a manner that the power source
voltage is to be supplied to the input side of the first step out
of the drive steps in accordance with a change in the number of
drive steps of the charged pump circuit with the result that the
number of steps of the charged pump circuit which are actually
operated can be changed in accordance with an increase and a
decrease in the power source voltage VDD. Consequently, in the case
where the output average current (load current) value Iout in the
conventional charged pump circuit is constant, it is possible to
inhibit an increase in an unutilized Zener current Iz which flows
through the Zener diodes for use in the output voltage clamp, and
an increase in the average consumed current IDD as a result of an
increase in this Zener current Iz.
[0221] Furthermore, according to the fourth embodiment of the
invention, since the unutilized Zener current which flows through
the Zener diodes for use in the output voltage clamp is detected
with the Zener current detecting circuit, and the number of drive
steps of the charged pump circuit is changed in accordance with an
increase and a decrease in the Zener current Iz in the same manner
as the second embodiment, it is possible to prevent an increase in
the unutilized Zener current Iz along with a change in the output
average current (load current) value in the charged pump circuit,
and an increase in the average consumed current IDD as a result of
an increase in this Zener current Iz.
[0222] Furthermore, in the drive control circuit of the charged
pump circuit according to the second embodiment of the invention,
in the case where all the steps of the charged pump circuit are
operated, a high voltage is applied to a portion between the source
and the drain of the NMOS transistor MN1 constituting the by-pass
circuit with the result that it becomes necessary to take measures
to provide a large area which is grounded from the device periphery
of the NMOS transistor MN1 in such a manner that the NPN bipolar
transistor which the NMOS transistor has in a parasitic manner is
not turned on with a substrate leak of the NMOS transistor MN1.
[0223] On the other hand, in the fourth embodiment, in the case
where all the steps of the charged pump circuit are operated, it is
the PMOS transistor constituting the by-pass circuit that a high
voltage is applied to a portion between the drain and the source.
Since, it is the PMOS transistor constituting the by-pass circuit
that a high voltage is applied to a portion between the drain and
the source in this manner, there is an advantage in that it will
cease to happen that the parasitic NPN bipolar transistor is turned
on with the substrate leak. In the case where the metal wiring
layer is small and the endurance of the NMOS transistor against the
pressure is not sufficient against the output voltage of the
charged pump circuit, the output load current of the charged pump
circuit changes in accordance with the operation power source
voltage and is effective in the case where the operation insurance
power source voltage scope is large.
[0224] Fifth Embodiment of the Invention
[0225] A structure of the drive control circuit of the charged pump
circuit according to the fifth embodiment of the invention is shown
in FIG. 8. In FIG. 8, the drive control circuit of the charged pump
circuit according to the fifth embodiment comprises a constant
current source circuit 70 for generating a constant current having
a negative power source voltage dependency constant, an oscillation
circuit 80 driven by a constant current having the negative power
source voltage dependency constant which current is generated by
the constant current generating circuit 70 for generating a pulse
signal of a frequency having a negative power source dependency
constant, and a clock signal supply circuit 20 for supplying two
kinds of clock signals .phi.1 and .phi.2 which change in levels in
a compensating manner so that the high level periods do not overlap
each other.
[0226] The constant current source circuit 70 comprises PMOS
transistors P14 and P15, a resistor R0, and a constant current
source 72. The source and the gate of the PMOS transistors P14 and
P15 are commonly connected so that the power source voltage VDD is
supplied to the source of the PMOS transistors P14 and P15. The
drain of the PMOS transistor P14 is grounded via the resistor R0.
The drain and the gate of the PMOS transistor P14 are
short-circuited. Furthermore, the drain of the PMOS transistor P15
is grounded via the constant current source 72, and, at the same
time, the drain of the PMOS transistor P15 is grounded to the drain
of the PMOS transistor P16 of the oscillation circuit 80. The PMOS
transistors P14 and P15 constitutes a current mirror circuit.
[0227] The oscillation circuit 80 comprises inverters 82, 83 and 84
having an odd-number of steps which are connected in a ring-like
manner, and PMOS transistors P16 through P20 and NMOS transistors
N12 through N15 for driving these inverters 82, 83 and 84. The
sources and the gates of the PMOS transistors P16 through P20 are
commonly connected. A high power source voltage VDD is supplied to
the source.
[0228] The PMOS transistors P16 through P20 constitute a current
mirror circuit. The sources and the gates of the NMOS transistors
are connected in common, and the sources thereof are grounded.
[0229] Furthermore, the drain of the PMOS transistor P16 is
grounded via the constant current source 72 of the constant current
power circuit 70. The drain of the PMOS transistor P17 is connected
to the drain of the NMOS transistor N12. The drain of the NMOS
transistor N12 is connected to the gate of the NMOS transistor N13.
The drains of the PMOS transistors N18 through N20 are connected to
the source of the PMOS transistors of the CMOS inverters
constituting inverters 82 through 84 respectively.
[0230] Furthermore, the drains of the NMOS transistors N13 through
N15 are connected to the sources of the NMOS transistors of CMOS
inverters constituting the inverters 82 through 84. Refrence Cn
refers to a load capacity of the inverters 82 through 84.
[0231] The charged pump circuit 10' has the same structure as the
conventional charged pump circuit shown in FIG. 14. The circuit 20
for generating a clock for driving the charged pump has the same
structure as the circuit shown in FIG. 11. Therefore, overlapped
explanation thereof will be omitted.
[0232] In the aforementioned structure, since the PMOS transistors
P14 and P15 of the constant current source circuit 70 constitute a
current mirror circuit, a current which flows to the resistor R0
from the PMOS transistor P14 becomes equal to the current 101 which
flows into the constant current source 72 from the PMOS transistor
15. Consequently, when the threshold voltage of the PMOS transistor
P14 of the constant current source circuit 70 is denoted by Vtmp,
the output current I1 of the constant current source circuit 70 is
given as a difference between the constant current I0 of the
constant current source circuit 72, and the current I01 I01 which
flows into the constant current source 72 which is determined by
the threshold value voltage Vtmp of the PMOS transistor P14, the
resistance value R0 of the resistor R0, and the voltage value of
the power source voltage VDD. Since the current I01 can be
represented by the mathematical expression of (VDD-Vtmp)/R0, the
following mathematical expression is established.
I1=I0-(VDD-Vtmp)/R0 (68)
[0233] It has been made clear from the mathematical expression (68)
that the output voltage I1 of the constant current source circuit
70 for driving the oscillation circuit 80 has a negative power
source voltage dependency constant.
[0234] On the other hand, in the oscillation circuit 80, since the
PMOS transistors P16 through P20 for driving the inverters 82
through 84 constitute the current mirror circuit, the output
current I1 which is generated from the constant current source
circuit 70 flows to the PMOS transistor P16 with the result that
the voltage between respective gates and sources of the PMOS
transistors P16 through P20 becomes equal because the gates and
sources of the PMOS transistors P16 through P20 are connected in
common. Then, the current I1 flows to each of the PMOS transistors
P16 through P20. The NMOS transistors N12 through N15 are operated
in such a manner that the current I1 is drawn via inverters 82
through 84. As a consequence, each of the load capacities Cn of the
inverters 82 through 84 are charged and discharged with the current
I so that a pulse signal of the frequency f which is determined by
the delay time with respect to the input signal of inverters 82
through 84 and the number of steps of inverters 82 through 84.
Here, when the number of steps of the inverters is denoted by N,
the delay time in which the output changes from a high level to a
low level out of the delay time of the inverters is denoted by
TPLH, and the delay time when the output has changed from a high
level to a low level with a change in the input from a low level to
a high level is denoted by TPHL, the oscillation frequency f can be
defined in the following manner.
f=1/(2N+1).multidot.(TPLH+TPHL) (69)
[0235] When the output current I1 of the constant current source
circuit 70 increases, and the current which is supplied to each of
the inverters 82, 83 and 84 (each of the drain currents of the PMOS
transistors P18, P19 and P20) increases, the time which is required
for the charge and the discharge of the load capacity Cn of the
input node of the inverters at the next step which is connected
after each of the inverters is shortened. Consequently, the
oscillation frequency becomes higher.
[0236] On the other hand, when the output current I1 of the
constant current source circuit 70 decreases, and the current which
is supplied to each of the inverters 82, 83, and 84 increases, the
time which is required for the charge and the discharge of the load
capacity Cn of the input node of the inverters at the next step
connected after each of the inverters increases so that the
oscillation frequency is lowered. Consequently, the oscillation
frequency f of the oscillation circuit 80 changes in proportion to
the constant current I1 which is an output current of the constant
current source circuit 70. Since the constant current I1 of
constant current source circuit 70 has a negative power source
voltage dependency constant, the oscillation frequency f of the
oscillation circuit 80 also has a negative power source dependency
constant.
[0237] The pulse signal of the frequency f which is generated by
the oscillation circuit 80 is output to the circuit 20 for
generating a clock for driving the charged pump, and the circuit 20
for generating a clock for driving the charged pump prepares two
kinds of clock signals .phi.1 and .phi.2 which change in levels in
a compensating manner so that the high level periods do not overlap
each other, and the two clock signals .phi.1 and .phi.2 are
supplied to the charged pump circuit 10'.
[0238] Since the charged pump circuit 10' shown in FIG. 8 is
operated in the same manner as the conventional charged pump
circuit shown in FIG. 14, the output voltage Vz of the charged pump
10', the Zener current Iz which flows through the Zener diodes ZD1
and ZD2 and the average output consumption current IDD will be
defined in the following manner.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (70)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (71)
IDD=n.multidot.(Iout+Iz) (72)
[0239] Here, Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (73)
[0240] When the oscillation frequency f of the oscillation circuit
80 is set to a lower level at an appropriate constant in accordance
with an increase in the power source voltage VDD, it is possible to
inhibit an increase in the Zener current Iz along with an increase
in the power source voltage VDD.
[0241] In the drive control circuit of the charged pump circuit
according to the fifth embodiment of the invention, since the
constant current having a negative power source voltage dependency
constant is generated with the constant current source circuit, the
pulse signal of the frequency having a negative power source
voltage dependency constant is generated with the oscillation
circuit which is driven with the constant current which has a
negative power source voltage dependency constant, and the charged
pump circuit is driven with the clock having the aforementioned
frequency at the clock signal supply circuit, the operation
frequency of the charged pump circuit can be changed in accordance
with an increase and a decrease in the power source voltage
VDD.
[0242] Consequently, in the case where the output voltage average
current (load current) value Iout in the conventional charged pump
circuit is constant, it is possible to inhibit an increase in the
unutilized Zener current Iz which flows through Zener diodes for
use in the output voltage clamp at the time of an increase in the
power source voltage VDD, and an increase in the average consumed
current IDD as a result of an increase in this Zener current
Iz.
[0243] Furthermore, in the fifth embodiment of the invention, in
the case where the power source voltage VDD changes when the
charged pump circuit is operated, a response is given in such a
manner that the operation frequency of the charged pump circuit
changes instantly with respect to the change in the power source
voltage with the result that the fifth embodiment is effective in
the case where the change in the output load current of the charged
pump circuit is small with respect to the change in the power
voltage, but the power source voltage change can be generated
during the operation.
[0244] Sixth Embodiment of the Invention
[0245] The drive control circuit of the charged pump circuit
according to the sixth embodiment of the invention comprises a
Zener current detecting circuit 30 for detecting a current which
flows through Zener diodes for use in the output voltage clamp
connected between the output terminal 200 of the charged pump
circuit 30 and the earth, a constant current source circuit 90 for
fetching the detected output of the Zener current detecting circuit
and generating the constant current which stands in inverse
proportion to a value of the current which flows through the
aforementioned Zener diodes, an oscillation circuit 80 which is
driven by the constant current source circuit 90 for generating a
pulse signal of a frequency which stands in inverse proportion to
the value of the current which flows through the aforementioned
Zener diodes, and a clock signal supply circuit 20 for preparing
two kinds of clock signals which change in levels in a compensating
manner so that the high level periods do not overlap each other on
the basis of the pulse signal output from the oscillation circuit
80 and supplying the two kinds of clock signals to the charged pump
circuit 10'.
[0246] Since the charged pump circuit 10', the circuit for
generating a clock for driving the charged pump 20, and the
oscillation circuit 80 have the same structure as the fifth
embodiment of the invention shown in FIG. 8, and the Zener current
detecting circuit 30 has the same structure as the second and the
fourth embodiment of the invention, the same components are denoted
by the same reference numerals. An overlapped explanation thereof
will be omitted as much as possible.
[0247] The Zener current detecting circuit 30 has a current
detecting resistor R4 connected in series to the Zener diodes ZD1
and ZD2 for use in the output voltage clamp connected between the
output terminal 200 of the charged pump circuit 10' and the earth,
the NMOS transistors N3 through N6, and constant current sources 32
and 34, and devices are selected such that the characteristics of
the NMOS transistors N3 and N4 are the same, and the
characteristics of the NMOS transistors N5 and N6 are the same. The
constant of each of the devices in the Zener current detecting
circuit 30 is selected so that the constant current Ic flows into
the constant current sources 32 and 34.
[0248] From a location between the connection point m1 between the
source of the NMOS transistor N6 and the constant current source
32, and the connection point m2 between the source of the NMOS
transistor N5 and the constant current source 34, the detected
output of the Zener current detecting circuit 30, namely, the
detected voltage obtained by converting into a voltage the Zener
current which flows through the Zener diodes ZD1 and ZD2 for use in
the output voltage clamp can be output.
[0249] A concrete structure of the constant current source circuit
90 is shown in FIG. 10. In FIG. 10, the sources of the PMOS
transistors P21, P22, P23, P24 and P25 are connected in common so
that the power source voltage VDD is supplied thereto. The drains
and the gates of the PMOS transistors P22 and P24 are
short-circuited, respectively. The gates of the PMOS transistors
P21, P22 and P23 are connected in common. The gate of the PMOS
transistor P24 is connected to the gate of the PMOS transistor P25.
The drain of the PMOS transistors P22 and P23 are connected to the
drains of the NMOS transistors N26 and N27, respectively. The
source of the NMOS transistor N26 and the source of the NMOS
transistor N27 are connected via a resistor Ri. The gate of the
NMOS transistor N26 is connected to the connection point m1 of the
Zener current detecting circuit 30, and the gate of the NMOS
transistor N27 is connected to the connection point m2 of the Zener
current detecting circuit 30, respectively. The drains of the NMOS
transistors N23 and N24 are connected in common. This connection
point thereof is connected to the connection point between the
resistor Ri and the source of the NMOS transistor N27. The drains
of the NMOS transistors N21 and N22 are connected in common, and
the connection point thereof is connected to the drain of the PMOS
transistor P21. The drain and the gate of the NMOS transistor N22
are connected.
[0250] A portion between the drain and the gate of the NMOS
transistor N20 is short-circuited. The gate of the NMOS transistor
N20 is connected to the gate of the NMOS transistor N21. The source
of the NMOS transistor N20 is grounded, and the drain thereof is
connected to the constant current source 90 for supplying the
constant current I01 to the NMOS transistor N20. The drain of the
PMOS transistor P24 is connected to the drain of the NMOS
transistor N25.
[0251] The drain of the PMOS transistor P25 is grounded via the
constant current source 94 into which the constant current I02
flows. It is constituted that the output current I1 for driving the
oscillation circuit 80 flows into the connection point between the
drain of the PMOS transistor P25 and the constant current source
94.
[0252] Furthermore, the sources of the NMOS transistors N20, N21,
N22, N23, N24, and N25 are connected in common and grounded. The
gate of the NMOS transistor N21 and the gate of the NMOS transistor
N23 are connected, and the gates of the NMOS transistors N22, N24
and N25 are connected in common.
[0253] The PMOS transistor N21 and the PMOS transistor N22, the
PMOS transistor N23 and the PMOS transistor P24, and the PMOS
transistor P24 and the PMOS transistor P25 constitute a current
mirror circuit respectively.
[0254] Furthermore, the NMOS transistor N22 and the NMOS transistor
N24, the NMOS transistor N22 and the NMOS transistor N25 constitute
the current mirror circuit respectively.
[0255] Furthermore, in the constant current source circuit 90
according to the fifth embodiment, the connection point between the
source of the NMOS transistor N27 and the resistor Ri constitutes
an imaginary earth point. The dimension ratio of the PMOS
transistors P21, P22 and P23 is set to P21:P22:P23=1:1:1, and, at
the same time, the dimension ratio of the NMOS transistors N22 and
N24 is set to N22:N24=1:2, and the dimension ratio of the NMOS
transistors N21 and N23 is set to N21:N23=1:2.
[0256] In the aforementioned structure, when the characteristics of
the NMOS transistor N3 and the NMOS transistor N4 in the Zener
current detecting circuit 30 are made to be the same, and the
characteristics of the NMOS transistor N5 and the NMOS transistor
N6 are made to be the same, the output voltage between the
connection points m1 and m2 becomes equal to the voltage VR4
between terminals of the current detecting resistor R4 for
detecting the Zener current Iz.
[0257] Consequently, the detected output VR4 of the Zener current
detecting circuit 30 will be defined in the following manner.
VR4=R4.multidot.(Iz-2Ic) (74)
[0258] On the other hand, in the constant current detecting circuit
90, the resistor Ri is connected between the source of the NMOS
transistor N26 having a gate connected to the connection point m1
and the source of the NMOS transistor N27 having a gate connected
to the connection point m2. The connection point between the source
of the NMOS transistor N27 and the resistor Ri serve as an
imaginary earth point. Furthermore, the PMOS transistor P22 and the
PMOS transistor N23 constitute the current mirror circuit.
Consequently, the drain current Ids which flows through the NMOS
transistor N26 and the NMOS transistor N27 become equal to each
other. As a consequence, the voltage Vgs between the gate and the
source becomes the same at the time of operation of the NMOS
transistor N26 and the NMOS transistor N27.
[0259] Consequently, the voltage applied to a portion between the
source of the NMOS transistor N26 and the source of the NMOS
transistor N27 becomes equal to the voltage VR4 across both
terminals of the current detecting resistor R4 of the Zener current
detecting circuit 30.
[0260] Furthermore, the dimension ratio of the devices of the PMOS
transistors P21, P22, and P23 is set to P21:P22:P23=1:1:1.
Furthermore, the device dimension ratio of the NMOS transistor N22
and the NMOS transistor N24 is set to N22:N24=1:2. Furthermore, the
device dimension ratio of the NMOS transistor N21 and the NMOS
transistor N23 is set to N21:N23=1:2. Consequently, in the case
where the device dimension ratio of the NMOS transistor N20 and the
NMOS transistor N21 is set to N20:N21=1:1, when the drain current
of the PMOS transistors P21, P22, P23 is set to Idsp21 through
Idsp23, and the drain current of the NMOS transistor N20 through
N24 is set to Idsn20 through Idsn24, the following relation is
established. 11 Idsn20 = Idsn21 = I01 Idsp21 = Idsp22 = Idsp23 =
I01 + VR4 / Ri = I01 + ( R4 ( Iz 2 Ic ) ) / Ri Idsn22 - Idsp23 -
Idsn21 = ( ( R4 ( Iz - 2 Ic ) ) / Ri Idsn23 = 2 Idsn21 = 2 I01
Idsn24 = 2 Idsp23 = 2 ( ( R4 ( Iz 2 Ic ) ) / Ri ( 75 )
[0261] Supposing that the device dimension ratio of the NMOS
transistor N22 and the NMOS transistor N25 is set to N22:N25=1:1,
and the device dimension of the PMOS transistor P24 and the PMOS
transistor P25 is set to P24:P25=1:1, the drain current which flows
through the NMOS transistor N22 and the NMOS transistor N25 becomes
equal because the NMOS transistor N22 and the NMOS transistor N23
constitute the current mirror circuit. Furthermore, the drain
current which flows through the PMOS transistor P24 and the PMOS
transistor P25 becomes equal because the PMOS transistor P24 and
the PMOS transistor P25 constitute the current mirror circuit.
Consequently, the drain current Idsn22 which flows through the NMOS
transistor N22 and the drain current Idsp25 which flows through the
PMOS transistor P25 becomes equal to each other.
[0262] Consequently, the output voltage I1 of the constant current
source circuit 90 will be defined in the following manner from the
mathematical expression (75).
I1=I02-((R4.multidot.(Iz-2Ic))/Ri (76)
[0263] It has been made clear from the mathematical expression (76)
that the output voltage I1 of the constant current source circuit
90 stands in inverse proportion (having a negative dependency
constant) to the Zener current Iz.
[0264] On the other hand, when the constant current I1 supplied by
the constant current source circuit 90 in the oscillation circuit
80 increases, and the current (respective drain currents of the
PMOS transistors P18, P19 and P20) supplied to respective inverters
82, 83 and 84 increase, the time required for the charge and
discharge of the load capacity of input nodes of the inverters at
next steps connected after respective inverters is shortened, and
the oscillation frequency f of the pulse signal to be output
becomes higher.
[0265] On the other hand, the constant current I1 supplied from the
constant current source circuit 90 decreases and the current
(respective drain currents of the PMOS transistors P18, P19 and
P20) supplied to each of the inverters 82, 83 and 84 decreases,
time required for the charge and discharge of the load capacity of
the input nodes of inverters at the next step connected after each
of the inverters increases and the oscillation frequency f of the
pulse signal is lowered.
[0266] Consequently, the oscillation frequency f of the oscillation
circuit 80 changes in proportion to the output current I1 of the
constant current source circuit 90. The output voltage I1 of the
constant current source circuit 90 stands in inverse proportion
(having a negative dependency constant) to the Zener current Iz.
Consequently, in the case where the Zener current increases and
decreases, the oscillation frequency f of the oscillation circuit
80 changes in inverse proportion to the Zener current Iz.
[0267] Since the charged pump circuit 10 is operated in the same
manner as the conventional charged pump circuit shown in FIG. 14,
the output voltage Vz of the charged pump circuit 10', the Zener
current Iz which flows through the Zener diodes ZD1 and ZD2 and the
average consumed current IDD will be defined in the following
manner.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD (77)
Iz=(Vout-Vz)/n.multidot.C.multidot.f (78)
IDD=n.multidot.(Iout+Iz) (79)
[0268] Here, Vout will be defined in the following manner.
Vout=VDD+n.multidot.(VDD-VD-Iout/(C.multidot.f))-VD (80)
[0269] In the sixth embodiment, since the oscillation frequency f
of the oscillation circuit 90 where the Zener current Iz determines
the frequency of the clock signal at an appropriate constant in
accordance with an increased amount can be lowered, it is possible
to suppress the value of the Zener current Iz by the lowering in
the frequency of the clock signal for driving the charged pump
circuit in the case where the Zener current Iz increases with an
increase in the power source voltage VDD and a change in the output
average current (load current) of the charged pump circuit.
[0270] In this manner, according to the sixth embodiment of the
invention, since the current which flows through the Zener diodes
for use in the output voltage clamp connected between the output
terminal of the charged pump circuit and the earth is detected with
the Zener current detecting circuit, the detected output of the
Zener current detecting circuit is fetched, and the constant
current which stands in inverse proportion to the value of the
current which flows through the aforementioned zener diodes is
generated, the pulse signal of the frequency which stands in
inverse proportion to the value of the current which flows through
the aforementioned Zener diodes with the oscillation circuit which
is driven with the constant current source circuit, and two kinds
of clock signals are supplied to the charged pump circuit by
preparing the aforementioned two kinds of two clock signals with
the clock signal supply circuit on the basis of the pulse signal
which is output from the oscillation circuit, it is possible to
change the operation frequency of the charged pump circuit in
accordance with an increase and a decrease in the Zener current
Iz.
[0271] Consequently, in the case where the output average current
(load current) value in the conventional charged pump circuit is
constant, it is possible to inhibit an increase in an unutilized
current which flows the Zener diodes for use in the output voltage
clamp along with an increase in the power source voltage VDD, and
an increase in the average consumed current IDD as result of an
increase in this Zener current Iz.
[0272] Furtheremore, according to the sixth embodiment, since the
unutilized Zener current which flows through the Zener diodes for
use in the output voltage clamp is detected with the Zener current
detecting circuit, and the operation frequency of the charged pump
circuit is changed in accordance with an increase and decrease in
the Zener current Iz, it is possible to prevent an increase in the
unutilized Zener current increases along with a change in the
output average current (load current) value Iout in the charged
pump circuit, and an increase in the average consumed current IDD
as a result in an increase in this Zener current Iz.
[0273] Furthermore, according to the sixth embodiment of the
invention, since a response is given in such a manner that the
operation frequency of the charged pump circuit changes in an
instant with respect to the change in the Zener current Iz, the
charged pump circuit according to the sixth embodiment is effective
in the case where the output load current of the charged pump
circuit frequently changes.
* * * * *