U.S. patent application number 09/366897 was filed with the patent office on 2002-01-24 for clock synthesizer with programmable input-output phase relationship.
Invention is credited to FOX, J. KEN, SEVALIA, PIYUSH.
Application Number | 20020008551 09/366897 |
Document ID | / |
Family ID | 26790266 |
Filed Date | 2002-01-24 |
United States Patent
Application |
20020008551 |
Kind Code |
A1 |
SEVALIA, PIYUSH ; et
al. |
January 24, 2002 |
CLOCK SYNTHESIZER WITH PROGRAMMABLE INPUT-OUTPUT PHASE
RELATIONSHIP
Abstract
A circuit comprising an oscillator, a reference path, and a
feedback path. The oscillator may have a reference input receiving
a reference signal, a feedback input receiving a feedback signal,
and an output. The reference path may provide the reference signal
from a reference clock input. The feedback path may provide the
feedback signal from the oscillator loop output. At least one of
the reference path and the feedback path comprises a programmable
delay circuit.
Inventors: |
SEVALIA, PIYUSH; (SUNNYVALE,
CA) ; FOX, J. KEN; (WOODINVILLE, WA) |
Correspondence
Address: |
CHRISTOPHER P. MAIORANA, P.C.
24025 GREATER MACK
SUITE 200
ST. CLAIR SHORES
MI
48080
US
|
Family ID: |
26790266 |
Appl. No.: |
09/366897 |
Filed: |
August 4, 1999 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60095469 |
Aug 5, 1998 |
|
|
|
Current U.S.
Class: |
327/105 |
Current CPC
Class: |
H03L 7/23 20130101; H03L
7/183 20130101; H03L 7/081 20130101; H03L 2207/10 20130101 |
Class at
Publication: |
327/105 |
International
Class: |
H03B 021/00 |
Claims
1. A clock circuit, comprising: an oscillator or loop, having a
reference input receiving a reference signal, a feedback input
receiving a feedback signal, and an output; a reference path
providing said reference signal from a reference clock input; and a
feedback path providing said feedback signal from the oscillator or
loop output; wherein at least one of the reference path and the
feedback path comprises a programmable delay circuit.
2. The circuit according to claim 1, wherein each of the reference
path and the feedback path comprises a programmable delay
circuit.
3. The circuit according to claim 1, further comprising a logic
circuit configured to select a characteristic or predetermined
delay for the programmable delay circuit.
4. The circuit according to claim 1, further comprising a divider
configured to provide a divided output from the oscillator or loop
output.
5. The circuit according to claim 1, further comprising: a second
oscillator or loop configured to provide a second output; and a
multiplexer configured to select one of the oscillator or loop
outputs as a clock output.
6. The circuit according to claim 5, wherein the logic circuit is
further configured to select an input for the feedback path from at
least two of the oscillator or loop output, the divided output, and
the clock output.
7. The circuit according to claim 1, wherein the reference path
further comprises a reference counter receiving the reference clock
input providing said reference signal therefrom, and the feedback
path further comprises a feedback counter receiving the reference
clock input providing said reference signal therefrom
8. A circuit comprising: means for generating an output in response
to (i) a reference input receiving a reference signal and (ii) a
feedback input receiving a feedback signal; means for generating
said reference signal from a reference clock input; and means for
generating said feedback signal from the oscillator or loop output,
wherein at least one of the reference path and the feedback path
comprises a programmable delay circuit.
9. A method of controlling a clock output, comprising the steps of:
producing the clock output in response to a reference input and a
feedback input; and delaying at least one of the reference input
and the feedback input by a programmable amount of time to thereby
control the clock output.
10. The method according to claim 9, further comprising the step of
programming one or more programmable elements controlling the
programmable amount of time.
Description
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/095,469, filed Aug. 5, 1998, which is hereby
incorporated by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a clock synthesizer with a
programmable input-output phase relationship generally and, more
particularly, to a PLL-based clock synthesizer with a programmable
input-output phase relationship for generating output frequencies
based on a reference clock input.
BACKGROUND OF THE INVENTION
[0003] A PLL-based clock synthesizer generates output frequencies
based on a reference clock input. The output clock frequency
usually has no integral relationship (i.e., the ratio of the output
clock frequency to an input clock frequency (or vice-versa) is an
integer) to the input clock frequency. However, the input and
output clocks are related by the relationship that there are Q
cycles of the input clock for every P cycles of the output clock,
where P and Q are integers. In some cases, it may be useful to have
a known phase relationship between the input and output clocks.
This is most often the case when either P/Q or Q/P is an integer,
but that is not always required. The input-output delay depends on
the difference between the delay of the logic in the reference path
and the delay in the logic of the output path (which begins at the
phase detector inputs, where the phase error is zero). The logic
delays are delays through multiplexers, counters, post-dividers,
etc.
[0004] The phase relationship in a zero-delay buffer may depend on
the location of a tap in the feedback path in the ring oscillator.
Additionally, zero-delay buffers usually have dividers either in
the reference path or the feedback path. Thus, zero-delay buffers
tend to be less flexible than a PLL as a clock generator. FIG. 1
illustrates a block diagram of a conventional zero-delay buffer
architecture.
[0005] Conventional method(s) have the disadvantages of
unpredictable input-output phase relationship and/or less
flexibility. However, many applications for clock synthesizers
benefit from a predictable input-output phase relationship, when
the output frequency is a multiple of the input frequency. The
present invention enjoys particular advantages in applications
where a predictable input-output phase relationship is desired,
particularly where the output frequency is an integral or one-half
integral multiple of the input frequency.
SUMMARY OF THE INVENTION
[0006] The present invention concerns a circuit comprising an
oscillator, a reference path, and a feedback path. The oscillator
may have a reference input receiving a reference signal, a feedback
input receiving a feedback signal, and an output. The reference
path may provide the reference signal from a reference clock input.
The feedback path may provide the feedback signal from the
oscillator loop output. At least one of the reference path and the
feedback path comprises a programmable delay circuit.
[0007] The objects, features and advantages of the present
invention include providing a clock synthesizer that may (i)
implement a programmable input-output phase relationship, (ii)
provide user programmable inputs for a programmable phase
relationship and/or (iii) implement a programmable phase
relationship in reference and/or feedback paths that may implement
an oscillator in a phase locked loop.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] These and other objects, features and advantages of the
present invention will be apparent from the following detailed
description and the appended claims and drawings in which:
[0009] FIG. 1 is a block diagram of a conventional buffer; and
[0010] FIG. 2 is a block diagram of a preferred embodiment of the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] The present invention concerns applications which use a
programmable (or other, similarly configurable PLL-based clock
generator, such as a serially configurable device) where the
input-output phase relationship is dependent on the values of the
internal counters and the multiplexers in the output path, which in
turn are dependent on the specific configuration of the device.
Program and/or configuration information may be stored in a
conventional nonvolatile or volatile memory, such as a read only
memory (ROM) , programmable read-only memory (PROM), erasable and
programmable read-only memory (EPROM), electrically erasable
programmable read-only memory (EEPROM), flash memory, random access
memory (RAM, which may be dynamic RAM or static RAM), nonvolatile
RAM, etc. The memory should be sufficiently large to store all the
desired frequency and configuration data (e.g., approximately 2K
bits, but could be more in particular design applications).
Configuration data may refer to programmed data bits, the values of
which result in control signals controlling one or more of the
following circuit parameters: voltage controlled oscillator (VCO)
gain, output buffer drive strength, delay lengths, phase comparator
boundaries, charge pump strength, counter reset values,
input/reference signal source, etc.
[0012] The present invention advantageously employs one or more of
the following new features:
[0013] (a) If the reference clock input is an electrical clock
signal, the input-output phase relationship can be made
user-programmable, through programmable memory, Serial Interface,
or hardware inputs, and thus the output clock can either lead or
lag behind the input clock. Ultimately, the user-programmable
input-output phase relationship provides a predictable input-output
delay.
[0014] (b) When the output clock is a multiple of the input clock,
or vice versa, and the multiplier is either an integral number (x1,
x3, x7, etc.) or one-half an integral number (21/2, 31/2, 61/2,
etc.), then the delay between the input and output clock rising
edges (when they are expected to be aligned) can be programmed to
be a predictable number, including zero. Additionally, other
relationships between the input clock and the output clock (e.g., 5
output clocks to 4 input clocks) may be implemented. This ensures
that when the input and output clocks have rising edges (e.g., in
the case of a rising edge-aligned PLL), there is predictable delay
between these rising edges. The same concept can also be applied to
falling edges (e.g., in the case of a PLL, which aligns falling
edges). This feature may be unique to PLL-based clock generators,
since they have counters in both the reference and feedback paths
(e.g., rising to falling edge aligned).
[0015] In a PLL-based clock generator, any of the following may be
sources of delay as a signal goes from input to output:
[0016] (a) Delay from input pin to input of reference counter,
T1
[0017] (b) Delay through the (optional) reference counter, T2
[0018] (c) Delay through the oscillator or PLL, T3
[0019] (d) Delay through the (optional) post-divider, T4
[0020] (e) Delay through the (optional) output multiplexer, T5
[0021] (f) Delay from output multiplexer to pin, T6
[0022] In order for the output signal to be in phase with the input
signal (where applicable), these delays should be eliminated
(noting that an output signal 360.degree. out of phase with the
input signal is effectively in phase, and thus, the delays
resulting in a 360.degree. out of phase output signal are
effectively eliminated). When the input-output phase relationship
needs to be predictable, one should compensate for the above delays
in a predictable manner for a particular configuration of a clock
generator.
[0023] The present invention therefore comprises (a) one or more
actual delay blocks, (b) a feedback path, and (c) control logic
which controls these delay blocks and feedback path, as indicated
in FIG. 2.
[0024] Delay generation in the present invention may be done
through conventional delay lines, or through RC circuits. Delay
compensation may be performed with either of at least two
techniques, described below.
[0025] (1) Feedback from the VCO:
[0026] One or more programmable delay blocks (e.g., DL1 and/or DL2
in FIG. 2) may be placed in one or more input paths to the PLL. For
example, one programmable delay circuit may be in a reference path
(e.g., between [i] a reference clock input and/or reference counter
and [ii] a phase and/or frequency detector in the PLL).
Alternatively and/or in addition, a programmable delay circuit may
be in a feedback path (e.g., from [i] the output of a VCO or VCO
output divider [identified as a "post divider" in FIG. 2] to [ii]
the phase and/or frequency detector in the PLL).
[0027] In the present invention, the programmable delay circuit may
be conventional, and may comprise a plurality of parallel gates,
switches or transistors, each receiving a common input from the
delay path, configured to select one of a plurality of signal
transmission paths coupled to the parallel gates, switches or
transistors. The programmable delay circuit may further comprise a
second plurality of parallel gates, switches or transistors,
coupling the outputs of the signal transmission paths to the delay
path.
[0028] Each of the signal transmission paths may independently have
a unique and/or characteristic signal transmission time, which may
be determined by one or more delay elements in the path. Delay
elements may include a resistor, a resistively-configured
transistor (e.g., having its gate coupled to a voltage supply such
as Vcc, Vss or ground, and having dimensions providing a
characteristic resistance), a diode-configured transistor (e.g.,
wherein the gate and one source/drain terminal are commonly coupled
to the input node), or a series of 2n inverters, where n is an
integer of 1 or more. Preferably, one of the signal transmission
paths does not contain a delay element. Examples of such circuits
may be found in U.S. Ser. Nos. 08/897,375 and 08/932,315, of which
the relevant portion(s) of each are incorporated herein by
reference.
[0029] The feedback delay block (e.g., DL2) may cause the feedback
input to the PFD (Phase/Frequency Detector) to lag behind a
reference input. Thus, the PLL may compensate for the resulting
phase difference by making the output of the VCO lead the reference
input. Hence, in this manner, programming a predetermined delay
value into the feedback delay block can eliminate one or more
delays (e.g., from T1-T6 above).
[0030] The reference delay block (e.g., DL1) may act as a
"fine-tuning knob," providing a secondary level of control over
output delay. In conjunction with the feedback delay block, the
programmable reference delay circuit forms the second half of a
"Differential Delay Control" (DDC) circuit and scheme. The
reference delay may (and preferably does) have the opposite effect
of the feedback delay in this embodiment. Therefore, if the time
increments of delay in the programmable feedback delay circuit are
not fine enough, the reference delay can be used to compensate for
the feedback delay. This may be implementation-dependent. In other
words, the feedback delay can be a coarse delay tuner, and the
reference delay can be a fine delay tuner, or vice-versa.
Additionally, if these delay blocks are configurable through serial
programming of configuration bits, then the user can dynamically
fine-tune the PLL for their particular application.
[0031] The reference delay may also provide fixed and/or
predictable input-output delay. In this case, the value programmed
into the reference delay will be greater than the value programmed
into the feedback delay by the amount of delay that the user wants
through the device. The value programmed into the feedback delay
should be dependent on the delays T1-T6 for which one wishes to
compensate.
[0032] (2) Feedback from beyond the multiplexer:
[0033] In this case, if the feedback path to the PLL originates
(directly or indirectly [e.g., after passing through one or more
logic gates]) from the output of a multiplexer receiving a
plurality of PLL outputs, then the feedback delay block may
automatically compensate for the delay through the post divider and
the multiplexer. In this case, the programmable delays in the
reference delay path and the feedback delay path may be programmed
to different values.
[0034] A logic block may be configured to control the delay blocks
and configure the feedback path (e.g., select its input or source).
The logic circuitry and configuration bits in the logic block can
be one-time programmable (e.g., using EPROM, ROM, fuses, or
metal-masks), or serially programmable through IC input pins or
programming hardware input pins. In the first case, the delay may
not controlled by the user unless one builds field programming
capability into the part. If the delay blocks and feedback path
source are controllable through serially downloadable data words,
then the user may have some adjustability and/or configurability in
fine-tuning a system (e.g., a circuit board) containing the present
clock circuit.
[0035] In either case, the user may estimate delays T1-T6, and
calculate the compensation provided by the reference delay, the
feedback delay, and the feedback path, using empirical formulae
determined in accordance with techniques and/or procedures known to
those skilled in the art.
[0036] One may alternatively implement the inventive concept (e.g.,
programmable delay blocks in feedback and/or reference input paths)
in a ring oscillator or delay-locked loop circuit.
[0037] One may omit the reference and feedback counters, although
they are preferably used for their conventionally-intended
purposes. Optionally, the order of the counter and the programmable
delay may be reversed (i.e., the programmable delay may receive the
feedback or reference path input and the counter may receive the
programmable delay output).
[0038] Configuration bits may be stored in flash memory, random
access memory (RAM, which may be static or dynamic), or a plurality
of registers. When the configuration bits are stored in flash
memory, EPROM or EEPROM, they may be reprogrammed while the clock
circuit is in place in the system or board.
[0039] The divider circuit may divide the oscillator or loop output
by any integer, including one, and may comprise a series of such
dividers. The divider circuit may further include a multiplier
circuit that may multiply the oscillator or loop output by any
integer, including one. The divider(s) and multiplier may be in any
series order and/or in parallel to permit selection of a single
such function or any combination thereof.
[0040] The present invention may provide an end user with control
over the input-output phase relationship of a clock device using
programmable delays in reference and/or feedback paths that are
easy to implement in conventional oscillator and locked-loop
circuits.
[0041] While the invention has been particularly shown and
described with reference to the preferred embodiments thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made without departing from the spirit
and scope of the invention.
* * * * *