U.S. patent application number 09/950132 was filed with the patent office on 2002-01-17 for compliant semiconductor chip package with fan-out leads and method of making same.
Invention is credited to Distefano, Thomas H..
Application Number | 20020006718 09/950132 |
Document ID | / |
Family ID | 27372360 |
Filed Date | 2002-01-17 |
United States Patent
Application |
20020006718 |
Kind Code |
A1 |
Distefano, Thomas H. |
January 17, 2002 |
Compliant semiconductor chip package with fan-out leads and method
of making same
Abstract
A semiconductor chip package, and a method of making such a
package, including a flexible dielectric element with a plurality
of electrically conductive terminals, an expander ring connected to
the flexible dielectric element, a semiconductor chip disposed with
a central opening in the expander ring, and fan-in and fan-out
leads connecting the terminals to contacts on the semiconductor
chip. The package also has an elastomer encapsulant disposed in the
gap between the expander ring and the semiconductor chip. The size
of the gap is controlled to minimize the pressure exerted on the
leads by the elastomer as it expands and contracts in response to
changes in temperature. The semiconductor chip and expander ring
may also be connected to a heat sink or thermal spreader with a
compliant adhesive.
Inventors: |
Distefano, Thomas H.; (Monte
Sereno, CA) |
Correspondence
Address: |
LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 SOUTH AVENUE WEST
WESTFIELD
NJ
07090
US
|
Family ID: |
27372360 |
Appl. No.: |
09/950132 |
Filed: |
September 10, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09950132 |
Sep 10, 2001 |
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09245224 |
Feb 5, 1999 |
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6309915 |
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60073843 |
Feb 5, 1998 |
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60084377 |
May 6, 1998 |
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Current U.S.
Class: |
438/617 ;
257/E23.055; 257/E23.069; 257/E23.124; 257/E23.135; 438/613 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 21/6835 20130101; H01L 23/49572
20130101; H01L 2924/19041 20130101; H01L 2924/351 20130101; H01L
24/01 20130101; H01L 2924/01322 20130101; H01L 23/3107 20130101;
H01L 23/3114 20130101; H01L 23/16 20130101; H01L 21/568 20130101;
H01L 2924/351 20130101; H01L 23/49816 20130101; H01L 2924/01322
20130101 |
Class at
Publication: |
438/617 ;
438/613 |
International
Class: |
H01L 021/44 |
Claims
1. A semiconductor chip assembly, comprising (a) an expander ring
having inner side walls defining an opening; (b) a semiconductor
chip having side surfaces defining the perimeter of the chip, said
chip being disposed within said opening of said expander ring so
that said side surfaces of said chip and said inner side walls of
said expander ring define a gap therebetween, said gap having a
width between said inner side walls and said side surfaces; (c) an
encapsulant disposed in the gap; and (d) leads extending from said
chip across said gap; whereinw.gtoreq.((CTE.sub.expander
ring-CTE.sub.chip)X.sub.c)/(CTE.sub.en- capsulant(1+2p);where w is
the width of the gap; CTE.sub.expander ring is the coefficient of
thermal expansion of the expander ring; CTE.sub.chip is the
coefficient of thermal expansion of the semiconductor chip; X, is
the shortest distance between a point on the outer perimeter of the
semiconductor chip and the center of the semiconductor chip;
CTE.sub.encapsulant is the coefficient of thermal expansion of the
encapsulant; and p is the Poisson ratio for the encapsulant.
2. The semiconductor chip assembly of claim 1 further comprising a
dielectric element and terminals on said dielectric element, said
dielectric element having a peripheral region, said expander ring
overlying said peripheral region of said dielectric element, at
least some of said terminals being disposed on the peripheral
region of said dielectric element and electrically connected to
said chip said leads extending across said gap.
3. The semiconductor chip assembly of claim 2 wherein said
dielectric element has a central region, said chip overlying said
central region of said dielectric element.
4. The semiconductor chip assembly of claim 3 wherein at least some
of said terminals are disposed on said central region of said
dielectric element, the assembly further comprising fan-in leads
electrically connecting said terminals on said central region and
said chip.
5. The semiconductor chip assembly of claim 4 wherein said fan-in
leads are interspersed with said leads extending across said
gap.
6. The semiconductor chip assembly of claim 3 further comprising a
compliant layer disposed between the semiconductor chip and the
central region of the dielectric element.
7. The semiconductor chip assembly of claim 6, wherein the
encapsulant is elastomeric and the dielectric element is
flexible.
8. The semiconductor chip assembly of claim 2 wherein said chip has
a face surface facing downwardly toward said dielectric element and
a back surface facing upwardly away from said dielectric element,
and said assembly further comprises a thermal spreader bonded to
the back surface of said semiconductor chip.
9. The semiconductor chip assembly of claim 8, further comprising
an adhesive disposed between said thermal spreader and the back
surface of said semiconductor chip.
10. The semiconductor chip assembly of claim 9, wherein said
adhesive is selected from the group consisting of silicone gels,
silicone elastomers, polyimide siloxanes, and flexiblized
epoxies.
11. The semiconductor chip assembly of claim 2, further comprising
means for electrically interconnecting the terminals to an external
substrate.
12. The semiconductor chip assembly of claim 2, wherein the
dielectric element has a top surface facing upwardly toward the
expander ring and chip and a bottom surface facing downwardly away
from said expander ring and chip, said terminals are disposed on
the top surface of the dielectric element, said dielectric element
having a plurality of vias extending through said dielectric
element so that said terminals are exposed for connection to an
external substrate through said vias.
13. The semiconductor chip assembly of claim 2, wherein the
dielectric element has a top surface facing upwardly toward the
expander ring and chip and a bottom surface facing downwardly away
from said expander ring and chip, said terminals are disposed on
the bottom surface of the dielectric element.
14. The semiconductor chip assembly of claim 1, wherein said
expander ring is comprised of a material selected from the group
consisting of alloy 42, copper, invar, steel, polypropylene,
epoxies, paper phenolics, and alloys and combinations thereof.
15. An electronic device comprising: (a) the semiconductor chip
assembly of claim 2; and (b) an external substrate electrically
interconnected to the terminals.
16. The electronic device of claim 14, wherein said electrically
interconnecting means include a plurality of solder balls and
wherein each of said solder balls is connected to one of the
terminals.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 09/245,224, filed on Feb. 5, 1999, entitled COMPLIANT
SEMICONDUCTOR CHIP PACKAGE WITH FAN-OUT LEADS AND METHODS OF MAKING
SAME, which application claims benefit of U.S. Provisional Patent
Application Ser. No. 60/073,843, filed Feb. 5, 1998; and U.S.
Provisional Patent Applications Ser. No. 60/084,377, filed on May
6, 1998 and entitled "Compliant Semiconductor Chip Package with
Fan-out Leads and Method of Making Same", the disclosures of which
are incorporated by reference herein.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to the art of electronic
packaging, and more specifically to assemblies incorporating
microelectronic components and methods of making such
assemblies.
[0003] In attempting to use the area on printed wiring boards more
efficiently, semiconductor chip manufacturers have switched some of
their production from larger more cumbersome interconnection
conventions, such as pin grid arrays and perimeter leaded quad flat
packs, to smaller conventions such as ball grid arrays ("BGA") and
chip scale packages ("CSP").
[0004] Using BGA technology, semiconductor chips are typically
interconnected to an external substrate, such as a printed circuit
board, using solder connections, such as with "flip-chip"
technology. However when solder alone is used to interconnect the
chip contact to the external substrate, the columns of solder are
generally designed to be short to maintain the solder's structural
integrity. This results in minimal elastic solder connections
properties which further results in increased susceptibility to
solder cracking due to mechanical stress caused by the differential
coefficient of thermal expansion ("CTE") of the chip relative to
the external substrate thereby reducing the reliability of the
solder connection. In other words, when the chip heats up during
use, both the chip and the external substrate expand; and when the
heat is removed, both the chip and the external substrate contract.
The problem that arises is that the chip and the external substrate
expand and contract at different rates and at different times,
thereby stressing the interconnections between them. As the
features of the semiconductor chips continue to be reduced in size,
the number of chips packed into a given area will be greater and
the heat dissipated by each of these chips will have a greater
effect on the thermal mismatch problem. This further increases the
need for a highly compliant scheme for interconnecting each chip to
the external substrate.
[0005] Such an interconnection scheme must also be capable of
accommodating a large number of interconnection between a single
semiconductor chip and an external substrate, such as a printed
circuit board. Complex microelectronic devices such as modem
semiconductor chips require numerous connections to other
electronic components. For example, a complex microprocessor chip
may require many hundreds of connections to an external
substrate.
[0006] Semiconductor chips commonly have been connected to
electrical traces on mounting substrates by one of three methods:
wire bonding, tape automated bonding and flip-chip bonding. In wire
bonding, the semiconductor chip is positioned on a substrate with
one surface of the chip abutting the substrate and the face or
contact bearing surface of the chip facing upward, away from the
substrate. Individual gold or aluminum wires are connected between
the contacts on the semiconductor chip and the current conducting
pads on the substrate. In tape automated bonding, a flexible
dielectric tape with a prefabricated array of leads thereon is
positioned over the semiconductor chip and substrate, and the
individual leads are bonded to the contacts and pads. In both wire
bonding and conventional tape automated bonding, the current
conducting pads on the substrate are arranged outside the area
covered by the semiconductor chip, so that the wires or leads
"fan-out" from the chip to the surrounding current conducting pads.
The area covered by the subassembly is considerably larger than the
area covered by chip. Because the speed with which a semiconductor
chip package can operate is inversely related to its size, this
presents a serious drawback. Moreover, the wire bonding and tape
automated bonding approaches are generally most workable with
semiconductor chips having contacts disposed in rows extending
along the periphery of the chip. They generally do not lend
themselves to the use of chips having contacts disposed in a
so-called area array, i.e., a grid-like pattern covering all or a
substantial portion of the chip face surface.
[0007] In the flip-chip mounting technique, the contact-bearing
surface of the semiconductor chip faces towards the substrate. Each
contact on the semiconductor chip is joined by a solder bond to the
corresponding current carrying pad on the substrate, as by
positioning solder balls on the substrate or contacts on the
semiconductor chip, juxtaposing the chip with the substrate in the
face-down orientation and momentarily melting or reflowing the
solder. The flip-chip technique yields a compact assembly, which
occupies an area of the substrate no larger than the area of the
chip itself. However, flip-chip assemblies suffer from significant
problems with thermal stress. The solder bonds between the contacts
on the semiconductor chip and the current carrying pads on the
substrate are substantially rigid. Changes in the size of the chip
and the substrate due to thermal expansion and contraction in
service create substantial stresses in these rigid bonds, which in
turn can lead to fatigue failure of the bonds. Moreover, it is
difficult to test the semiconductor chip before attaching it to the
substrate and hence difficult to maintain the required outgoing
quality level in the finished assembly, particularly where the
assembly includes numerous semiconductor chips.
[0008] Numerous attempts have been made to solve the foregoing
problems. Useful CSP solutions are disclosed in commonly assigned
U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390; 5,477,611;
5,518,964; 5,688,716; and 5,659,952, the disclosures of which are
incorporated herein by reference.
[0009] In preferred embodiments, the structures disclosed in U.S.
Pat. Nos. 5,148,265 and 5,148,266, incorporate flexible, sheet-like
structures referred to as "interposers" or "chip carriers". The
preferred chip carrier has a plurality of terminals disposed on a
flexible, sheet-like top layer. In use, the interposer is disposed
on the contact-bearing surface of the chip with the terminals
facing upwardly, away from the chip. The terminals are then
connected to the contacts on the chip. Most preferably, this
connection is made by bonding prefabricated leads on the interposer
to contacts on the chip, using a tool engaged with the leads. The
completed assembly is then connected to a substrate, as by bonding
the terminals of the chip carrier to the substrate. Because the
leads and the dielectric layer of the chip carrier are flexible,
the terminals on the chip carrier can move relative to the contacts
on the chip without imposing significant stresses on the bonds
between the leads and the contacts on the chip or on the bonds
between the terminals of the chip carrier and the substrate. Thus,
the assembly can compensate for thermal effects. Moreover, the
assembly most preferably includes a compliant layer disposed
between the terminals on the chip carrier and the face of the
semiconductor chip itself as, for example, an elastomeric layer
incorporated in the chip carrier and disposed between the
dielectric layer of the chip carrier and the semiconductor chip.
Such a compliant structure permits displacement of the individual
terminals independently towards the chip and also facilitates
movement of the terminals relative to the chip in directions
parallel to the chip surface. The compliant structure further
enhances the resistance of the assembly to thermal stresses during
use and facilitates engagement between the subassembly and a test
fixture during manufacturing. Thus, a test fixture incorporating
numerous electrical contacts can be engaged with all of the
terminals in the subassembly despite minor variations in the height
of the terminals. The substrate can be tested before it is bonded
to a substrate so as to provide a tested, known-good part to the
substrate assembly operation. This in turn provides very
substantial economic and quality advantages.
[0010] U.S. Pat. No. 5,455,930 describes a further improvement.
Components according to preferred embodiments of the '930 patent
use a flexible, dielectric top sheet. A plurality of terminals are
mounted on the top sheet. A support layer is disposed underneath
the top sheet, the support layer having a bottom surface remote
from the top sheet. A plurality of electrically conductive,
elongated leads are connected to the terminals on the tip sheet and
extend generally side by side downwardly from the terminals through
the support layer. Each lead has lower end at the bottom surface of
the support layer. The lower ends of the leads have conductive
bonding materials as, for example, eutectic bonding metals. The
support layer surrounds and supports the leads. Components of this
type can be connected to microelectronic elements, such as
semiconductor chips or wafers by "juxtaposing, the bottom surface
of the support layer with the contact-bearing surface of the chip
so as to bring the lower ends of the leads into engagement with the
contacts on the chip, and then subjecting the assembly to elevated
temperature and pressure conditions. All of the lower ends of the
leads bond to the contacts on the semiconductor chip substantially
simultaneously. The bonded leads connect the terminals on the top
sheet with the contacts on the chip. The support layer desirable is
either formed from a relatively low-modulus, compliant material, or
else is removed and replaced after the lead bonding step with such
a compliant material. In the finished assembly, the terminals on
the relatively flexible dielectric top sheet desirably are moveable
with respect to the contacts on the semiconductor chip to permit
testing of and to compensate for thermal effects. The component and
the methods of the '930 patent provide further advantages,
including the ability to make all of the bonds to the chip or other
component in a single lamination-like process step.
[0011] U.S. Pat. No. 5,518,964 discloses still further
improvements. Preferred methods according to the '964 patent,
include the step of providing a dielectric connection component
having a plurality of terminals and a plurality of leads. Each lead
has terminal-end attached to one of the terminals and a tip end (or
contact-end) attached to a contact on a chip. Preferred methods
also include the step of simultaneously forming all of the leads by
moving all of the tip ends of the leads relative to the
terminal-ends thereof and relative to the dielectric connection
component so as to bend the tip ends away from the dielectric
connection component. The dielectric connection component and the
chip desirably move in vertical and horizontal directions relative
to each other so as to deform the leads towards positions in which
the leads extend generally vertically downward, away from the
dielectric connection component. The method may also include the
step of injecting a flowable compliant dielectric material around
the leads. The terminals can be connected to an external substrate,
such as a printed circuit board, to thereby provide electrical
current communication to the contacts on the chip. Each terminal
structure is movable with respect to the contacts on the chip in
horizontal directions parallel to the chip, as well as in vertical
directions towards and away from the chip, to accommodate
differences in thermal expansion and contraction between the chip
and the external substrate and to facilitate testing and assembly.
The finished assembly can be mounted within an area of an external
substrate substantially the same as that required to mount a bare
chip.
[0012] U.S. Pat. No. 5,477,611 discloses a method of creating an
interface between a chip and chip carrier including spacing the
chip a give distance above the chip carrier and introducing a
liquid in the gap between the chip and the carrier. Preferably, the
liquid is an elastomer that is cured into a resilient layer after
its introduction into the gap. In another preferred embodiment, the
terminals on a chip carrier are planarized or otherwise vertically
positioned by deforming the terminals into set vertical locations
with a plate, and a liquid is then cured between the chip carrier
and the chip.
[0013] U.S. Pat. No. 5,688,716 discloses a method of making a
semiconductor chip assembly having fan-out leads. The method
includes the step of providing a semiconductor chip and a package
element attached to the chip. The peripheral region of the package
element projects beyond the outer edge of the chip. A dielectric
element having terminals on its top surface is positioned over the
chip and package element such that a central region of the
dielectric element overlies the chip and a peripheral region of the
dielectric having at least some of the terminals thereon overlies
the peripheral region of the package element, The assembly also has
leads that are attached to contacts on the chip and to the
terminals on the dielectric element. The method also comprises the
step of moving the dielectric element and chip relative to one
another such that the leads are bent into a flexible configuration.
The method also comprises the step of injecting a liquid beneath
the dielectric element and curing such liquid to form a compliant
layer.
[0014] U.S. Pat. No. 5,659,952 discloses a method of fabricating a
compliant interface for a semiconductor chip. The method includes
the steps of providing a first support structure, such as a
flexible dielectric sheet, having a porous resilient layer thereon.
The resilient layer may be a plurality of compliant pads or
compliant spacers. A second support element, such as a
semiconductor chip, is abutted against the resilient layer and a
curable liquid is disposed within the porous resilient layer. The
curable liquid may then be cured to form a compliant layer.
[0015] Despite the positive results of the aforementioned commonly
owned inventions, still further improvements would be
desirable.
SUMMARY OF THE INVENTION
[0016] The present invention relates to compliant semiconductor
chip packages and to methods of making such packages. The
semiconductor chip package according to one embodiment of the
present invention comprises a dielectric element with a plurality
of electrically conductive terminals, an expander ring connected to
the dielectric element, a semiconductor chip disposed within a
central opening in the expander ring, and fan-in and fan-out leads
connecting the terminals to contacts on the semiconductor chip.
Semiconductor chip packages having fan-in leads are disclosed in
commonly assigned U.S. Pat. No. 5,258,330, the disclosure of which
is incorporated herein by reference. Semiconductor chip packages
having fan-out leads and semiconductor chip packages having both
fan-in and fan-out leads are disclosed in commonly assigned U.S.
Pat. No. 5,679,977, the disclosure of which is incorporated herein
by reference. The package also comprises an encapsulant disposed in
the gap between the expander ring and the semiconductor chip. The
size of the gap is controlled to minimize the pressure exerted on
the leads by the encapsulant as it expands and contracts in
response to changes in temperature. The semiconductor chip and
expander ring may also be connected to a heat sink or thermal
spreader with a compliant adhesive.
[0017] The present invention also relates to a method of making a
semiconductor chip package. The method comprises the steps of
providing a dielectric element, disposing a compliant layer over
the dielectric element, disposing a semiconductor chip over the
compliant layer, disposing an expander ring over the compliant
layer such that a gap is formed between the inner diameter of a
central opening in the expander ring and the outer periphery of the
semiconductor chip, and electrically interconnecting terminals on
the dielectric element to contacts on the semiconductor chip. If
the package is to include a thermal spreader, such thermal spreader
can be attached to the semiconductor chip and/or the expander ring
with an adhesive. If the coefficient of thermal expansion
(hereinafter "CTE") of the thermal spreader and the CTE of the
semiconductor chip are not matched, then the adhesive should be a
compliant adhesive. In preferred embodiments, the thermal spreader
is attached before the contacts and the terminals are electrically
interconnected. In preferred embodiments, the semiconductor chip
package is encapsulated by injecting a liquid composition, which is
curable to an elastomeric encapsulant, into the open spaces between
the dielectric element, the semiconductor chip, the expander ring
and the optional thermal spreader, including the gap between the
outer periphery of the semiconductor chip and the inner diameter of
the central opening of the expander ring. The compliant adhesive,
the compliant layer and the encapsulant may be comprised of the
same or different materials. Prior to injecting the liquid
composition, it is desirable to seal the package by adhering a
coverlay to the bottom surface of the dielectric element. The
coverlay preferably has a plurality of holes which are dispose over
and aligned with the terminals on the dielectric element. If a
thermal spreader is used and the thermal spreader has relief slots,
it is also desirable to adhere a protective film over the thermal
spreader to seal such slots. A plurality of solder balls may be
attached to the terminals. The semiconductor chip package can be
connected to an external circuit via such solder balls.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a side view of one embodiment of the semiconductor
chip assembly of the present invention.
[0019] FIG. 2 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0020] FIG. 3 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0021] FIG. 4 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0022] FIG. 5 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0023] FIG. 6 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0024] FIG. 7 is a side view of another embodiment of the
semiconductor chip assembly of the present invention.
[0025] FIGS. 8A-8S show views of a plurality of semiconductor chip
packages in progressive steps in a manufacturing process according
to one embodiment of the method of the present invention. FIGS. 8A,
8B, 8C, 8E are top plan view of such packages in various steps in
such manufacturing process. FIG. 8D is a top plan view of a
component used in such manufacturing process. FIG. 8F is a bottom
plan view of another component used in such manufacturing process.
FIG. 8G is a top plan view of such packages after the component of
FIG. 8F has been adhered to such packages. FIG. 8H is a bottom plan
view of the packages in progress after the manufacturing step
described in FIG. 8G has been completed. FIG. 81 is an exploded
view of a portion of FIG. 8H. FIG. 8J is a bottom plan view of the
packages in progress after another manufacturing process step has
been completed. FIG. 8K is an exploded view of a portion of FIG.
8J. FIG. 8L is a bottom plan view of another component used in such
manufacturing process. FIG. 8M is a bottom plan view of the
packages in process after the component of FIG. 8L has been adhered
to such packages. FIG. 8N is a top plan view of another component
used in such manufacturing process. FIG. 80 is a top plan view of
the packages in process after the component of FIG. 8N has been
adhered to such packages. FIGS. 8P-8S are bottom plan view of such
packages in various steps in such manufacturing process.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] As depicted in FIG. 1, the semiconductor chip assembly I
according to one aspect of the present invention includes a
semiconductor chip 2, an expander ring 7 and a dielectric element
5. Semiconductor chip 2 has a face surface 15, a back surface 16
opposite the face surface, and four side surfaces 17 (two of which
are visible in FIG. 1) which connect the face surface to the back
surface. The four side surfaces form the outer perimeter of
semiconductor chip 2. Expander ring 7 has a first surface 20, a
second surface 21 opposite the first surface, and four inner side
walls 22 (two of which are visible in FIG. 1) which define a
central opening. Dielectric element 5 has a top surface 18, a
bottom surface 19 opposite top surface 18, and a plurality of
apertures 6. Top surface 18 is comprised of a central region, which
is disposed beneath the face surface 15 of semiconductor chip 2,
and a peripheral region that surrounds the central region.
Descriptors such as "top", "bottom", "beneath", etc, should be
understood to refer to the drawing in FIG. 1 and not to any
gravitational frame of reference. In preferred embodiments
dielectric element 5 is flexible. Expander ring 7 is disposed over
dielectric element 5 such that second surface 21 confronts the
peripheral region of the top surface 18 of dielectric element 5.
The CTE of the dielectric element is preferably from 15 to 22
ppm/.degree. C., inclusive. The CTE of the expander ring is
preferably from 5 to 30 ppm/.degree. C., inclusive. Semiconductor
chip 2 is disposed within the central opening of expander ring 7
such that a gap 8 is formed between the outer perimeter of
semiconductor chip 2 and the four inner side walls 22 of the
central opening of expander ring 7. A compliant layer 11 is
disposed between face surface 15 of semiconductor chip 2 and top
surface 18 of dielectric element 5. The CTE of the compliant layer
is preferably from 100 to 300 ppm/.degree. C., inclusive. An
adhesive 27 is disposed between the expander ring 7 and the
dielectric element 5. An encapsulant 3 is disposed within gap 8. In
preferred embodiments,
w.gtoreq.((CTE.sub.expander
ring-CTE.sub.chip)X.sub.c)/(CTE.sub.encapsulan- t(1+2p));
[0027] where w is the width of gap 8; CTE.sub.expander ring is the
coefficient of thermal expansion of the expander ring; CTE.sub.chip
is the coefficient of thermal expansion of the semiconductor chip;
X.sub.c is the shortest distance between the outer edge of the chip
and the center of the chip (See FIG. 1); CTE.sub.encapsulant is the
coefficient of thermal expansion of the encapsulant; and p is the
Poisson ratio for the encapsulant. In preferred embodiments, the
encapsulant is elastomeric, has a modulus of 0.5 to 600 MPa. and is
comprised of a silicone gel, a silicone elastomer, a filled
silicone elastomer, a urethane, an epoxy, or a flexiblized epoxy.
In particularly preferred embodiments, the elastomeric encapsulant
is comprised of a silicone elastomer.
[0028] A plurality of leads 4 interconnect contacts on the
semiconductor chip 2 to terminals on the dielectric element 5.
Leads 4 may be formed by any method, including the methods
disclosed in commonly assigned U.S. Pat. Nos. 5,390,844; 5,398,863;
5,489,749; 5,491,302; and 5,536,909, the disclosures of which are
incorporated herein by reference. Leads 4 may also be formed by
wire bonding. In preferred embodiments, the leads are comprised of
gold, copper or alloys thereof or combinations thereof.
[0029] The leads 4 are used to electrically interconnect terminals
on the dielectric element to contacts on the semiconductor chip or
to electrically interconnect the terminals to an external circuit.
The apertures 6 may be used to provide access for a bonding tool to
the leads so that such electrically interconnections can be made.
The apertures are optional and may be replaced with other means for
making such electrical interconnections. One such means is an
electrically conductive path disposed within such dielectric
element.
[0030] In another embodiment of the present invention, and as
depicted in FIG. 2, compliant layer 11 may include a plurality of
compliant spacers 11a. One or more such compliant spacers 11a may
also be disposed between second surface 21 of expander ring 7 and
the peripheral region of top surface 18 of dielectric element 5.
Compliant spacers 11a preferably have a modulus of 0.5 to 600 MPa.
In preferred embodiments, the compliant spacers 11a are comprised
of a silicone gel, a silicone elastomer or a flexiblized epoxy. In
particularly preferred embodiments, the compliant spacers are
comprised of a silicone elastomer.
[0031] In order to dissipate heat from the assembly, a thermal
spreader 10 may be connected to back surface 16 of semiconductor
chip 2 with a first adhesive 9, as depicted in FIG. 3. Thermal
spreader 10 may also be connected to the first surface 20 of
expander ring 7 with a second adhesive or ring adhesive 26. The
second adhesive may also be used to accommodate for differences and
tolerances between the semiconductor chip and the expander ring.
First adhesive 9 and second adhesive 26 may be comprised of the
same or different materials. In preferred embodiments, the first
and second adhesives have a modulus between 0.5 to 600 MPa. The
first and second adhesives are preferably comprised of a silicone
gel, a silicone elastomer, a polyimide siloxane, or a flexiblized
epoxy. The first and second adhesives may further comprise one or
more fillers. In preferred embodiments, at least one of such
fillers has a high thermal conductivity. Such highly thermally
conductive fillers may be metallic or non-metallic. In preferred
embodiments the second adhesive is comprised of a silicone
elastomer. For semiconductor chip packages that will be used in low
power applications, the preferred first adhesive is selected from
the group consisting of filled flexiblized epoxies and filled
silicone elastomers. Filled flexiblized epoxies are particularly
preferred. For semiconductor chip packages which will be used in
medium power applications, the preferred first adhesive is selected
from the group consisting of filled flexiblized epoxies, filled
polyimide siloxanes and filled silicone elastomers. For
semiconductor chip packages which will be used in high power
applications, the preferred first adhesive is an epoxy filled with
silver/glass, an epoxy filled with gold/geranium alloys, or an
epoxy filled with gold/silicon alloys.
[0032] In an alternative embodiment, and as depicted in FIG. 4, a
plurality of compliant spacers 11b may be disposed between thermal
spreader 10 and the first surface 20 of expander ring 7. In
preferred embodiments, the compliant spacers 11b are comprised of a
silicone gel, a silicone elastomer or a flexiblized epoxy. In
particularly preferred embodiments, the compliant spacers are
comprised of a silicone elastomer.
[0033] In preferred embodiments and as depicted in FIG. 5,
semiconductor chip 2 is connected to dielectric element 5 with a
compliant layer comprised of compliant spacers 11a. Expander ring 7
is connected to the peripheral region of the top surface 18 of
dielectric element 5 with a plurality of compliant spacers 11a and
to thermal spreader 10 with a plurality of compliant spacers 11b.
Compliant spacers 11a and 11b may have similar dimensions or, as
depicted in FIG. 5, different dimensions. Compliant spacers 11a and
11b may be comprised of the same or different materials.
[0034] As depicted in FIG. 6, terminals 23 on the dielectric
element 5 may be disposed on the top surface 18 of the dielectric
element 5. Leads 4 connect contacts (not shown) on semiconductor
chip 2 with terminals 23. A plated via 24 disposed in dielectric
element 5 is connected to each terminal 23. An electrically
conductive mass 13 is disposed within each via 24. In preferred
embodiments each electrically conductive mass 13 is a solder
ball.
[0035] As depicted in FIG. 7, the semiconductor chip assembly 1 of
the present invention may have both fan-in leads 4a and fan-out
leads 4b. Dielectric element 5 has apertures 6 which accommodate
both fan-in leads 4a and fan-out leads 4b. In preferred embodiments
the fan-in and fan-out leads are arranged interstitially such that
every other lead in a row of leads is a fan-in lead and the
remaining leads are fan-out leads. Assembly I also has a solder
mask or coverlay 14. Coverlay 14 is disposed over the bottom
surface 19 of dielectric element 5. Coverlay 14 has a plurality of
holes 25 which are aligned with terminals 23. Assembly I further
comprises a plurality of electrically conductive masses 13 which
are disposed in such holes 25. Masses 13 can be used to
electrically and physically connect the assembly to an external
circuit, such as a printed circuit board.
[0036] The dielectric element described with reference to the above
semiconductor chip packages and methods for making the same
preferably is a flexible dielectric element. In particularly
preferred embodiments, the dielectric element is a thin sheet of a
polymeric material such as a polylmide, a fluoropolymer, a
thermoplastic polymer, or an elastomer, with polyimide being a
particularly preferred material for use as the flexible dielectric
element. In preferred embodiments, the flexible dielectric element
is from 10 to 100 microns and more preferably from 25 to 75 microns
thick.
[0037] Each expander ring is used to support the solder balls which
are attached to the terminals of the fan-out leads and to add
structural stability to the package. The strip of expander rings
may be made of any material which will support the solder balls.
The expander rings may be made a conductive or a non-conductive
material. The expander rings may be made of a metal, a plastic, or
a paper based material. In preferred embodiments, the expander
rings are comprised of a material selected from alloy 42, copper,
invar, steel, polypropylene, epoxy or paper phenolic, or alloys
thereof, or combinations thereof. In particularly preferred
embodiments, the expander rings are comprised of a material
selected from copper, copper alloys, steel and combinations
thereof. The expander ring may be thicker or thinner than the
associated semiconductor chip. In preferred embodiments however,
the thickness of the expander ring is less than or equal to the
thickness of the semiconductor die. The CTE of the expander ring is
preferably intermediate between the CTE of the semiconductor chip
and the CTE of the dielectric element. If the package contains a
thermal spreader, the CTE of the thermal spreader is preferably
low, close to the CTE of the semiconductor chip, and the CTE of the
expander ring is preferably intermediate between the CTE of the
thermal spreader and the CTE of the dielectric element. In
preferred embodiments, the CTE of the thermal spreader is from 5 to
30 ppm/.degree. C., inclusive. One or more capacitors, transistors,
and/or resistors may be embedded in the expander ring and/or on the
dielectric element and electrically connected, via wire bonds,
solder or a conductive adhesive, to one or more terminals on the
dielectric element.
[0038] The thermal spreader is made from a material having a high
thermal conductivity. In preferred embodiments, the CTE of the
thermal spreader is close to the CTE of the semiconductor chip. For
semiconductor chip packages which will be used in low power
applications, the thermal spreader is preferably made from a
material selected from the group consisting of copper, copper
alloys, nickel plated copper alloys, aluminum, aluminum alloys,
anodized aluminum alloys, and steel. For semiconductor chip
packages which will be used in medium power applications, the
thermal spreader is preferably made from a material selected from
the group consisting of copper, copper alloys, alloy 42 and
multi-layered laminates containing copper coated invar. The
preferred multi-layer laminate is copper-invar-copper. For
semiconductor chip packages which will be used in high power
applications, the thermal spreader is preferably made of a material
selected from the group consisting of aluminum nitride and tungsten
copper.
[0039] The coverlay may be a temporary coverlay or a permanent
coverlay. The coverlay material must be capable of being bonded, at
least temporarily, to the dielectric element and of sealing any
apertures or holes in such element. The coverlay is preferably 1/2
mil to 10 Mils thick, more preferably 1/2 mil to 5 mils thick, most
preferably less than 2.5 mils thick. The coverlay material is
preferably comprised of polypropylene, polyester, polyimide or
combinations thereof, with polyimide being particularly preferred
for use as a permanent coverlay and polypropylene being
particularly preferred for applications using a temporary coverlay.
Materials which are commonly used as solder masks, such as solder
masks sold under Dupont's brand name Pyralux.RTM. may also be used
as a coverlay. Dupont's Pyralux.RTM. solder mask are generally
photoimageable, dry film solder masks which are based on acrylic,
urethane and -imide based, materials. The coverlay may also
comprise an adhesive layer. The adhesive layer is preferably
comprised of an acrylic, epoxy or silicone adhesive, with acrylic
adhesives being particularly preferred. Prior to the step in which
the coverlay is laminated to the dielectric element, the adhesive
layer must be tacky or must be in a form that is heat and/or
pressure activated. In preferred embodiments, the coverlay used in
the present invention is a permanent coverlay. The coverlay may
have a plurality of apertures. If the coverlay is comprised of a
photoimageable material, the apertures may be formed in the
coverlay after it is attached to the dielectric element.
[0040] The semiconductor chip package of the present invention can
be made according to the method of the present invention. FIGS.
8A-8S depict various steps in one method of the present invention.
As depicted in FIG. 8A, a dielectric element 101 is provided. In
preferred embodiments, dielectric element 101 is flexible.
Dielectric element 101 is in a strip form and has a top surface
102, a bottom surface (not shown) opposite top surface 102, and a
plurality of apertures 104. Apertures 104 are sometimes also
referred to as bond windows. The flexible dielectric element
described with reference to the above semiconductor chip packages
and methods for making the same is preferably a thin sheet of a
polymeric material such as a polylmide, a fluoropolymer, a
thermoplastic polymer, or an elastomer, with polyimide being a
particularly preferred material for use as the flexible dielectric
element. In preferred embodiments, the flexible dielectric element
is from 10 to 100 microns and more preferably from 25 to 75 microns
thick. Polylmide in strip form is generally supplied with a
plurality of sprocket holes 105. Although such sprocket holes may
be used as an alignment aid in the method of the present invention,
such sprocket holes are not required to practice the present
method.
[0041] Flexible dielectric element 101 has a plurality of
electrically conductive traces 106. Only a portion of each trace is
visible through the bond windows 104. Each trace 106 has a contact
end and a terminal-end. The contact-end will eventually be
connected to a contact on the face surface of semiconductor chip
108. Neither the tip nor the terminal-ends are visible in FIG. 8A.
Traces 106 may be disposed on either the top surface 102 or the
bottom surface 103 of the flexible dielectric element 101. In the
embodiment pictured in FIGS. 8A-8S, traces 106 are disposed on the
bottom surface 103 (See FIG. 8H).
[0042] As depicted in FIG. 8B, a plurality of compliant spacers 107
are disposed on the top surface 102 of flexible dielectric element
101. Some methods of disposing such compliant spacers or resilient
elements are described in commonly assigned U.S. Pat. No. 5,659,952
and U.S. patent application with Ser. No. 08/879,922 and a filing
date of Jun. 20, 1997, the disclosures of which are incorporated
herein by reference. In preferred embodiments, the compliant
spacers 107 are comprised of a silicone gel, a silicone elastomer
or a flexiblized epoxy. The compliant spacers preferably have a
modulus of 0.5 to 600 MPa. In particularly preferred embodiments,
the compliant spacers are comprised of a silicone elastomer. Prior
to die attach some or all of the compliant spacers 107 may be in an
uncured, partially cured or fully cured state. An adhesive may be
disposed on the top surface of such spacers 107. Commonly assigned
U.S. patent application with Ser. No. 08/931,680 and a filing date
of Sep. 16, 1997, the disclosure of which is incorporated herein by
reference, teaches one method of disposing an adhesive over a
Compliant spacer or compliant pad.
[0043] As depicted in FIG. 8C, a plurality of semiconductor chips
108 are then disposed over the top surface 102 of flexible
dielectric element 101. Each chip 108 has a face surface (not
shown), a back surface 111 opposite the face surface, and a
plurality of electrically conductive contacts (not shown) disposed
on the face surface 110. Each chip 108 is positioned over one set
of bond windows 104 and the face surface of each is adhered to
flexible dielectric element 101. If compliant spacers 107 are in an
uncured state, a partially cured state, or have an adhesive
disposed on the top surfaces of such spacers, chips 108 may be
adhered to flexible dielectric element 101 using such spacers 107.
Heat and pressure may be required to achieve a good bond between
spacers 107 and chips 108.
[0044] As depicted in FIG. 8D, a strip of expander rings 109 is
provided. Each expander ring 109 has a first surface 112, a second
surface (not shown) opposite first surface 112, and four inner side
walls 113 which define a central opening 114. Each expander ring is
used to support the solder balls which are attached to the
terminals of the fan-out leads and to add structural stability to
the package. Various methods of packaging semiconductor chips using
expander rings are described in co-pending, commonly assigned U.S.
patent application Ser. No. 09/067,310, having a filing date of
Apr. 28, 1998, the disclosure of which is hereby incorporated
herein by reference. The expander rings of the '310 application are
referred to as unitary support structures.
[0045] The strip of expander rings 109 may be made of any material
which will support the solder balls. The expander rings may be made
of a conductive or a non-conductive material. The expander rings
may be made of a metal, a plastic, or a paper based material. In
preferred embodiments, the expander rings are comprised of a
material selected from alloy 42, copper, invar, steel,
polypropylene, epoxy or paper phenolic, or alloys thereof, or
combinations thereof. In particularly preferred embodiments, the
expander rings are comprised of a material selected from copper,
copper alloys, steel and combinations thereof. The expander ling
may be thicker or thinner than the associated semiconductor chip.
In preferred embodiments however, the thickness of the expander
ring is less than or equal to the thickness of the semiconductor
die. The CTE of the expander ring is preferably intermediate
between the CTE of the semiconductor chip and the CTE of the
flexible dielectric element. If the package contains a thermal
spreader, the CTE of the thermal spreader is preferably low, close
to the CTE of the semiconductor chip, and the CTE of the expander
ring is preferably intermediate between the CTE of the thermal
spreader and the CTE of the flexible dielectric element. One or
more capacitors, resistors, and/or transistors, may be embedded in
the expander ring and electrically connected, via wire bonds,
solder or a conductive adhesive, to one or more terminals on the
flexible dielectric element.
[0046] As depicted in FIG. 8E, the strip of expander rings 109 is
disposed over the flexible dielectric element 101 such that a) the
second surface of each expander ring 109 confronts the top surface
102 of the flexible dielectric element 101; b) the central opening
114 of each expander ring 109 is disposed around one of the
semiconductor chips 108; and c) for each semiconductor chip 108, a
gap 115 is maintained between each inner side wall 113 and the
outer perimeter of the semiconductor chip 108. In preferred
embodiments,
w>((CTE.sub.expander
ring-CTE.sub.chip)X.sub.c)/(CTE.sub.encapsulant(1+- 2p);
[0047] where w is the width of gap 115; CTE.sub.expander ring is
the coefficient of thermal expansion of the expander ring;
CTE.sub.chip is the coefficient of thermal expansion of the
semiconductor chip; X.sub.c is the shortest distance between the
outer edge of the chip and the center of the chip;
CTE.sub.encapsulant is the coefficient of thermal expansion of the
encapsulant; and p is the Poisson ratio for the encapsulant which
will be disposed within the gap. With some chips, such as, for
example rectangular chips, X.sub.c is not constant for all points
on the outer edge of the chip. For such chips, w can be calculated
for each point on the outer edge of the chip. The gap between the
chip and the expander ring, as measured at each such point on the
outer edge of the chip should be at least the value of w calculated
for that point. In preferred embodiment however, the width of the
gap is constant and is selected to be at least as wide as the
highest value of w calculated for the chip.
[0048] In preferred embodiments, the encapsulant is elastomeric. In
more preferred embodiments, the elastomeric encapsulant has a
modulus of 0.5 to 600 MPa. and is comprised of a silicone gel, a
silicone elastomer, a filled silicone elastomer, a urethane, an
epoxy, or a flexiblized epoxy. In particularly preferred
embodiments, the elastomeric encapsulant is comprised of a silicone
elastomer.
[0049] The strip of expander rings 109 may have one or more
fidicuals to aid in the proper alignment of the expander rings on
the flexible dielectric element. The sprocket holes 105 may also be
used to aid in the alignment of the expander rings. The second
surface of each of the expander rings 109 is adhered to the
compliant spacers 107, preferably using heat and/or pressure. In
preferred embodiments, the first surface 112 of each expander ring
109 is coplanar with the back surface 111 of each semiconductor
chip 108. The second surface of the expander ring may be coplanar
with the face surface of each semiconductor chip 108. Such heat and
pressure can also be used to correct for any lack of coplanarity
between each expander ring 109 and the associated semiconductor
chip 108.
[0050] As depicted in FIG. 8F, a strip of thermal spreaders 116 is
provided. The strip of thermal spreaders 116 has an alpha surface
(not shown) and a beta surface 117 opposite the alpha surface. The
thermal spreader is made from a material having a high thermal
conductivity. In preferred embodiments, the CTE of the thermal
spreader is close to the CTE of the semiconductor chip. For
semiconductor chip packages which will be used in low power
applications, the thermal spreader is preferably made from a
material selected from the group consisting of copper, copper
alloys, nickel plated copper alloys, aluminum, aluminum alloys,
anodized aluminum alloys, and steel. For semiconductor chip
packages which will be used in medium power applications, the
thermal spreader is preferably made from a material selected from
the group consisting of copper, copper alloys, alloy 42 and
multi-layered laminates containing copper coated invar. The
preferred multi-layer laminate is copper-invar-copper. For
semiconductor chip packages which will be used in high power
applications, the thermal spreader is preferably made of a material
selected from the group consisting of aluminum nitride and tungsten
copper.
[0051] The strip of thermal spreaders 116 may have a plurality of
elongated slots 119. Such slots 119 are incorporated in the strip
of thermal spreaders 116 to ease the singulation process in which
the strip of packaged semiconductor chips are cut into individual
packages. The strip of thermal spreaders 116 may have one or more
fiducials to aid in the alignment of the thermal spreaders. The
strip of thermal spreaders may be aligned with sprocket holes 105
in flexible dielectric element 101 to aid in the positioning of the
thermal spreaders. A first adhesive 118 is disposed on the beta
surface 117. Such adhesive may take for example, the form of a pad,
a film or a dispensed pattern such as a plurality of dots of
adhesive. Adhesive 118 will eventually be used to bond beta surface
117 to the back surfaces of each of semiconductor chips 108. A
second adhesive or ring adhesive 118' may also be disposed on beta
surface 117 and be in the form of a pad, a film or a plurality of
dots. Second adhesive 118 may be used to accommodate for
differences and tolerances between the semiconductor chip and the
expander ring. The dots of adhesive 118' will eventually be used to
bond beta surface 117 to first surface 112 of each expander ring
109. If the CTE of the strip of thermal spreaders 116 and the CTE
of the semiconductor chips is not matched, then adhesive 118 should
be compliant. In preferred embodiments, both adhesives 118 and 118'
are compliant. Adhesives 118 and 118' may be comprised of the same
or different materials. In preferred embodiments, the first and
second adhesives are comprised of a silicone gel, a silicone
elastomer, a polyimide siloxane, or a flexiblized epoxy. The first
and second adhesive may further comprises one or more fillers. In
preferred embodiments, at least one of such fillers has a high
thermal conductivity. Such highly thermally conductive fillers may
be metallic or non-metallic. In preferred embodiments, the first
and second adhesives have a modulus between 0.5 to 600 MPa. and are
comprised of a silicone gel, a silicone elastomer, a polyimide
siloxane, or a flexiblized epoxy. In particularly preferred
embodiments the second adhesive is comprised of a silicone
elastomer. For semiconductor chip packages which will be used in
low power applications, the preferred first adhesive is selected
from the group consisting of filled flexiblized epoxies and filled
silicone elastomers. Filled flexiblized epoxies are particularly
preferred. For semiconductor chip packages which will be used in
medium power applications, the preferred first adhesive is selected
from the group consisting of filled flexiblized epoxies, filled
polyimide siloxanes and filled silicone elastomers. For
semiconductor chip packages which will be used in high power
applications, the preferred first adhesive is an epoxy filled with
silver/glass, an epoxy filled with gold/geranium alloys, or an
epoxy filled with gold/silicon alloys. The dimensions of the dots
of adhesives 118 and 118' may be the same or different.
[0052] The strip of thermal spreaders 116 is disposed over
semiconductor chips 108 and expander rings 109 such that the beta
surface 117 of the strip of thermal spreaders 116 confronts the
back surfaces 111 of semiconductor chips 108 and the first surfaces
112 of each expander ring 109. The strip of thermal spreaders 116
is adhered to such back surfaces and first surfaces with the
adhesives 118 and 118'. Once this is complete, the alpha surface
120 of the strip of expander rings 109 is visible from a top plan
view, as depicted in FIG. 8G.
[0053] FIG. 8H is a view of the bottom surface 103 of the flexible
dielectric element 101 prior to the processing step in which the
leads are formed. A portion of the face surface 110 of each chip
108 is visible in FIG. 8H through bond windows 104. FIG. 8H also
depicts a plurality of electrically conductive traces 121 disposed
on the bottom surface 103 of flexible dielectric element 101. FIG.
81 is an exploded view of a portion of FIG. 8H, depicting more
details of traces 121. Each trace 121 has a terminal 122 and a
contact-end 123. Some of the traces 121 have a terminal 122 that is
disposed on a portion of flexible dielectric element 101 which lies
underneath the face surface 110 of semiconductor chip 108. The
directional descriptor "underneath," as used to describe FIG. 8H
(which is a bottom plan view), should be read to mean "below when
viewed from a top plan view" and not with reference to any
gravitational frame of reference. Some traces will eventually be
formed into "fan-in" leads. Some of the traces (such as trace 12F)
have a terminal 122' that is disposed on a portion of the flexible
dielectric element which lies underneath the second surface of
expander ring 109. Such traces 121' will eventually be formed into
"fan-out" leads. The package depicted in FIG. 81 has a total of 26
traces. In preferred embodiments, the package will have 40 or more
leads, more preferably 40 to 1000 leads. In preferred embodiments,
terminals 122 and 122' are disposed in ordered rows or an area
array having a consistent pitch. In preferred embodiments, the
fan-in and fan-out leads are comprised of gold, copper or alloys
thereof or combinations thereof.
[0054] FIG. 8J depicts the flexible dielectric element 101 and the
plurality of chips 108 after the fan-in and fan-out leads have been
formed. FIG. 8K is an exploded view of a portion of FIG. 8J. As
depicted in FIG. 8K, the contact-end 123 of each trace 121 is
bonded to an electrically conductive contact on the face surface
110 of semiconductor chip 108 to form a fan-in lead 124 which
electrically interconnects the chip 108 to the flexible dielectric
element 101. The contact-end 123' of each trace 121' is bonded to
an electrically conductive contact on the face surface 110 of
semiconductor chip 108 to form a fan-out lead 124'. The fan-in and
fan-out leads may be formed by any method, including the methods
disclosed in commonly assigned U.S. Pat. Nos. 5,390,844; 5,398,863;
5,489,749; 5,491,302; and 5,536,909, the disclosures of which are
incorporated herein by reference. In an alternative embodiment, the
fan-in and fan-out leads may be formed by wire bonding each contact
to the respective terminal.
[0055] Next, the bond windows 104 and any other apertures or holes
in flexible dielectric element 101 are sealed using a coverlay,
such as coverlay 125 which is depicted in FIG. 8L.
[0056] The coverlay may be a temporary coverlay or a permanent
coverlay. The coverlay material must be capable of being bonded, at
least temporarily, to the flexible dielectric element and of
sealing any apertures or holes in such element. The coverlay is
preferably 1/2 mil to 10 mils thick, more preferably 1/2 mil to 5
mils thick, most preferably less than 2.5 mils thick. The coverlay
material is preferably comprised of polypropylene, polyester,
polyimide or combinations thereof, with polyimide being
particularly preferred for use as a permanent coverlay and
polypropylene being particularly preferred for applications using a
temporary coverlay. Materials which are commonly used as solder
masks, such as solder masks sold under Dupont's brand name
Pyralux.RTM. may also be used as a coverlay. Dupont's Pyralux.RTM.
solder masks are generally photoimageable, dry film solder mask
which are based on acrylic, urethane and -imide based materials.
The coverlay may also comprise an adhesive layer. The adhesive
layer is preferably comprised of an acrylic, epoxy or silicone
adhesive, with acrylic adhesives being particularly preferred.
Prior to the step in which the coverlay is laminated to the
flexible dielectric element, the adhesive layer must be tacky or
must be in an activatable form, such as a heat and/or pressure
activated from. In preferred embodiments, the coverlay used in the
present invention is a permanent coverlay. The coverlay may have a
plurality of apertures. If the coverlay is comprised of a
photoimageable material, the apertures may be formed in the
coverlay after it is attached to the flexible dielectric
element.
[0057] The coverlay depicted in FIG. 8L is photoimageable and has
been exposed in a pattern corresponding to the pattern of terminals
on the flexible dielectric element. As depicted in FIG. 8M,
coverlay 125 is laminated to the bottom surface 103 of flexible
dielectric element 101. The coverlay may be vacuum laminated,
pressure laminated, vacuum-pressure laminated or otherwise
laminated onto the bottom surface 103 of the flexible dielectric
element 101. FIG. 8M depicts the bottom surface 103 after a
transparent coverlay 125 has been laminated to it.
[0058] A protective film 127 is provided, as depicted in FIG. 8N.
The protective film of the present invention can be any of the
materials listed above for the coverlay. In preferred embodiments,
however, the protective film used in the present invention is a
temporary coverlay which is removed after use. The protective film
may be removed by, for example, using heat, peeling the film from
the strip of thermal spreaders, or immersing the protective film in
a caustic solution. Protective film 127 is used to seal the
elongated slots and any other apertures in thermal spreader 116
while a liquid composition is injected into the assembly to
encapsulated it. Protective film 127 should be capable of being,
bonded to the alpha surface of thermal spreader 116. Since
protective film 127 may be removed after the encapsulation process,
in preferred embodiments, protective film 127 forms only a
temporary bond to the alpha surface of the strip of thermal
spreaders 116. As depicted in FIG. 80, film 127 is adhered to the
thermal spreader 116 to seal the elongated slots 119.
[0059] After coverlay 125 has been laminated to flexible dielectric
element 101 and after protective film 127 has been adhered to the
alpha surface of the strip of thermal spreaders 116, the assembly
can be encapsulated using a liquid composition which is curable to
an encapsulant. In preferred embodiments the encapsulant is
elastomeric. The elastomeric encapsulant increases the reliability
of the assembly by compensating for the mismatch in CTE between the
semiconductor chip package and an external circuit. The liquid
composition is disposed between the top surface 102 of the flexible
dielectric element 101 and the thermal spreader 116. The liquid
composition fills the open spaces between any of the expander ring,
the thermal spreader, the semiconductor chip, the flexible
dielectric element, the compliant adhesive, and the compliant
spacers. The liquid composition also fills in gap 115 (see FIG. 8E)
between the expander ring 109 and the semiconductor chip 108. The
assembly may be encapsulated with the liquid composition via a
dispensing operation, a dispensing operation followed by subjecting
the assembly to vacuum and or pressure, a dispensing operation
preformed while the assembly is under vacuum, or by a pressurized
injection operation. Various methods of encapsulating the assembly
are disclosed, for example, in commonly assigned U.S. patent
application Ser. No. 09/067,698 filed on Apr. 28, 1998.
[0060] FIG. 8P depicts the assembly of the present invention after
the strip has been vacuum impregnated with liquid composition 126.
Terminals 122 and 122' and a portion of each lead 124 and 124' are
visible in FIG. 8P. The coverlay 125 seals against the bottom
surface 103 of the flexible dielectric element 101 to prevent the
liquid encapsulant 126 from contaminating terminals 122 and 122'.
After being impregnated into the assembly, liquid composition 126
is cured or at, least partially cured. Protective film 127 may then
removed from thermal spreader 116. Holes are formed in coverlay 125
by exposing the photoimageable coverlay to a developer, such as
potassium carbonate. The holes are formed in a pattern
corresponding to the pattern of terminals 122 and 122' on flexible
dielectric element 101. Flux is then applied on the terminals and,
as depicted in FIG. 8Q, solder balls 128 are disposed within the
holes in coverlay 125. The solder balls are reflowed. The plurality
of semiconductor chips 108 are then singulated as depicted in FIG.
8R and FIG. 8S to form a plurality of packaged semiconductor chip
assemblies 129.
[0061] The method described with reference to FIGS. 8A 8S employs
various process steps which are conducted on components in strip
format. The method of the present invention may also be practiced
with components that are supplied in a reel to reel format.
* * * * *