U.S. patent application number 08/928770 was filed with the patent office on 2002-01-10 for semiconductor device and method for fabricating the same.
Invention is credited to ANEZAKI, TOHRU, EMA, TAIJI, MITANI, JUNICHI.
Application Number | 20020003248 08/928770 |
Document ID | / |
Family ID | 46276180 |
Filed Date | 2002-01-10 |
United States Patent
Application |
20020003248 |
Kind Code |
A1 |
EMA, TAIJI ; et al. |
January 10, 2002 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Abstract
The semiconductor device comprises a MOSFET including a pair of
impurity diffused regions formed on both sides of a gate formed on
a semiconductor substrate; an insulation film covering a top of the
MOSFET and having a through-hole opened on one of the impurity
diffused regions formed in; and a capacitor formed at at least a
part of an inside of the through-hole, the through-hole having a
larger diameter inside than at a surface thereof or having a larger
diameter at an intermediate part between the surface thereof and a
bottom thereof than the surface and the bottom thereof.
Inventors: |
EMA, TAIJI; (KAWASAKI-SHI,
JP) ; ANEZAKI, TOHRU; (KAWASAKI-SHI, JP) ;
MITANI, JUNICHI; (KAWASAKI-SHI, JP) |
Correspondence
Address: |
ARMSTRONG,WESTERMAN, HATTORI,
MCLELAND & NAUGHTON, LLP
1725 K STREET, NW, SUITE 1000
WASHINGTON
DC
20006
US
|
Family ID: |
46276180 |
Appl. No.: |
08/928770 |
Filed: |
September 12, 1997 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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08928770 |
Sep 12, 1997 |
|
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|
08592481 |
Jan 26, 1996 |
|
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|
5874756 |
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Current U.S.
Class: |
257/301 ;
257/E21.648; 257/E21.654; 438/243; 438/386 |
Current CPC
Class: |
H01L 27/10873 20130101;
H01L 27/10852 20130101 |
Class at
Publication: |
257/301 ;
438/243; 438/386 |
International
Class: |
H01L 029/76; H01L
021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 31, 1995 |
JP |
7-13748 |
Nov 29, 1995 |
JP |
7-310737 |
Sep 13, 1996 |
JP |
8-243687 |
Claims
What is claimed is:
1. A semiconductor device comprising: a MOSFET including a pair of
impurity diffused regions formed on both sides of a gate formed on
a semiconductor substrate: an insulation film covering a top of the
MOSFET, a through-hole opened on one of the impurity diffused
regions being formed in the insulation film; and a capacitor formed
at at least a part of an inside of the through-hole, the
through-hole having a larger diameter inside than at a surface
thereof.
2. A semiconductor device comprising: a MOSFET including a pair of
impurity diffused regions formed on both sides of a gate formed on
a semiconductor substrate: an insulation film covering a top of the
MOSFET, a through-hole opened on, one of the impurity diffused
regions being formed in the insulation film; and a capacitor formed
at at least a part of an inside of the through-hole, the
through-hole having a larger diameter at an intermediate part
thereof between a surface thereof and a bottom thereof than at the
surface and the bottom thereof.
3. A method for fabricating a semiconductor device comprising: a
MOSFET forming step of forming on a semiconductor substrate a
MOSFET including a gate and a pair of impurity diffused regions on
both sides of the gate; an insulation film forming step of forming
an insulation film for covering the MOSFET; a through-hole forming
step of forming in the insulation film a through-hole having a
larger diameter inside than at a surface thereof, the through-hole
being opened on one of the impurity diffused regions; and a
capacitor forming step of forming a capacitor at at least a part of
an inside of the through-hole.
4. A method for fabricating a semiconductor device comprising: a
MOSFET forming step of forming on a semiconductor substrate a
MOSFET including a gate and a pair of impurity diffused regions on
both sides of the gate; an insulation film forming step of forming
an insulation film for covering the MOSFET; a through-hole forming
step of forming in the insulation film a through-hole having a
larger diameter at an intermediate part between a surface thereof
and a bottom thereof than the surface and the bottom thereof, the
through-hole being opened on one of the impurity diffused regions;
and a capacitor forming step of forming a capacitor at at least a
part of an inside of the through-hole.
5. A method for fabricating a semiconductor device comprising: a
MOSFET forming step of forming an a semiconductor substrate a
MOSFET including a gate and a pair of impurity diffused regions on
both sides of the gate; an insulation film forming step of forming
a plurality of insulation films being laminated for covering the
MOSFET; a through-hole forming step of forming in the insulation
films a through-hole having a larger diameter inside than at a
surface thereof, the through-hole being opened on one of the
impurity diffused regions; and a capacitor forming step of forming
a capacitor at at least a part of an inside of the
through-hole.
6. A method for fabricating a semiconductor device according to
claim 5, wherein the insulation film forming step includes a step
of forming a first insulation film, and a step of forming on the
first insulation film a second insulation film having etching
characteristics different from those of the first insulation film;
and the through-hole forming step includes a step of forming in the
first insulation film and the second insulation film the
through-hole having substantially the same opening diameter, and a
step of retreating the first insulation film inside the
through-hole by the use of an etchant having a higher etching rate
with respect to the first insulation film than with respect to the
second insulation film.
7. A method for fabricating a semiconductor device comprising: a
MOSFET forming step of forming on a semiconductor substrate a
MOSFET including a gate and a pair of impurity diffused regions on
both sides of the gate; an insulation film forming step of forming
a plurality of insulation films being laminated for covering the
MOSFET; a through-hole forming step of forming in the insulation
films a through-hole having a larger diameter at an intermediate
part between a surface thereof and a bottom thereof than the
surface and the bottom thereof, the through-hole being opened on
one of the impurity diffused regions; and a capacitor forming step
of forming a capacitor at at least a part of an inside of the
through-hole.
8. A method for fabricating a semiconductor device according to
claim 7, wherein the insulation film forming step includes a step
of forming a first insulation film, a step of forming on the first
insulation film a second insulation film having etching
characteristics different from those of the first insulation film,
and a step of forming on the second insulation film a third
insulation film having etching characteristics different from those
of the second insulation film; and the through-hole forming step
includes a step of forming in the first insulation film, the second
insulation film and the third insulation film the through-hole
having substantially the same opening diameter, and a step of
retreating the second insulation film inside the through-holes by
the use of an etchant having a higher etching rate with respect to
the second insulation film than with respect to the first and the
third insulation film.
9. A method for fabricating a semiconductor device according to
claim 7 wherein the insulation film forming step includes a step of
forming a first insulation film, a step of forming on the first
insulation film a second insulation film having etching
characteristics different from those of the first insulation film,
and a step of forming on the second insulation film a third
insulation film having etching characteristics different from those
of the second insulation film; and the through-hole forming step
includes a step of etching the second and the third insulation
films by the use of an etchant which has a higher etching rate with
respect to the second insulation film than with respect to the
third insulation film and substantially anisotropically contains an
isotropic component, and a step of isotropically etching the first
insulation film by the use of an etchant having a higher etching
rate with respect to the first insulation film than with respect to
the second insulation film.
10. A method for fabricating a semiconductor device according to
claim 9, wherein the etchant for etching the first insulation film
has a higher etching rate with respect to the second insulation
film than with respect to the third insulation film.
11. A method for fabricating a semiconductor device according to
claim 8, wherein the first insulation film is a silicon nitride
film; the second insulation film is a silicon oxide film containing
boron and/or phosphorus: the third insulation film is a non-doped
silicon oxide film.
12. A method for fabricating a semiconductor device according to
claim 9, wherein the first insulation film is a silicon nitride
film; the second insulation film is a silicon oxide film containing
boron and/or phosphorus: the third insulation film is a non-doped
silicon oxide film.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of Ser. No.
08/592,481, filed on Jan. 26, 1996.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor device and
a method for fabricating the same, more specifically to a
high-integration DRAM and a method for fabricating the same.
[0003] The present invention can realize a large capacitor and a
micronized memory while securing an alignment allowance in a
lithography step and electric isolation.
[0004] With reference to FIGS. 3A and 3B, a conventional
semiconductor device and a method for fabricating the same will be
explained.
[0005] A field oxide film 2 for defining a device region is formed
on a semiconductor substrate 1. A gate 4 of memory cell transistor
is formed through a gate oxide film 3 in the device region defined
by the field oxide film 2. A part of the gate 4 is extended on the
field oxide film 2. An insulation film 5 is formed on the side
walls and the upper surface of the gate 4. A silicon nitride
(Si.sub.3N.sub.4) film 6 which function as an etching stopper and
an inter-layer insulation film 12 are formed on the semiconductor
substrate 1 having memory cell transistor. A through-hole is formed
through these films down to the semiconductor substrate 1. A
storage electrode 9 of a capacitor connected to the semiconductor
substrate 1 is formed on the inside wall and the bottom of the
through-hole. An opposed electrode 11 of the capacitor is formed
through a dielectric film 10 on the surface of the storage
electrode 9.
[0006] In the exemplified conventional semiconductor device, the
side wall of the through-hole for the capacitor contact is vertical
or tapered. In such capacitor, in a case that the through-hole has
a large diameter for a larger capacitance, the opening is subjected
to restrictions for an alignment allowance for a bit line contact
and for electric isolation.
[0007] In a case that a hole diameter and a disalignment are large,
as shown in FIG. 3A, the field oxide film 2 is adversely dug even
though the contact is formed in self-alignment with the gate 4 to
resultantly form a projection in the capacitors with a resultant
problem that an electric field tends to be concentrated to cause
dielectric breakdown of the dielectric film 10. Increase of a hole
diameter is restricted.
[0008] In a case that, as shown in FIG. 3B, the contact is formed
only by an optical alignment, a hole diameter must be smaller
because the storage electrode of the capacitor tends to
short-circuit with the gate electrode.
[0009] Accordingly, in a case that the capacitor has such
configuration, it is restricted to simply increase a hole diameter
for a larger capacitance. As means for effectively omitting such
restriction to the opening, the bit line contact is formed before,
and then the capacitor is formed. A problem with this means is
fabrication step increase.
SUMMARY OF THE INVENTION
[0010] An object of the present invention is to provide a larger
capacitance while the requirements of alignment allowance for the
alignment of an opening for a capacitor contact and a bit line
contact, and of electric isolation from an adjacent conducting
films.
[0011] The above-described object is achieved by a semiconductor
device comprising: a MOSFET including a pair of impurity diffused
regions formed on both sides of a gate formed on a semiconductor
substrate: an insulation film covering a top of the MOSFET, a
through-hole opened on one of the impurity diffused regions being
formed in the insulation film; and a capacitor formed at at least a
part of an inside of the through-hole, the through-hole having a
larger diameter inside than at a surface thereof.
[0012] The above-described object is also achieved by a
semiconductor device comprising: a MOSFET including a pair of
impurity diffused regions formed on both sides of a gate formed on
a semiconductor substrate: an insulation film covering a top of the
MOSFET, a through-hole opened on one of the impurity diffused
regions being formed in the insulation film; and a capacitor formed
at at least a part of an inside of the through-hole, the
through-hole having a larger diameter at an intermediate part
thereof between a surface thereof and a bottom thereof than at the
surface and the bottom thereof.
[0013] The above-described object is also achieved by a method for
fabricating a semiconductor device comprising: a MOSFET forming
step of forming on a semiconductor substrate a MOSFET including a
gate and a pair of impurity diffused regions on both sides of the
gate; an insulation film forming step of forming an insulation film
for covering the MOSFET; a through-hole forming step of forming in
the insulation film a through-hole having a larger diameter inside
than at a surface thereof, the through-hole being opened on one of
the impurity diffused regions; and a capacitor forming step of
forming a capacitor at at least a part of an inside of the
through-hole.
[0014] The above-described object is also achieved by a method for
fabricating a semiconductor device comprising: a MOSFET forming
step of forming on a semiconductor substrate a MOSFET including a
gate and a pair of impurity diffused regions on both sides of the
gate; an insulation film forming step of forming an insulation film
for covering the MOSFET; a through-hole forming step of forming in
the insulation film a through-hole having a larger diameter at an
intermediate part between a surface thereof and a bottom thereof
than the surface and the bottom thereof, the through-hole being
opened on one of the impurity diffused regions; and a capacitor
forming step of forming a capacitor at at least a part of an inside
of the through-hole.
[0015] The above-described object is also achieved by a method for
fabricating a semiconductor device comprising: a MOSFET forming
step of forming on a semiconductor substrate a MOSFET including a
gate and a pair of impurity diffused regions on both sides of the
gate; an insulation film forming step of forming a plurality of
insulation films being laminated for covering the MOSFET; a
through-hole forming step of forming in the insulation films a
through-hole having a larger diameter inside than at a surface
thereof, the through-hole being opened on one of the impurity
diffused regions; and a capacitor forming step of forming a
capacitor at at least a part of an inside of the through-hole.
[0016] In the above-described method for fabricating the
semiconductor device, it is preferable that the insulation film
forming step includes a step of forming a first insulation film,
and a step of forming on the first insulation film a second
insulation film having etching characteristics different from those
of the first insulation film; and the through-hole forming step
includes a step of forming in the first insulation film and the
second insulation film the through-hole having substantially the
same opening diameter, and a step of retreating the first
insulation film inside the through-hole by the use of an etchant
having a higher etching rate with respect to the first insulation
film than with respect to the second insulation film.
[0017] The above-described object is also achieved by a method for
fabricating a semiconductor device comprising: a MOSFET forming
step of forming on a semiconductor substrate a MOSFET including a
gate and a pair of impurity diffused regions on both sides of the
gate; an insulation film forming step of forming a plurality of
insulation films being laminated for covering the MOSFET; a
through-hole forming step of forming in the insulation films a
through-hole having a larger diameter at an intermediate part
between a surface thereof and a bottom thereof than the surface and
the bottom thereof, the through-hole being opened on one of the
impurity diffused regions; and a capacitor forming step of forming
a capacitor at at least a part of an inside of the
through-hole.
[0018] In the above-described method for fabricating the
semiconductor device, it is preferable that the insulation film
forming step includes a step of forming a first insulation film, a
step of forming on the first insulation film a second insulation
film having etching characteristics different from those of the
first insulation film, and a step of forming on the second
insulation film a third insulation film having etching
characteristics different from those of the second insulation film;
and the through-hole forming step includes a step of forming in the
first insulation film, the second insulation film and the third
insulation film the through-hole having substantially the same
opening diameter, and a step of retreating the second insulation
film inside the through-holes by the use of an etchant having a
higher etching rate with respect to the second insulation film than
with respect to the first and the third insulation film.
[0019] In the above-described method for fabricating the
semiconductor device, it is preferable that the insulation film
forming step includes a step of forming a first insulation film, a
step of forming on the first insulation film a second insulation
film having etching characteristics different from those of the
first insulation film, and a step of forming on the second
insulation film a third insulation film having etching
characteristics different from those of the second insulation film;
and the through-hole forming step includes a step of etching the
second and the third insulation films by the use of an etchant
which has a higher etching rate with respect to the second
insulation film than with respect to the third insulation film and
substantially anisotropically contains an isotropic component, and
a step of isotropically etching the first insulation film by the
use of an etchant having a higher etching rate with respect to the
first insulation film than with respect to the second insulation
film.
[0020] In the above-described method for fabricating the
semiconductor device, it is preferable that the etchant for etching
the first insulation film has a higher etching rate with respect to
the second insulation film than with respect to the third
insulation film.
[0021] In the above-described method for fabricating the
semiconductor device, it is preferable that the first insulation
film is a silicon nitride film; the second insulation film is a
silicon oxide film containing boron and/or phosphorus: the third
insulation film is a non-doped silicon oxide film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIGS. 1A and lB are diagrammatic sectional views of the
semiconductor device, which explain the principle of the present
invention.
[0023] FIGS. 2A-2E are sectional views of the semiconductor device
according to a first embodiment of the present invention in the
steps of the method for fabricating the same, which explain the
same and the method for fabricating the same.
[0024] FIGS. 3A and 3B are sectional views of the conventional
semiconductor device, which explain the problems of the
conventional semiconductor device.
DETAILED DESCRIPTION OF THE INVENTION
[0025] The principle of the present invention will be explained
with reference to FIGS. 1A and lB.
[0026] A field oxide film 2 for defining a device region is formed
on a semiconductor substrate 1. A gate 4 of a memory cell
transistor is formed on a gate oxide film 3 in the device region
defined by the field oxide film 2. A part of the gate 4 is extended
on the field oxide film 2. An insulation film 5 is formed on the
side wall and the upper surface of the gate 4. On the semiconductor
substrate 1 with the memory cell transistor including the gate
covered with the insulation file 5 are formed a silicon nitride
(Si.sub.3N.sub.4) film 6 which is to function as an etching
stopper, an inter-layer insulation film 7 of boro-phospho-silicate
glass (BPSG) film, and inter-layer insulation film 8 of silicon
dioxide (SiO.sub.2) film are formed. A through-hole is formed
through the silicon nitride film 6 and the inter-layer insulation
films 7, 8. The through-hole has a larger diameter in the
inter-layer insulation film 7 than in the silicon nitride film 6
and the inter-layer insulation film 8. A storage electrode 9 of a
capacitor connected to the semiconductor substrate 1 is formed on
the inside wall and the bottom of the through-hole. An opposed
electrode 11 of the capacitor is formed on the surface of the
storage electrode 9 through a dielectric film 10.
[0027] As described above, the present invention is characterized
in that, as shown in FIG. 1A, the through-hole for the capacitor
contact has a larger diameter at an intermediate part thereof
between the opening (the surface) and the contact (the bottom) than
at the opening and the contact thereof.
[0028] An inside diameter of the through-hole can be increased up
to a size which permits electric isolation from the adjacent
conducting film without considering an alignment allowance.
[0029] The through-hole is formed by forming the inter-layer
insulation film of two or more insulation layers having etching
rates different from each others anisotropically etching the
inter-layer insulation film, and isotropically etching the
inter-layer insulation film by the use of an etching rate
difference between insulation layers.
[0030] A configuration of the through-hole can be decided
arbitrarily depending on a structure of the inter-layer insulation
film, and can be as shown in FIG. 1B.
[0031] As described above, the capacitor can have an increased
capacitance while the requirements of an alignment allowance for
alignment of the opening and the contact of the capacitor contact,
and electric isolation from the adjacent conducting film are
met.
[0032] [A First Embodiment]
[0033] FIGS. 2A-2E are explanatory views of a first embodiment of
the present invention.
[0034] As shown in FIG. 2A, a 200 nm-thick field oxide film 2 is
formed on a p-type silicon (p-Si) substrate 1 by local oxidation
method, and an about 7 nm-thick gate oxide film 3 is formed by
thermal oxidation in an active region surrounded by the field oxide
film 2.
[0035] Then, a 150 nm-thick polycrystalline silicon film 4
containing phosphorus is grown by chemical vapor deposition (CVD)
method, and a 100 nm-thick SiO.sub.2 film 5A is grown on the
polycrystalline silicon film 4. Then, the polycrystalline silicon
film 4 and the SiO.sub.2 film 5A are patterned by lithography step
and anisotropic etching to form a gate 4 of a MOSFET.
[0036] Then, with the gate 4 and the field oxide film 2 as a mask,
a 1E14 cm.sup.-2 dose of phosphorus ions (P.sup.+) is implanted at
a 20 keV energy to form a source/drain diffused layer 1A of the
MOSFET.
[0037] As shown in FIG. 2B, a 100 nm-thick SiO.sub.2 film is grown
and is subjected to anisotropic etching to form a sidewall spacer
5.
[0038] As shown in FIG. 2C, a 100 nm-thick Si.sub.3N.sub.4 film 6
and a 2 .mu.m-thick BPSG film 7 are grown by CVD method.
[0039] Then, the BPSG film 7 is reflowed by a thermal treatment for
about 15 minutes in a 850.degree. C. nitrogen atmosphere to
planarize the surface of the substrate.
[0040] It is possible that a SiO.sub.2 film may be provided below
the Si.sub.3N.sub.4 film 6.
[0041] Then, a 200 nm-thick SiO.sub.2 film 8 is grown by CVD
method. The SiO.sub.2 film 9 may function as a hard mask for
forming a through-hole. A conducting film, e g. a polycrystalline
silicon film, may be also applicable for the hard mask, but in this
case it should be noted that a capacitor and a bit line do not
short-circuit with each other.
[0042] Then, a resist pattern for forming the through-hole is
formed by photolithography step.
[0043] Then, the SiO.sub.2 film 8 and the BPSG film 7 are etched
with an etching gas (e.g., C.sub.4F.sub.8+Ar+CO+O.sub.2) having an
etching selectivity with respect to the Si.sub.3N.sub.4 film 6.
Then, the Si.sub.3N.sub.4 film 6, which has functioned as the
etching stopper is anisotropically etched to form the through-hole
13.
[0044] Then, the BPSG film 7 is selectively etched to be retreated
by the use of a etching rate difference by isotopic etching, such
as hydrofluoric acid treatment or others to form a larger-diameter
portion in the through-hole. The larger-diameter portion may have a
size which permits electric isolation from the adjacent conducting
film.
[0045] The through-hole for exposing the source/drain diffused
region 1A is extended on the gate 4. Unless the Si.sub.3N.sub.4
film 6 is etched under good control, a storage electrode to be
formed in the through-hole and the gate 4 short-circuit with each
other. This must be kept in mind.
[0046] In a case that a contact diameter is large, or a
disalignment in the photolithography is large, the through-hole is
adversely extended even on the field oxide film. In etching the
Si.sub.3N.sub.4 film 6, a projection of the capacitor in the field
oxide film 2 as shown in FIG. 3A is formed, and dielectric
breakdown of the dielectric film of the capacitor tends to occur
due to electric field concentration. The projection must be
avoided. A size of the contact is thus limited, and a contact
diameter is generally determined by both an alignment allowance and
the electric isolation.
[0047] AS shown in FIG. 2D, a 100 nm-thick polycrystalline silicon
film containing phosphorus is grown by CVD method. The
polycrystalline silicon film except that inside the through-holes
13 is removed by mechanical chemical polishing to form the storage
electrodes 9 of the capacitors in respective through-holes 13.
Reference numeral 14 is a lead portion for a bit line.
[0048] A 5 nm-thick Si.sub.3N.sub.4 film 10 is grown on the surface
of the storage electrode 9 by CVD method. Then, the Si.sub.3N.sub.4
film 10 is oxidized to form the dielectric film 10 of a silicon
oxynitride film. Then, a 100 nm-thick polycrystalline silicon film
containing phosphorus is grown to form the opposed electrode 11 of
the capacitor.
[0049] Then, the polycrystalline silicon film is etched by
lithography step to form an opening 15 of the Si.sub.3N.sub.4 film
of the lead portion of a bit line.
[0050] As shown in FIG. 2E, a 350 nm-thick BPSG film 16 is grown on
the entire surface of the substrate by CVD method. Then, the BPSG
film 16 is reflowed under the above-described conditions to
planarize the surface of the substrate.
[0051] It is possible that an SiO.sub.2 film is grown in place of
the BPSG film and is planarized by mechanical chemical
polishing.
[0052] Then, the BPSG film 16 is etched by lithography step to form
an opening 17 in the BPSG film 16 in the lead portion for a bit
line.
[0053] Although a portion of a larger-hole diameter is present
inside the capacitor, the opening of the through-hole has the same
diameter as the conventional opening, and an alignment allowance of
the bit line contact is as conventional.
[0054] Then, Ti film, TiN film and W film are grown by CVD method
in the stated order and patterned by lithography step to form a bit
line 18.
[0055] Thus, hole diameters of the opening and the contact are
defined in accordance with the requirements of an alignment
allowance and electric isolation, but a through-hole whose inside
diameter is determined by the requirement of electric isolation
alone is formed, whereby the capacitor can easily have an increased
capacitance with the conventional alignment allowance.
[0056] [A Second Embodiment]
[0057] The second embodiment is different from the first embodiment
in the formation of the through-hole of the first embodiment shown
in FIG. 2C.
[0058] As shown in FIG. 2C, a resist pattern for forming a
through-hole is formed. Then, an SiO.sub.2 film 8 and a BPSG film 7
are etched with an etching gas having a etching selectivity with
respect to an Si.sub.3N.sub.4 film 6. Here the etching gas which
has an etching rate having a relationship of
BPSG>SiO.sub.2>Si.sub.3N.sub.4,
[0059] and is anisotropic and has a trace of an isotopic component,
e.g., C.sub.4F.sub.8+Ar+CO+O.sub.2, is used, whereby the BPSC film
7 is a little transversely extended. An extension depends on a film
thickness of the BPSG film 7.
[0060] Then, the Si.sub.3N.sub.4 film 6 is isotopically etched to
form a through-hole 13 for exposing a source/drain diffused region
1A of a MOSFET.
[0061] In a case that the Si.sub.3N.sub.4 film 6 is isotopically
etched, an etching gas having an etching rate having a relationship
of
Si.sub.3N.sub.4>BPSG>SiO.sub.2,
[0062] e.g., SF.sub.6+HBr, is used, and in a case that in etching
the SiO.sub.2 film 8 and the BPSG film 7, the BPSG fiLm 7 is
transversely much extended, the through-hole 13 has a configuration
having a larger diameter inside as shown in FIG. 1A.
[0063] In a case that a transverse extension is small, the
through-hole 13 has a reversely tapered configuration as shown in
FIG. 1B. In this case, because the etching step of increasing an
inside diameter also etches the Si.sub.3N.sub.4 film 6, no addition
is made to a step number.
[0064] [A Third Embodiment]
[0065] In the first and the second embodiments, the capacitor and
the lead portion for a bit line are concurrently formed, but the
lead portion for a bit line may be opened after the capacitor is
formed.
[0066] The contact of the capacitor is formed by self-alignment
with the gate but may be formed by the usual alignment.
[0067] [A Fourth Embodiment]
[0068] In the first and the second embodiments, the capacitor and
the lead portion for a bit line are concurrently opened, but the
capacitor may be formed after the lead portion for a bit line is
opened and the bit line is formed.
[0069] The contact of the capacitor is formed by self-alignment
with the gate but may be formed by the usual alignment.
[0070] In forming the through-hole in the inter-layer insulation
film by etching, the BPSG film on the Si.sub.3N.sub.4 film is
anisotropically etched up to midway, then isotopically etched and
again anisotropically etched to thereby form a larger-diameter in
the through-hole. It is possible to further repeat the
anisotropical etching and the isotopic etching to thereby form a
plurality of a larger diameter. In this case, to define a diameter
of the opening in the surface, the initial etching is
anisotropic.
[0071] According to the present invention, the capacitor can have
an increase capacitance while the requirements of an alignment
allowance for alignment of the opening of the capacitor contact and
the bit line contact and electric isolation from the adjacent
conducting film.
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