U.S. patent application number 09/218010 was filed with the patent office on 2002-01-03 for method for manufacturing semiconductor device.
Invention is credited to KITAGURO, KOICHI, SAKAMOTO, KAZUHISA.
Application Number | 20020001925 09/218010 |
Document ID | / |
Family ID | 18446657 |
Filed Date | 2002-01-03 |
United States Patent
Application |
20020001925 |
Kind Code |
A1 |
SAKAMOTO, KAZUHISA ; et
al. |
January 3, 2002 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Abstract
The present invention is characterized by providing epitaxial
growth of a semiconductor layer on the surface of a wafer not
provided with mirror finishing and having irregularity, introducing
impurities having different conductivity type in the epitaxially
grown semiconductor layer to form at least a pn junction, and
further providing rapid thermal anneal by rapid heating-up and
rapid cooling-down in any step in the manufacturing process. By so
processing, there can be obtained a semiconductor device having
high speed switching characteristics in stable manner without
causing problems in manufacturing process such as diffusion of
heavy metal or irradiation of corpuscular ray.
Inventors: |
SAKAMOTO, KAZUHISA;
(KYOTO-SHI, JP) ; KITAGURO, KOICHI; (KYOTO-SHI,
JP) |
Correspondence
Address: |
ARENT FOX KINTNER PLOTKIN & KAHN PLLC
1050 CONNECTICUT AVENUE NW SUITE 600
WASHINGTON
DC
20036-5339
US
|
Family ID: |
18446657 |
Appl. No.: |
09/218010 |
Filed: |
December 22, 1998 |
Current U.S.
Class: |
438/508 ;
257/E21.318; 257/E21.381; 438/507; 438/509 |
Current CPC
Class: |
C30B 25/18 20130101;
H01L 21/3221 20130101; H01L 29/66303 20130101 |
Class at
Publication: |
438/508 ;
438/507; 438/509 |
International
Class: |
C30B 001/00; H01L
021/20; H01L 021/36 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 25, 1997 |
JP |
9-355968 |
Claims
What is claimed is:
1. A method for manufacturing a semiconductor device comprising:
(a) providing epitaxial growth of a semiconductor layer on a
surface of a sub-wafer not provided with mirror finishing, (b)
introducing impurities having different conductivity type in said
epitaxially grown semiconductor layer to form at least a pn
junction, and (c) further providing rapid thermal anneal by rapid
heating-up and rapid cooling-down in any step in a manufacturing
process.
2. The manufacturing method according to claim 1, wherein a surface
of said sub-wafer is provided with wet chemical etching to form
said surface, and said semiconductor layer is epitaxially grown on
said surface.
3. The manufacturing method according to claim 1, wherein a surface
of said sub-wafer surface is polished with a polishing material of
more than 2 g m to form said surface, and said semiconductor layer
is epitaxially grown on said surface.
4. The manufacturing method according to claim 1, wherein said
surface of said sub-wafer is formed to a roughness of 0.001-0.5
.mu.m in microroughness, and said rapid thermal anneal is carried
out at 700-900.degree. C.
5. The manufacturing method according to claim 4, wherein said
roughness is 0.01-0.5 .mu.m.
6. The manufacturing method according to claim 1, wherein said
rapid thermal anneal by rapid heating-up and rapid cooling-down is
carried out after a heat treatment step in said manufacturing
process.
7. The manufacturing method according to claim 1, wherein said
rapid thermal anneal is carried out by irradiation of optical lamp
or high frequency band irradiation.
8. The manufacturing method according to claim 1, wherein a
transistor is formed by steps comprising: forming a collector
region by growing epitaxially said semiconductor layer; forming a
base region by introducing said impurities having different
conductivity type to said semiconductor layer; and forming an
emitter region by introducing same conductivity type impurities as
said semiconductor layer into said base region.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a method for manufacturing
a semiconductor device such as diode, transistor, thyristor,
insulated gate bipolar transistor (IGBT), MOSFET, and the like,
having high speed switching characteristics as well as high
electric characteristics.
[0002] In order to obtain high speed switching response
characteristics with a semiconductor device having pn junction,
there has been a known method for reducing the lifetime of small
number of carriers by diffusing heavy metals such as gold or
platinum, or by irradiating corpuscular rays like electron ray,
X-ray, proton, and the like.
[0003] The method for diffusing the heavy metals such as gold or
platinum on a semiconductor layer has been studied for long, but
due to the difficulty of control of the diffusion amount and
homogenizing, so the method involves a problem of no satisfactory
correlation (h.sub.FE-t.sub.stg) between the current amplification
rate (hFE) and the storage time (t.sub.stg) in the transistor or
the like. Furthermore, it is necessary to take care of the
prevention of soiling of apparatus such as a post-treatment
furnace, and process control is also laborious.
[0004] Furthermore, the method of irradiating corpuscular ray is to
reduce the lifetime of the carrier because the corpuscular ray
having high energy causes a defect to the crystals in the
semiconductor layer and forms a deep level. These crystal defects
are bound by a restriction that they require to be treated in the
course of the latter half of the semiconductor manufacturing
process, as the lifetime of the carrier reinstates to the original
state through the heat treatment at relatively low temperature to
cause loss of effect.
SUMMARY OF THE INVENTION
[0005] An object of the present invention is to provide a method
for manufacturing a semiconductor device having high speed
switching characteristics in stable manner without causing problems
in manufacturing process such as diffusion of heavy metal or
irradiation of corpuscular ray.
[0006] As a result of the strenuous study continued by the present
inventors to obtain a semiconductor device which can give high
speed switching characteristics in a stabilized condition, it has
been found that, by providing epitaxial growth of a semiconductor
layer on a wafer not provided with mirror surface finish but having
irregularity on the surface, a semiconductor layer having moderate
crystal defects grows, and the crystal defects do not show much
decrease even in the subsequent manufacturing process accompanied
with temperature increase, and moreover, the crystal defects can be
stabilized by providing heat treatments by rapid heating-up up and
rapid cooling-down, thereby making it possible to accelerate the
switching speed without causing any problem to the electric
characteristics.
[0007] The semiconductor manufacturing method of the present
invention is characterized by providing epitaxial growth of a
semiconductor layer on a surface of a sub-wafer not provided with
mirror finishing, introducing impurities having different
conductivity type in said epitaxially grown semiconductor layer to
form at least a pn junction, and further providing rapid thermal
anneal by rapid heating-up and rapid cooling-down in any step in a
manufacturing process.
[0008] The sub-wafer not provided with mirror surface referred to
here is one obtained by providing a surface treatment by wet
chemical etching only after slicing to a wafer from an ingot, or,
even in case of polishing with a polishing material, by making the
final polishing with a polishing material larger than 2 .mu.m in
the final polishing, which means the wafer to be obtained by not
being provided with polishing with a polishing material of no less
than 2 .mu.m in the final polishing. The term of rapid thermal
anneal (RTA) by rapid heating-up and by rapid cooling-down means
the heat treatment by heating with rapid temperature elevation rate
and cooling with rapid temperature descending rate, which means the
heat treatment capable, for example, of increasing the temperature
within about 1 minute for heating from room temperature to about
850.degree. C. and cooling in about the same rate. The method
includes a method of charging the object on a boat having small
thermal capacity rapidly in a heating furnace of predetermined
temperature, and a method of heating by means of optical lamp such
as an infrared lamp, discharge lamp, laser beam lamp, or by high
frequency irradiation.
[0009] By providing the sub-wafer surface with wet chemical
treatment, or by polishing with a polishing material of more than 2
.mu.m, the surface of the above sub-wafer is formed, and by
epitaxially growing the above semiconductor layer on the surface,
the surface treatment of sub-wafer can be made in a short time to
give a semiconductor device having rapid switching speed without
requiring time-taking polishing.
[0010] Concretely, the sub-wafer surface is processed to surface
roughness of 0.001-0.5 .mu.m, more preferably of 0.01-0.5 .mu.m, in
a microroughness, and the heat treatment (RTA) may be carried out
at 700-900.degree. C. The microroughness means, as shown in FIG. 3,
the maximum variation amount between the peak and the trough in
about 500 .mu.m length.
[0011] It is preferable for the heat treatment (RTA) by rapid
heating-up and rapid cooling-down to be carried out after the
annealing step in the semiconductor device manufacturing process in
the sense of making the crystal defect assured. The above rapid
heating-up may be carried out by irradiation of light lamp or by
high frequency irradiation.
[0012] By allocating the epitaxially grown semiconductor layer to
be a collector region, the region formed by introducing the
impurities having different conductivity type into the
semiconductor layer to be a base region, and introducing the same
conductivity type impurities as the semiconductor layer into the
base region to form an emitter region, a transistor having
increased switching speed can be formed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a view to show a manufacturing step of an
embodiment in the semiconductor device manufacturing method of the
present invention;
[0014] FIG. 2 is a view showing the relation of the storage time
t.sub.stg to the direct current amplification rate hFE of the
transistor manufactured by an embodiment of the manufacturing
method of the present invention;
[0015] FIG. 3 is an explanatory view of the microroughness.
DETAILED DESCRIPTION
[0016] The semiconductor manufacturing method of the present
invention is to finish the surface of the sub-wafer which is for
example sliced from the ingot by wet chemical etching process or
the like so as to make, at first, the surface roughness of the
slice face la on one side of the sub-wafer 1 about 0.001-0.5 .mu.m,
more preferably about 0.01-0.5 .mu.m, as shown in FIG. 1(a). The
thickness of this sub-wafer is to be more than 10 .mu.m, preferably
about 50-150 .mu.m, more preferably about 80-120 .mu.m. In FIG. 1,
the surface roughness of the sub-wafer 1 is illustrated in
exaggerated manner. The original surface of sliced sub-wafer is
very rough, but as the wet etching amount is increased, the surface
is flattened. Thus, by adjusting the etching amount according to
the roughness of the sliced condition of surface, the etching
amount may be adjusted to give the surface roughness as exemplified
above. Even in the case of not relying on the wet chemical etching,
or in case of polishing with a polishing material after providing
chemical etching to a certain extent, the irregular surface as
mentioned above can be obtained by performing polishing with a
polishing material of more than 2 .mu.m. The amount of this
irregularity can be known for example by a probe method of bringing
a probe into contact with the surface or by measuring the
reflectivity of laser beam. The surface roughness of the
conventional mirror face finishing when measured by this method is
no more than 0.1 nm in micro-roughness.
[0017] Next, as shown in FIG. 1 (b), for example an n-type Si is
epitaxially grown on the surface la of the sub-wafer 1 to grow a
semiconductor layer 2 by for example 10 -60 .mu.m. The thickness of
the semiconductor layer 2 to be epitaxially grown may differ
depending on the objective semiconductor device, and for example in
case of manufacturing a power transistor, the layer is to be grown
to a thickness of about 30 .mu.m. In case the thickness of the
semiconductor layer 2 to be epitaxially grown is thin, preferably
the sub-wafer 1 is provided with surface treatment to come to a
smaller surface roughness of the range mentioned above. This is
because the thicker the thickness of the epitaxial growth layer is,
irregularity becomes less on the surface side to show smaller
crystal defect, but on the other hand when the growth layer is too
thin, the irregularity is not sufficiently reduced to flattening
but too large crystal defect causes lowering of the electric
characteristics of the device.
[0018] Continuously, when, as shown in FIG. 1 (c), by introducing
for example p-type impurities by diffusion or ion injection or the
like, forming a base region 3, and further introducing the n-type
impurities in the similar manner to form an emitter region, a
transistor is formed on a sub-wafer 1 in matrix form.
[0019] Subsequently, or after forming for example a base region in
the preceding manufacturing process, the transistor is contained in
a furnace in which rapid heating-up is made by raising the
temperature to about 650-1150.degree. C., followed by allowing to
stand for about 10 minutes. Further, after being kept in the
furnace for about 1 minute, the sub-wafer 1 is taken out from the
furnace to room temperature and subjected to rapid cooling-down.
The heat treatment (RTA) by rapid heating-up and rapid cooling-down
can be realized by placing the object on a boat having small
thermal capacity and taking in and out of the furnace whose
temperature is elevated to a predetermined level, or by heating by
irradiation of light of infrared lamp, discharge lamp, laser beam,
etc. or irradiation of heat beam such as a high frequency
irradiation direct to the sub-wafer. In short, heating may be made
so as to bring the predetermined temperature to the range of
650-1150.degree. C. in about 1 minute by a rapid heating-up device,
and heat treatment may be applied at the same temperature for 1
second or in the period of several seconds to 10 minutes.
[0020] The rapid heating-up and rapid cooling-down are made to
bring back to the original condition of crystal defect by thermal
impact, even if the crystal defect is mended by diffusion process
or formation of thermal oxide film, as described later. Preferably
the RTA treatment is to be made after completion of the high
temperature heat treatment such as diffusion processing. However,
as described later, since the base of the crystal defect is a
mechanical one based on the irregularity of the surface of the
sub-wafer 1, the crystal defect is not eliminated by heat
treatment, and as it is possible to make the crystal defect more
assured by thermal shock to be exerted by RTA, this is sufficiently
effective even without providing the subsequent process.
[0021] Thereafter, though not illustrated, a contact hole is formed
on the insulating film on the wafer surface, a metal for electrode
such as aluminum is coated by sputtering or vacuum deposition
process, and patterning is provided to form an electrode. And, by
dividing the product into the respective chips, the semiconductors
of the present invention are obtainable.
[0022] According to the present invention, the semiconductor layer
is epitaxially grown on a wafer form semiconductor substrate in
sub-wafer condition under the irregular surface condition without
having the mirror surface finish. Accordingly, the epitaxially
grown semiconductor layer does not become perfect crystal
condition, and crystal defect occurs. When the crystal defects are
too much the electric characteristics of transistor and the like
are deteriorated, but it has been known that, when the above
irregularity is about 0.001-0.5 .mu.g of microroughness no
abnormality occurs in the electric characteristics. On the other
hand, the crystal defect tends to shorten the life of small number
carrier by forming the recombination center of carrier. Though
there has hitherto been used a method of forming a recombination
center of carrier by diffusion of heavy metal or irradiation of
electron beam in a transistor or the like to shorten the life .tau.
of the small number carrier, thereby accelerating the switching
speed, the above method shows the same action as said conventional
method.
[0023] The storage time t.sub.stg which significantly affects the
switching speed is represented by the following expression:
[0024] t.sub.stg=.tau..multidot.ln[I.sub.B.multidot..tau./Q.sub.s ]
(1)
[0025] where, .tau. is a life of the small number carriers to be
injected in the base; Q.sub.s is a base charge to provide a
saturation mode; and I.sup.B is base current, respectively. From
the above expression (1) it can be seen that the storage time
t.sub.stg depends on the life .tau. of the small number carriers.
Sine, in the present invention, crystal defects are formed by the
irregularity of the sub-wafer as described above to become the
capture center or recombination center, the life .tau. of the small
number carriers as described above becomes short. As a result, the
storage time t.sub.stg becomes small.
[0026] The recombination center based on the crystal defect
according to the present invention is to be formed by a mechanical
configuration based on the irregularity of the substrate surface at
the time of epitaxially growing the semiconductor layer. Because of
this, the center is less apt to be mended by the subsequent
annealing treatment or the like. Though diffusion of impurities and
annealing treatments are provided in various processes, different
from the conventional process of causing the crystal defects to be
formed subsequently based on heavy metal diffusion or electron beam
irradiation, the present invention process is to provide formation
of the crystal defects based on the mechanical configuration, so
that there is less case for the reinstatement to be made by the
subsequent diffusion step or annealing step. Even under such
condition, if a long time heat treatment is provided in a diffusion
step or the like, some defects are repaired to lessen the crystal
defects. Since, even in this case the mechanical structure itself
of irregularity does not show change, the crystal defects based on
the irregularity can be induced again by providing rapid thermal
annealing to give thermal shock by rapid heating-up and rapid
cooling-down, and in the semiconductor layer provided with thermal
shock there occurs less tendency to have repair of crystal defect
even by subsequent annealing treatment. For this reason, by
providing a rapid thermal treatment, stable recombination center
can be secured, and semiconductor device which shows faster and
stable switching time is obtainable.
[0027] Using a wafer of a condition sliced from the ingot and
provided with etching of about 120 .mu.m by wet chemical etching as
mentioned above, a power transistor is manufactured, whose relation
of storage time and direct current amplification rate h.sub.FE is
compared with that of the power transistor manufactured by using
the conventional mirror surface finished wafer, and the results are
shown in FIG. 2. FIG. 2 shows a direct current amplification rate
h.sub.FE in the horizontal axis abscissa and the storage time
t.sub.stg in the vertical axis, where P shows the data of the
present invention transistor and Q of the conventional transistor.
It can be seen that, according to the present invention, the
storage time is smaller and the switching time is shorter than
those of the transistor manufactured by using the conventional
mirror face finished wafer.
[0028] According to the present invention, by forming a crystal
defect based on mechanical configuration and further making the
crystal defect assured by further rapid thermal anneal, the
lifetime of the carrier is shortened with the crystal defect
utilized as a center of recombination and the switching speed is
made high, so that it does not occur that the crystal defect is
mended by diffusion treatment or annealing treatment and the
switching time is fluctuated to become unstable. As a result, there
can be obtained a semiconductor device which has always stabilized
and high speed switching speed.
[0029] Furthermore, while conventionally there had been required a
long time polishing process for producing a mirror surface, the
time for processing can be omitted to realize cost reduction and
improvement of switching speed.
[0030] Although preferred example have been described in some
detail, it is to be understood that certain changes can be made by
those skilled in the art without departing from the spirit and
scope of the invention as defined by the appended claims.
* * * * *